From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54439) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgkua-0004oy-OD for qemu-devel@nongnu.org; Wed, 22 Feb 2017 23:21:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cgkuZ-0008Ko-Gi for qemu-devel@nongnu.org; Wed, 22 Feb 2017 23:21:48 -0500 Message-ID: <1487823698.23895.3.camel@gmail.com> From: Suraj Jitindar Singh Date: Thu, 23 Feb 2017 15:21:38 +1100 In-Reply-To: <20170223034710.GJ12577@umbus.fritz.box> References: <1487563478-22265-1-git-send-email-sjitindarsingh@gmail.com> <1487563478-22265-4-git-send-email-sjitindarsingh@gmail.com> <20170220073146.GC661@balbir.ozlabs.ibm.com> <20170223034710.GJ12577@umbus.fritz.box> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , Balbir Singh Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, sam.bobroff@au1.ibm.com On Thu, 2017-02-23 at 14:47 +1100, David Gibson wrote: > On Mon, Feb 20, 2017 at 06:31:46PM +1100, Balbir Singh wrote: > > > > On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh > > wrote: > > > > > > The logical partitioning control register controls a threads > > > operation > > > based on the partition it is currently executing. Add new > > > definitions and > > > update the mask used when writing to the LPCR based on the POWER9 > > > spec. > > > > > > Signed-off-by: Suraj Jitindar Singh > > > --- > > >  target/ppc/cpu.h            | 18 ++++++++++++++++++ > > >  target/ppc/mmu-hash64.c     |  8 ++++++++ > > >  target/ppc/translate_init.c | 24 ++++++++++++++++++------ > > >  3 files changed, 44 insertions(+), 6 deletions(-) > > > > > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > > > index bb96dd5..425e79d 100644 > > > --- a/target/ppc/cpu.h > > > +++ b/target/ppc/cpu.h > > > @@ -384,12 +384,19 @@ struct ppc_slb_t { > > >  #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT) > > >  #define LPCR_VRMASD_SHIFT (63 - 16) > > >  #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT) > > > +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask > > > */ > > > +#define LPCR_PECE_U_SHIFT (63 - 19) > > > +#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT) > > > +#define LPCR_HVEE         (1ull << (63 - 17)) /* Hypervisor Virt > > > Exit Enable */ > > >  #define LPCR_RMLS_SHIFT   (63 - 37) > > >  #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT) > > >  #define LPCR_ILE          (1ull << (63 - 38)) > > >  #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt > > > location */ > > >  #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT) > > > +#define LPCR_UPRT         (1ull << (63 - 41)) /* Use Process > > > Table */ > > > +#define LPCR_EVIRT        (1ull << (63 - 42)) /* Enhanced > > > Virtualisation */ > > >  #define LPCR_ONL          (1ull << (63 - 45)) > > > +#define LPCR_LD           (1ull << (63 - 46)) /* Large > > > Decrementer */ > > >  #define LPCR_P7_PECE0     (1ull << (63 - 49)) > > >  #define LPCR_P7_PECE1     (1ull << (63 - 50)) > > >  #define LPCR_P7_PECE2     (1ull << (63 - 51)) > > > @@ -398,11 +405,22 @@ struct ppc_slb_t { > > >  #define LPCR_P8_PECE2     (1ull << (63 - 49)) > > >  #define LPCR_P8_PECE3     (1ull << (63 - 50)) > > >  #define LPCR_P8_PECE4     (1ull << (63 - 51)) > > > +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask > > > */ > > > +#define LPCR_PECE_L_SHIFT (63 - 51) > > > +#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT) > > > +#define LPCR_PDEE         (1ull << (63 - 47)) /* Privileged > > > Doorbell Exit EN */ > > > +#define LPCR_HDEE         (1ull << (63 - 48)) /* Hyperv Doorbell > > > Exit Enable */ > > > +#define LPCR_EEE          (1ull << (63 - 49)) /* External Exit > > > Enable        */ > > > +#define LPCR_DEE          (1ull << (63 - 50)) /* Decrementer > > > Exit Enable     */ > > > +#define LPCR_OEE          (1ull << (63 - 51)) /* Other Exit > > > Enable           */ > > >  #define LPCR_MER          (1ull << (63 - 52)) > > > +#define LPCR_GTSE         (1ull << (63 - 53)) /* Guest > > > Translation Shootdown */ > > >  #define LPCR_TC           (1ull << (63 - 54)) > > > +#define LPCR_HEIC         (1ull << (63 - 59)) /* HV Extern > > > Interrupt Control */ > > >  #define LPCR_LPES0        (1ull << (63 - 60)) > > >  #define LPCR_LPES1        (1ull << (63 - 61)) > > >  #define LPCR_RMI          (1ull << (63 - 62)) > > > +#define LPCR_HVICE        (1ull << (63 - 62)) /* HV > > > Virtualisation Int Enable */ > > >  #define LPCR_HDICE        (1ull << (63 - 63)) > > This patch is missing > > > > #define LPCR_HR (1ull << (63 - 43)) /* HV uses Radix > > Tree Translation */ > > > > See arch/powerpc/include/asm/reg.h in the Linux kernel.  > Suraj, if you're resending anyway, add this.  It doesn't matter for > non-powernv, of course, but we might as well put the #define in to > document it. > Yeah adding a define can't hurt