From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (ozlabs.org [103.22.144.67]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vTwNL4dXpzDqq5 for ; Fri, 24 Feb 2017 13:41:38 +1100 (AEDT) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vTwNK4LTSz9s7K for ; Fri, 24 Feb 2017 13:41:37 +1100 (AEDT) Message-ID: <1487904081.23576.254.camel@kernel.crashing.org> Subject: [PATCH v5 2/12] drm/ast: Handle configuration without P2A bridge From: Benjamin Herrenschmidt To: dri-devel@lists.freedesktop.org Cc: linuxppc-dev@ozlabs.org, airlied@redhat.com, "Y . C . Chen" , Joel Stanley Date: Fri, 24 Feb 2017 13:41:21 +1100 In-Reply-To: References: <20170223225357.9572-1-benh@kernel.crashing.org> <20170223225357.9572-2-benh@kernel.crashing.org> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , The ast driver configures a window to enable access into BMC memory space in order to read some configuration registers. If this window is disabled, which it can be from the BMC side, the ast driver can't function. Closing this window is a necessity for security if a machine's host side and BMC side are controlled by different parties; i.e. a cloud provider offering machines "bare metal". A recent patch went in to try to check if that window is open but it does so by trying to access the registers in question and testing if the result is 0xffffffff. This method will trigger a PCIe error when the window is closed which on some systems will be fatal (it will trigger an EEH for example on POWER which will take out the device). This patch improves this in two ways: - First, if the firmware has put properties in the device-tree containing the relevant configuration information, we use these. - Otherwise, a bit in one of the SCU scratch registers (which are readable via the VGA register space and writeable by the BMC) will indicate if the BMC has closed the window. This bit has been defined by Y.C Chen from Aspeed. If the window is closed and the configuration isn't available from the device-tree, some sane defaults are used. Those defaults are hopefully sufficient for standard video modes used on a server. Signed-off-by: Russell Currey Signed-off-by: Benjamin Herrenschmidt -- v2. [BenH] - Reworked on top of Aspeed P2A patch - Cleanup overall detection via a "config_mode" and log the selected mode for diagnostics purposes - Add a property for the SCU straps v3. [BenH] - Moved the config mode detection to a separate functionn - Add reading of SCU 0x40 D[12] to detect the window is closed as to not trigger a bus error by just "trying". (change provided by Y.C. Chen) v4. [BenH] - Only devices with the AST2000 PCI ID have a P2A bridge - Update the P2A presence test to account for VGA only mode as provided by Y.C. Chen. v5. [BenH] - Fixup prefix of OF properties based on Joel Stanley review comments. --- drivers/gpu/drm/ast/ast_drv.h | 6 +- drivers/gpu/drm/ast/ast_main.c | 264 +++++++++++++++++++++++++---------------- drivers/gpu/drm/ast/ast_post.c | 7 +- 3 files changed, 168 insertions(+), 109 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index 7abda94..3bedcf7 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -113,7 +113,11 @@ struct ast_private { struct ttm_bo_kmap_obj cache_kmap; int next_cursor; bool support_wide_screen; - bool DisableP2A; + enum { + ast_use_p2a, + ast_use_dt, + ast_use_defaults + } config_mode; enum ast_tx_chip tx_chip_type; u8 dp501_maxclk; diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 533e762..fb99762 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -62,13 +62,84 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast, return ret; } +static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) +{ + struct device_node *np = dev->pdev->dev.of_node; + struct ast_private *ast = dev->dev_private; + uint32_t data, jregd0, jregd1; + + /* Defaults */ + ast->config_mode = ast_use_defaults; + *scu_rev = 0xffffffff; + + /* Check if we have device-tree properties */ + if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", + scu_rev)) { + /* We do, disable P2A access */ + ast->config_mode = ast_use_dt; + DRM_INFO("Using device-tree for configuration\n"); + return; + } + + /* Not all families have a P2A bridge */ + if (dev->pdev->device != PCI_CHIP_AST2000) + return; + + /* + * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge + * is disabled. We force using P2A if VGA only mode bit + * is set D[7] + */ + jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); + jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); + if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { + /* Double check it's actually working */ + data = ast_read32(ast, 0xf004); + if (data != 0xFFFFFFFF) { + /* P2A works, grab silicon revision */ + ast->config_mode = ast_use_p2a; + + DRM_INFO("Using P2A bridge for configuration\n"); + + /* Read SCU7c (silicon revision register) */ + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + *scu_rev = ast_read32(ast, 0x1207c); + return; + } + } + + /* We have a P2A bridge but it's disabled */ + DRM_INFO("P2A bridge disabled, using default configuration\n"); +} static int ast_detect_chip(struct drm_device *dev, bool *need_post) { struct ast_private *ast = dev->dev_private; - uint32_t data, jreg; + uint32_t jreg, scu_rev; + + /* + * If VGA isn't enabled, we need to enable now or subsequent + * access to the scratch registers will fail. We also inform + * our caller that it needs to POST the chip + * (Assumption: VGA not enabled -> need to POST) + */ + if (!ast_is_vga_enabled(dev)) { + ast_enable_vga(dev); + DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); + *need_post = true; + } else + *need_post = false; + + + /* Enable extended register access */ + ast_enable_mmio(dev); ast_open_key(ast); + /* Find out whether P2A works or whether to use device-tree */ + ast_detect_config_mode(dev, &scu_rev); + + /* Identify chipset */ if (dev->pdev->device == PCI_CHIP_AST1180) { ast->chip = AST1100; DRM_INFO("AST 1180 detected\n"); @@ -80,12 +151,7 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) ast->chip = AST2300; DRM_INFO("AST 2300 detected\n"); } else if (dev->pdev->revision >= 0x10) { - uint32_t data; - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - - data = ast_read32(ast, 0x1207c); - switch (data & 0x0300) { + switch (scu_rev & 0x0300) { case 0x0200: ast->chip = AST1100; DRM_INFO("AST 1100 detected\n"); @@ -110,26 +176,6 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) } } - /* - * If VGA isn't enabled, we need to enable now or subsequent - * access to the scratch registers will fail. We also inform - * our caller that it needs to POST the chip - * (Assumption: VGA not enabled -> need to POST) - */ - if (!ast_is_vga_enabled(dev)) { - ast_enable_vga(dev); - ast_enable_mmio(dev); - DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); - *need_post = true; - } else - *need_post = false; - - /* Check P2A Access */ - ast->DisableP2A = true; - data = ast_read32(ast, 0xf004); - if (data != 0xFFFFFFFF) - ast->DisableP2A = false; - /* Check if we support wide screen */ switch (ast->chip) { case AST1180: @@ -146,17 +192,12 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) ast->support_wide_screen = true; else { ast->support_wide_screen = false; - if (ast->DisableP2A == false) { - /* Read SCU7c (silicon revision register) */ - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - data = ast_read32(ast, 0x1207c); - data &= 0x300; - if (ast->chip == AST2300 && data == 0x0) /* ast1300 */ - ast->support_wide_screen = true; - if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ - ast->support_wide_screen = true; - } + if (ast->chip == AST2300 && + (scu_rev & 0x300) == 0x0) /* ast1300 */ + ast->support_wide_screen = true; + if (ast->chip == AST2400 && + (scu_rev & 0x300) == 0x100) /* ast1400 */ + ast->support_wide_screen = true; } break; } @@ -220,85 +261,102 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) static int ast_get_dram_info(struct drm_device *dev) { + struct device_node *np = dev->pdev->dev.of_node; struct ast_private *ast = dev->dev_private; - uint32_t data, data2; - uint32_t denum, num, div, ref_pll; + uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; + uint32_t denum, num, div, ref_pll, dsel; - if (ast->DisableP2A) - { + switch (ast->config_mode) { + case ast_use_dt: + /* + * If some properties are missing, use reasonable + * defaults for AST2400 + */ + if (of_property_read_u32(np, "aspeed,mcr-configuration", + &mcr_cfg)) + mcr_cfg = 0x00000577; + if (of_property_read_u32(np, "aspeed,mcr-scu-mpll", + &mcr_scu_mpll)) + mcr_scu_mpll = 0x000050C0; + if (of_property_read_u32(np, "aspeed,mcr-scu-strap", + &mcr_scu_strap)) + mcr_scu_strap = 0; + break; + case ast_use_p2a: + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + mcr_cfg = ast_read32(ast, 0x10004); + mcr_scu_mpll = ast_read32(ast, 0x10120); + mcr_scu_strap = ast_read32(ast, 0x10170); + break; + case ast_use_defaults: + default: ast->dram_bus_width = 16; ast->dram_type = AST_DRAM_1Gx16; ast->mclk = 396; + return 0; } - else - { - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - data = ast_read32(ast, 0x10004); - - if (data & 0x40) - ast->dram_bus_width = 16; - else - ast->dram_bus_width = 32; - if (ast->chip == AST2300 || ast->chip == AST2400) { - switch (data & 0x03) { - case 0: - ast->dram_type = AST_DRAM_512Mx16; - break; - default: - case 1: - ast->dram_type = AST_DRAM_1Gx16; - break; - case 2: - ast->dram_type = AST_DRAM_2Gx16; - break; - case 3: - ast->dram_type = AST_DRAM_4Gx16; - break; - } - } else { - switch (data & 0x0c) { - case 0: - case 4: - ast->dram_type = AST_DRAM_512Mx16; - break; - case 8: - if (data & 0x40) - ast->dram_type = AST_DRAM_1Gx16; - else - ast->dram_type = AST_DRAM_512Mx32; - break; - case 0xc: - ast->dram_type = AST_DRAM_1Gx32; - break; - } - } + if (mcr_cfg & 0x40) + ast->dram_bus_width = 16; + else + ast->dram_bus_width = 32; - data = ast_read32(ast, 0x10120); - data2 = ast_read32(ast, 0x10170); - if (data2 & 0x2000) - ref_pll = 14318; - else - ref_pll = 12000; - - denum = data & 0x1f; - num = (data & 0x3fe0) >> 5; - data = (data & 0xc000) >> 14; - switch (data) { - case 3: - div = 0x4; + if (ast->chip == AST2300 || ast->chip == AST2400) { + switch (mcr_cfg & 0x03) { + case 0: + ast->dram_type = AST_DRAM_512Mx16; break; - case 2: + default: case 1: - div = 0x2; + ast->dram_type = AST_DRAM_1Gx16; break; - default: - div = 0x1; + case 2: + ast->dram_type = AST_DRAM_2Gx16; + break; + case 3: + ast->dram_type = AST_DRAM_4Gx16; + break; + } + } else { + switch (mcr_cfg & 0x0c) { + case 0: + case 4: + ast->dram_type = AST_DRAM_512Mx16; + break; + case 8: + if (mcr_cfg & 0x40) + ast->dram_type = AST_DRAM_1Gx16; + else + ast->dram_type = AST_DRAM_512Mx32; + break; + case 0xc: + ast->dram_type = AST_DRAM_1Gx32; break; } - ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000); } + + if (mcr_scu_strap & 0x2000) + ref_pll = 14318; + else + ref_pll = 12000; + + denum = mcr_scu_mpll & 0x1f; + num = (mcr_scu_mpll & 0x3fe0) >> 5; + dsel = (mcr_scu_mpll & 0xc000) >> 14; + switch (dsel) { + case 3: + div = 0x4; + break; + case 2: + case 1: + div = 0x2; + break; + default: + div = 0x1; + break; + } + ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000); return 0; } diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index 6c5391c..64549ce 100644 --- a/drivers/gpu/drm/ast/ast_post.c +++ b/drivers/gpu/drm/ast/ast_post.c @@ -379,17 +379,14 @@ void ast_post_gpu(struct drm_device *dev) ast_open_key(ast); ast_set_def_ext_reg(dev); - if (ast->DisableP2A == false) - { + if (ast->config_mode == ast_use_p2a) { if (ast->chip == AST2300 || ast->chip == AST2400) ast_init_dram_2300(dev); else ast_init_dram_reg(dev); ast_init_3rdtx(dev); - } - else - { + } else { if (ast->tx_chip_type != AST_TX_NONE) ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ } From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benjamin Herrenschmidt Subject: [PATCH v5 2/12] drm/ast: Handle configuration without P2A bridge Date: Fri, 24 Feb 2017 13:41:21 +1100 Message-ID: <1487904081.23576.254.camel@kernel.crashing.org> References: <20170223225357.9572-1-benh@kernel.crashing.org> <20170223225357.9572-2-benh@kernel.crashing.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C7F66EB97 for ; Fri, 24 Feb 2017 02:41:34 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: linuxppc-dev@ozlabs.org, Joel Stanley , airlied@redhat.com List-Id: dri-devel@lists.freedesktop.org VGhlIGFzdCBkcml2ZXIgY29uZmlndXJlcyBhIHdpbmRvdyB0byBlbmFibGUgYWNjZXNzIGludG8g Qk1DCm1lbW9yeSBzcGFjZSBpbiBvcmRlciB0byByZWFkIHNvbWUgY29uZmlndXJhdGlvbiByZWdp c3RlcnMuCgpJZiB0aGlzIHdpbmRvdyBpcyBkaXNhYmxlZCwgd2hpY2ggaXQgY2FuIGJlIGZyb20g dGhlIEJNQyBzaWRlLAp0aGUgYXN0IGRyaXZlciBjYW4ndCBmdW5jdGlvbi4KCkNsb3NpbmcgdGhp cyB3aW5kb3cgaXMgYSBuZWNlc3NpdHkgZm9yIHNlY3VyaXR5IGlmIGEgbWFjaGluZSdzCmhvc3Qg c2lkZSBhbmQgQk1DIHNpZGUgYXJlIGNvbnRyb2xsZWQgYnkgZGlmZmVyZW50IHBhcnRpZXM7Cmku ZS4gYSBjbG91ZCBwcm92aWRlciBvZmZlcmluZyBtYWNoaW5lcyAiYmFyZSBtZXRhbCIuCgpBIHJl Y2VudCBwYXRjaCB3ZW50IGluIHRvIHRyeSB0byBjaGVjayBpZiB0aGF0IHdpbmRvdyBpcyBvcGVu CmJ1dCBpdCBkb2VzIHNvIGJ5IHRyeWluZyB0byBhY2Nlc3MgdGhlIHJlZ2lzdGVycyBpbiBxdWVz dGlvbgphbmQgdGVzdGluZyBpZiB0aGUgcmVzdWx0IGlzIDB4ZmZmZmZmZmYuCgpUaGlzIG1ldGhv ZCB3aWxsIHRyaWdnZXIgYSBQQ0llIGVycm9yIHdoZW4gdGhlIHdpbmRvdyBpcyBjbG9zZWQKd2hp Y2ggb24gc29tZSBzeXN0ZW1zIHdpbGwgYmUgZmF0YWwgKGl0IHdpbGwgdHJpZ2dlciBhbiBFRUgK Zm9yIGV4YW1wbGUgb24gUE9XRVIgd2hpY2ggd2lsbCB0YWtlIG91dCB0aGUgZGV2aWNlKS4KClRo aXMgcGF0Y2ggaW1wcm92ZXMgdGhpcyBpbiB0d28gd2F5czoKCiAtIEZpcnN0LCBpZiB0aGUgZmly bXdhcmUgaGFzIHB1dCBwcm9wZXJ0aWVzIGluIHRoZSBkZXZpY2UtdHJlZQpjb250YWluaW5nIHRo ZSByZWxldmFudCBjb25maWd1cmF0aW9uIGluZm9ybWF0aW9uLCB3ZSB1c2UgdGhlc2UuCgogLSBP dGhlcndpc2UsIGEgYml0IGluIG9uZSBvZiB0aGUgU0NVIHNjcmF0Y2ggcmVnaXN0ZXJzICh3aGlj aAphcmUgcmVhZGFibGUgdmlhIHRoZSBWR0EgcmVnaXN0ZXIgc3BhY2UgYW5kIHdyaXRlYWJsZSBi eSB0aGUgQk1DKQp3aWxsIGluZGljYXRlIGlmIHRoZSBCTUMgaGFzIGNsb3NlZCB0aGUgd2luZG93 LiBUaGlzIGJpdCBoYXMgYmVlbgpkZWZpbmVkIGJ5IFkuQyBDaGVuIGZyb20gQXNwZWVkLgoKSWYg dGhlIHdpbmRvdyBpcyBjbG9zZWQgYW5kIHRoZSBjb25maWd1cmF0aW9uIGlzbid0IGF2YWlsYWJs ZSBmcm9tCnRoZSBkZXZpY2UtdHJlZSwgc29tZSBzYW5lIGRlZmF1bHRzIGFyZSB1c2VkLiBUaG9z ZSBkZWZhdWx0cyBhcmUKaG9wZWZ1bGx5IHN1ZmZpY2llbnQgZm9yIHN0YW5kYXJkIHZpZGVvIG1v ZGVzIHVzZWQgb24gYSBzZXJ2ZXIuCgpTaWduZWQtb2ZmLWJ5OiBSdXNzZWxsIEN1cnJleSA8cnVz Y3VyQHJ1c3NlbGwuY2M+ClNpZ25lZC1vZmYtYnk6IEJlbmphbWluIEhlcnJlbnNjaG1pZHQgPGJl bmhAa2VybmVsLmNyYXNoaW5nLm9yZz4KLS0KCnYyLiBbQmVuSF0KICAgIC0gUmV3b3JrZWQgb24g dG9wIG9mIEFzcGVlZCBQMkEgcGF0Y2gKICAgIC0gQ2xlYW51cCBvdmVyYWxsIGRldGVjdGlvbiB2 aWEgYSAiY29uZmlnX21vZGUiIGFuZCBsb2cgdGhlCiAgICAgIHNlbGVjdGVkIG1vZGUgZm9yIGRp YWdub3N0aWNzIHB1cnBvc2VzCiAgICAtIEFkZCBhIHByb3BlcnR5IGZvciB0aGUgU0NVIHN0cmFw cwoKdjMuIFtCZW5IXQogICAgLSBNb3ZlZCB0aGUgY29uZmlnIG1vZGUgZGV0ZWN0aW9uIHRvIGEg c2VwYXJhdGUgZnVuY3Rpb25uCiAgICAtIEFkZCByZWFkaW5nIG9mIFNDVSAweDQwIERbMTJdIHRv IGRldGVjdCB0aGUgd2luZG93IGlzCiAgICAgIGNsb3NlZCBhcyB0byBub3QgdHJpZ2dlciBhIGJ1 cyBlcnJvciBieSBqdXN0ICJ0cnlpbmciLgogICAgICAoY2hhbmdlIHByb3ZpZGVkIGJ5IFkuQy4g Q2hlbikKdjQuIFtCZW5IXQogICAgLSBPbmx5IGRldmljZXMgd2l0aCB0aGUgQVNUMjAwMCBQQ0kg SUQgaGF2ZSBhIFAyQSBicmlkZ2UKICAgIC0gVXBkYXRlIHRoZSBQMkEgcHJlc2VuY2UgdGVzdCB0 byBhY2NvdW50IGZvciBWR0Egb25seQogICAgICBtb2RlIGFzIHByb3ZpZGVkIGJ5IFkuQy4gQ2hl bi4KdjUuIFtCZW5IXQogICAgLSBGaXh1cCBwcmVmaXggb2YgT0YgcHJvcGVydGllcyBiYXNlZCBv biBKb2VsIFN0YW5sZXkKICAgICAgcmV2aWV3IGNvbW1lbnRzLgotLS0KIGRyaXZlcnMvZ3B1L2Ry bS9hc3QvYXN0X2Rydi5oICB8ICAgNiArLQogZHJpdmVycy9ncHUvZHJtL2FzdC9hc3RfbWFpbi5j IHwgMjY0ICsrKysrKysrKysrKysrKysrKysrKysrKystLS0tLS0tLS0tLS0tLS0tCiBkcml2ZXJz L2dwdS9kcm0vYXN0L2FzdF9wb3N0LmMgfCAgIDcgKy0KIDMgZmlsZXMgY2hhbmdlZCwgMTY4IGlu c2VydGlvbnMoKyksIDEwOSBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9k cm0vYXN0L2FzdF9kcnYuaCBiL2RyaXZlcnMvZ3B1L2RybS9hc3QvYXN0X2Rydi5oCmluZGV4IDdh YmRhOTQuLjNiZWRjZjcgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9hc3QvYXN0X2Rydi5o CisrKyBiL2RyaXZlcnMvZ3B1L2RybS9hc3QvYXN0X2Rydi5oCkBAIC0xMTMsNyArMTEzLDExIEBA IHN0cnVjdCBhc3RfcHJpdmF0ZSB7CiAJc3RydWN0IHR0bV9ib19rbWFwX29iaiBjYWNoZV9rbWFw OwogCWludCBuZXh0X2N1cnNvcjsKIAlib29sIHN1cHBvcnRfd2lkZV9zY3JlZW47Ci0JYm9vbCBE aXNhYmxlUDJBOworCWVudW0geworCQlhc3RfdXNlX3AyYSwKKwkJYXN0X3VzZV9kdCwKKwkJYXN0 X3VzZV9kZWZhdWx0cworCX0gY29uZmlnX21vZGU7CiAKIAllbnVtIGFzdF90eF9jaGlwIHR4X2No aXBfdHlwZTsKIAl1OCBkcDUwMV9tYXhjbGs7CmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0v YXN0L2FzdF9tYWluLmMgYi9kcml2ZXJzL2dwdS9kcm0vYXN0L2FzdF9tYWluLmMKaW5kZXggNTMz ZTc2Mi4uZmI5OTc2MiAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL2FzdC9hc3RfbWFpbi5j CisrKyBiL2RyaXZlcnMvZ3B1L2RybS9hc3QvYXN0X21haW4uYwpAQCAtNjIsMTMgKzYyLDg0IEBA IHVpbnQ4X3QgYXN0X2dldF9pbmRleF9yZWdfbWFzayhzdHJ1Y3QgYXN0X3ByaXZhdGUgKmFzdCwK IAlyZXR1cm4gcmV0OwogfQogCitzdGF0aWMgdm9pZCBhc3RfZGV0ZWN0X2NvbmZpZ19tb2RlKHN0 cnVjdCBkcm1fZGV2aWNlICpkZXYsIHUzMiAqc2N1X3JldikKK3sKKwlzdHJ1Y3QgZGV2aWNlX25v ZGUgKm5wID0gZGV2LT5wZGV2LT5kZXYub2Zfbm9kZTsKKwlzdHJ1Y3QgYXN0X3ByaXZhdGUgKmFz dCA9IGRldi0+ZGV2X3ByaXZhdGU7CisJdWludDMyX3QgZGF0YSwganJlZ2QwLCBqcmVnZDE7CisK KwkvKiBEZWZhdWx0cyAqLworCWFzdC0+Y29uZmlnX21vZGUgPSBhc3RfdXNlX2RlZmF1bHRzOwor CSpzY3VfcmV2ID0gMHhmZmZmZmZmZjsKKworCS8qIENoZWNrIGlmIHdlIGhhdmUgZGV2aWNlLXRy ZWUgcHJvcGVydGllcyAqLworCWlmIChucCAmJiAhb2ZfcHJvcGVydHlfcmVhZF91MzIobnAsICJh c3BlZWQsc2N1LXJldmlzaW9uLWlkIiwKKwkJCQkJc2N1X3JldikpIHsKKwkJLyogV2UgZG8sIGRp c2FibGUgUDJBIGFjY2VzcyAqLworCQlhc3QtPmNvbmZpZ19tb2RlID0gYXN0X3VzZV9kdDsKKwkJ RFJNX0lORk8oIlVzaW5nIGRldmljZS10cmVlIGZvciBjb25maWd1cmF0aW9uXG4iKTsKKwkJcmV0 dXJuOworCX0KKworCS8qIE5vdCBhbGwgZmFtaWxpZXMgaGF2ZSBhIFAyQSBicmlkZ2UgKi8KKwlp ZiAoZGV2LT5wZGV2LT5kZXZpY2UgIT0gUENJX0NISVBfQVNUMjAwMCkKKwkJcmV0dXJuOworCisJ LyoKKwkgKiBUaGUgQk1DIHdpbGwgc2V0IFNDVSAweDQwIERbMTJdIHRvIDEgaWYgdGhlIFAyIGJy aWRnZQorCSAqIGlzIGRpc2FibGVkLiBXZSBmb3JjZSB1c2luZyBQMkEgaWYgVkdBIG9ubHkgbW9k ZSBiaXQKKwkgKiBpcyBzZXQgRFs3XQorCSAqLworCWpyZWdkMCA9IGFzdF9nZXRfaW5kZXhfcmVn X21hc2soYXN0LCBBU1RfSU9fQ1JUQ19QT1JULCAweGQwLCAweGZmKTsKKwlqcmVnZDEgPSBhc3Rf Z2V0X2luZGV4X3JlZ19tYXNrKGFzdCwgQVNUX0lPX0NSVENfUE9SVCwgMHhkMSwgMHhmZik7CisJ aWYgKCEoanJlZ2QwICYgMHg4MCkgfHwgIShqcmVnZDEgJiAweDEwKSkgeworCQkvKiBEb3VibGUg Y2hlY2sgaXQncyBhY3R1YWxseSB3b3JraW5nICovCisJCWRhdGEgPSBhc3RfcmVhZDMyKGFzdCwg MHhmMDA0KTsKKwkJaWYgKGRhdGEgIT0gMHhGRkZGRkZGRikgeworCQkJLyogUDJBIHdvcmtzLCBn cmFiIHNpbGljb24gcmV2aXNpb24gKi8KKwkJCWFzdC0+Y29uZmlnX21vZGUgPSBhc3RfdXNlX3Ay YTsKKworCQkJRFJNX0lORk8oIlVzaW5nIFAyQSBicmlkZ2UgZm9yIGNvbmZpZ3VyYXRpb25cbiIp OworCisJCQkvKiBSZWFkIFNDVTdjIChzaWxpY29uIHJldmlzaW9uIHJlZ2lzdGVyKSAqLworCQkJ YXN0X3dyaXRlMzIoYXN0LCAweGYwMDQsIDB4MWU2ZTAwMDApOworCQkJYXN0X3dyaXRlMzIoYXN0 LCAweGYwMDAsIDB4MSk7CisJCQkqc2N1X3JldiA9IGFzdF9yZWFkMzIoYXN0LCAweDEyMDdjKTsK KwkJCXJldHVybjsKKwkJfQorCX0KKworCS8qIFdlIGhhdmUgYSBQMkEgYnJpZGdlIGJ1dCBpdCdz IGRpc2FibGVkICovCisJRFJNX0lORk8oIlAyQSBicmlkZ2UgZGlzYWJsZWQsIHVzaW5nIGRlZmF1 bHQgY29uZmlndXJhdGlvblxuIik7Cit9CiAKIHN0YXRpYyBpbnQgYXN0X2RldGVjdF9jaGlwKHN0 cnVjdCBkcm1fZGV2aWNlICpkZXYsIGJvb2wgKm5lZWRfcG9zdCkKIHsKIAlzdHJ1Y3QgYXN0X3By aXZhdGUgKmFzdCA9IGRldi0+ZGV2X3ByaXZhdGU7Ci0JdWludDMyX3QgZGF0YSwganJlZzsKKwl1 aW50MzJfdCBqcmVnLCBzY3VfcmV2OworCisJLyoKKwkgKiBJZiBWR0EgaXNuJ3QgZW5hYmxlZCwg d2UgbmVlZCB0byBlbmFibGUgbm93IG9yIHN1YnNlcXVlbnQKKwkgKiBhY2Nlc3MgdG8gdGhlIHNj cmF0Y2ggcmVnaXN0ZXJzIHdpbGwgZmFpbC4gV2UgYWxzbyBpbmZvcm0KKwkgKiBvdXIgY2FsbGVy IHRoYXQgaXQgbmVlZHMgdG8gUE9TVCB0aGUgY2hpcAorCSAqIChBc3N1bXB0aW9uOiBWR0Egbm90 IGVuYWJsZWQgLT4gbmVlZCB0byBQT1NUKQorCSAqLworCWlmICghYXN0X2lzX3ZnYV9lbmFibGVk KGRldikpIHsKKwkJYXN0X2VuYWJsZV92Z2EoZGV2KTsKKwkJRFJNX0lORk8oIlZHQSBub3QgZW5h YmxlZCBvbiBlbnRyeSwgcmVxdWVzdGluZyBjaGlwIFBPU1RcbiIpOworCQkqbmVlZF9wb3N0ID0g dHJ1ZTsKKwl9IGVsc2UKKwkJKm5lZWRfcG9zdCA9IGZhbHNlOworCisKKwkvKiBFbmFibGUgZXh0 ZW5kZWQgcmVnaXN0ZXIgYWNjZXNzICovCisJYXN0X2VuYWJsZV9tbWlvKGRldik7CiAJYXN0X29w ZW5fa2V5KGFzdCk7CiAKKwkvKiBGaW5kIG91dCB3aGV0aGVyIFAyQSB3b3JrcyBvciB3aGV0aGVy IHRvIHVzZSBkZXZpY2UtdHJlZSAqLworCWFzdF9kZXRlY3RfY29uZmlnX21vZGUoZGV2LCAmc2N1 X3Jldik7CisKKwkvKiBJZGVudGlmeSBjaGlwc2V0ICovCiAJaWYgKGRldi0+cGRldi0+ZGV2aWNl ID09IFBDSV9DSElQX0FTVDExODApIHsKIAkJYXN0LT5jaGlwID0gQVNUMTEwMDsKIAkJRFJNX0lO Rk8oIkFTVCAxMTgwIGRldGVjdGVkXG4iKTsKQEAgLTgwLDEyICsxNTEsNyBAQCBzdGF0aWMgaW50 IGFzdF9kZXRlY3RfY2hpcChzdHJ1Y3QgZHJtX2RldmljZSAqZGV2LCBib29sICpuZWVkX3Bvc3Qp CiAJCQlhc3QtPmNoaXAgPSBBU1QyMzAwOwogCQkJRFJNX0lORk8oIkFTVCAyMzAwIGRldGVjdGVk XG4iKTsKIAkJfSBlbHNlIGlmIChkZXYtPnBkZXYtPnJldmlzaW9uID49IDB4MTApIHsKLQkJCXVp bnQzMl90IGRhdGE7Ci0JCQlhc3Rfd3JpdGUzMihhc3QsIDB4ZjAwNCwgMHgxZTZlMDAwMCk7Ci0J CQlhc3Rfd3JpdGUzMihhc3QsIDB4ZjAwMCwgMHgxKTsKLQotCQkJZGF0YSA9IGFzdF9yZWFkMzIo YXN0LCAweDEyMDdjKTsKLQkJCXN3aXRjaCAoZGF0YSAmIDB4MDMwMCkgeworCQkJc3dpdGNoIChz Y3VfcmV2ICYgMHgwMzAwKSB7CiAJCQljYXNlIDB4MDIwMDoKIAkJCQlhc3QtPmNoaXAgPSBBU1Qx MTAwOwogCQkJCURSTV9JTkZPKCJBU1QgMTEwMCBkZXRlY3RlZFxuIik7CkBAIC0xMTAsMjYgKzE3 Niw2IEBAIHN0YXRpYyBpbnQgYXN0X2RldGVjdF9jaGlwKHN0cnVjdCBkcm1fZGV2aWNlICpkZXYs IGJvb2wgKm5lZWRfcG9zdCkKIAkJfQogCX0KIAotCS8qCi0JICogSWYgVkdBIGlzbid0IGVuYWJs ZWQsIHdlIG5lZWQgdG8gZW5hYmxlIG5vdyBvciBzdWJzZXF1ZW50Ci0JICogYWNjZXNzIHRvIHRo ZSBzY3JhdGNoIHJlZ2lzdGVycyB3aWxsIGZhaWwuIFdlIGFsc28gaW5mb3JtCi0JICogb3VyIGNh bGxlciB0aGF0IGl0IG5lZWRzIHRvIFBPU1QgdGhlIGNoaXAKLQkgKiAoQXNzdW1wdGlvbjogVkdB IG5vdCBlbmFibGVkIC0+IG5lZWQgdG8gUE9TVCkKLQkgKi8KLQlpZiAoIWFzdF9pc192Z2FfZW5h YmxlZChkZXYpKSB7Ci0JCWFzdF9lbmFibGVfdmdhKGRldik7Ci0JCWFzdF9lbmFibGVfbW1pbyhk ZXYpOwotCQlEUk1fSU5GTygiVkdBIG5vdCBlbmFibGVkIG9uIGVudHJ5LCByZXF1ZXN0aW5nIGNo aXAgUE9TVFxuIik7Ci0JCSpuZWVkX3Bvc3QgPSB0cnVlOwotCX0gZWxzZQotCQkqbmVlZF9wb3N0 ID0gZmFsc2U7Ci0KLQkvKiBDaGVjayBQMkEgQWNjZXNzICovCi0JYXN0LT5EaXNhYmxlUDJBID0g dHJ1ZTsKLQlkYXRhID0gYXN0X3JlYWQzMihhc3QsIDB4ZjAwNCk7Ci0JaWYgKGRhdGEgIT0gMHhG RkZGRkZGRikKLQkJYXN0LT5EaXNhYmxlUDJBID0gZmFsc2U7Ci0KIAkvKiBDaGVjayBpZiB3ZSBz dXBwb3J0IHdpZGUgc2NyZWVuICovCiAJc3dpdGNoIChhc3QtPmNoaXApIHsKIAljYXNlIEFTVDEx ODA6CkBAIC0xNDYsMTcgKzE5MiwxMiBAQCBzdGF0aWMgaW50IGFzdF9kZXRlY3RfY2hpcChzdHJ1 Y3QgZHJtX2RldmljZSAqZGV2LCBib29sICpuZWVkX3Bvc3QpCiAJCQlhc3QtPnN1cHBvcnRfd2lk ZV9zY3JlZW4gPSB0cnVlOwogCQllbHNlIHsKIAkJCWFzdC0+c3VwcG9ydF93aWRlX3NjcmVlbiA9 IGZhbHNlOwotCQkJaWYgKGFzdC0+RGlzYWJsZVAyQSA9PSBmYWxzZSkgewotCQkJCS8qIFJlYWQg U0NVN2MgKHNpbGljb24gcmV2aXNpb24gcmVnaXN0ZXIpICovCi0JCQkJYXN0X3dyaXRlMzIoYXN0 LCAweGYwMDQsIDB4MWU2ZTAwMDApOwotCQkJCWFzdF93cml0ZTMyKGFzdCwgMHhmMDAwLCAweDEp OwotCQkJCWRhdGEgPSBhc3RfcmVhZDMyKGFzdCwgMHgxMjA3Yyk7Ci0JCQkJZGF0YSAmPSAweDMw MDsKLQkJCQlpZiAoYXN0LT5jaGlwID09IEFTVDIzMDAgJiYgZGF0YSA9PSAweDApIC8qIGFzdDEz MDAgKi8KLQkJCQkJYXN0LT5zdXBwb3J0X3dpZGVfc2NyZWVuID0gdHJ1ZTsKLQkJCQlpZiAoYXN0 LT5jaGlwID09IEFTVDI0MDAgJiYgZGF0YSA9PSAweDEwMCkgLyogYXN0MTQwMCAqLwotCQkJCQlh c3QtPnN1cHBvcnRfd2lkZV9zY3JlZW4gPSB0cnVlOwotCQkJfQorCQkJaWYgKGFzdC0+Y2hpcCA9 PSBBU1QyMzAwICYmCisJCQkgICAgKHNjdV9yZXYgJiAweDMwMCkgPT0gMHgwKSAvKiBhc3QxMzAw ICovCisJCQkJYXN0LT5zdXBwb3J0X3dpZGVfc2NyZWVuID0gdHJ1ZTsKKwkJCWlmIChhc3QtPmNo aXAgPT0gQVNUMjQwMCAmJgorCQkJICAgIChzY3VfcmV2ICYgMHgzMDApID09IDB4MTAwKSAvKiBh c3QxNDAwICovCisJCQkJYXN0LT5zdXBwb3J0X3dpZGVfc2NyZWVuID0gdHJ1ZTsKIAkJfQogCQli cmVhazsKIAl9CkBAIC0yMjAsODUgKzI2MSwxMDIgQEAgc3RhdGljIGludCBhc3RfZGV0ZWN0X2No aXAoc3RydWN0IGRybV9kZXZpY2UgKmRldiwgYm9vbCAqbmVlZF9wb3N0KQogCiBzdGF0aWMgaW50 IGFzdF9nZXRfZHJhbV9pbmZvKHN0cnVjdCBkcm1fZGV2aWNlICpkZXYpCiB7CisJc3RydWN0IGRl dmljZV9ub2RlICpucCA9IGRldi0+cGRldi0+ZGV2Lm9mX25vZGU7CiAJc3RydWN0IGFzdF9wcml2 YXRlICphc3QgPSBkZXYtPmRldl9wcml2YXRlOwotCXVpbnQzMl90IGRhdGEsIGRhdGEyOwotCXVp bnQzMl90IGRlbnVtLCBudW0sIGRpdiwgcmVmX3BsbDsKKwl1aW50MzJfdCBtY3JfY2ZnLCBtY3Jf c2N1X21wbGwsIG1jcl9zY3Vfc3RyYXA7CisJdWludDMyX3QgZGVudW0sIG51bSwgZGl2LCByZWZf cGxsLCBkc2VsOwogCi0JaWYgKGFzdC0+RGlzYWJsZVAyQSkKLQl7CisJc3dpdGNoIChhc3QtPmNv bmZpZ19tb2RlKSB7CisJY2FzZSBhc3RfdXNlX2R0OgorCQkvKgorCQkgKiBJZiBzb21lIHByb3Bl cnRpZXMgYXJlIG1pc3NpbmcsIHVzZSByZWFzb25hYmxlCisJCSAqIGRlZmF1bHRzIGZvciBBU1Qy NDAwCisJCSAqLworCQlpZiAob2ZfcHJvcGVydHlfcmVhZF91MzIobnAsICJhc3BlZWQsbWNyLWNv bmZpZ3VyYXRpb24iLAorCQkJCQkgJm1jcl9jZmcpKQorCQkJbWNyX2NmZyA9IDB4MDAwMDA1Nzc7 CisJCWlmIChvZl9wcm9wZXJ0eV9yZWFkX3UzMihucCwgImFzcGVlZCxtY3Itc2N1LW1wbGwiLAor CQkJCQkgJm1jcl9zY3VfbXBsbCkpCisJCQltY3Jfc2N1X21wbGwgPSAweDAwMDA1MEMwOworCQlp ZiAob2ZfcHJvcGVydHlfcmVhZF91MzIobnAsICJhc3BlZWQsbWNyLXNjdS1zdHJhcCIsCisJCQkJ CSAmbWNyX3NjdV9zdHJhcCkpCisJCQltY3Jfc2N1X3N0cmFwID0gMDsKKwkJYnJlYWs7CisJY2Fz ZSBhc3RfdXNlX3AyYToKKwkJYXN0X3dyaXRlMzIoYXN0LCAweGYwMDQsIDB4MWU2ZTAwMDApOwor CQlhc3Rfd3JpdGUzMihhc3QsIDB4ZjAwMCwgMHgxKTsKKwkJbWNyX2NmZyA9IGFzdF9yZWFkMzIo YXN0LCAweDEwMDA0KTsKKwkJbWNyX3NjdV9tcGxsID0gYXN0X3JlYWQzMihhc3QsIDB4MTAxMjAp OworCQltY3Jfc2N1X3N0cmFwID0gYXN0X3JlYWQzMihhc3QsIDB4MTAxNzApOworCQlicmVhazsK KwljYXNlIGFzdF91c2VfZGVmYXVsdHM6CisJZGVmYXVsdDoKIAkJYXN0LT5kcmFtX2J1c193aWR0 aCA9IDE2OwogCQlhc3QtPmRyYW1fdHlwZSA9IEFTVF9EUkFNXzFHeDE2OwogCQlhc3QtPm1jbGsg PSAzOTY7CisJCXJldHVybiAwOwogCX0KLQllbHNlCi0JewotCQlhc3Rfd3JpdGUzMihhc3QsIDB4 ZjAwNCwgMHgxZTZlMDAwMCk7Ci0JCWFzdF93cml0ZTMyKGFzdCwgMHhmMDAwLCAweDEpOwotCQlk YXRhID0gYXN0X3JlYWQzMihhc3QsIDB4MTAwMDQpOwotCi0JCWlmIChkYXRhICYgMHg0MCkKLQkJ CWFzdC0+ZHJhbV9idXNfd2lkdGggPSAxNjsKLQkJZWxzZQotCQkJYXN0LT5kcmFtX2J1c193aWR0 aCA9IDMyOwogCi0JCWlmIChhc3QtPmNoaXAgPT0gQVNUMjMwMCB8fCBhc3QtPmNoaXAgPT0gQVNU MjQwMCkgewotCQkJc3dpdGNoIChkYXRhICYgMHgwMykgewotCQkJY2FzZSAwOgotCQkJCWFzdC0+ ZHJhbV90eXBlID0gQVNUX0RSQU1fNTEyTXgxNjsKLQkJCQlicmVhazsKLQkJCWRlZmF1bHQ6Ci0J CQljYXNlIDE6Ci0JCQkJYXN0LT5kcmFtX3R5cGUgPSBBU1RfRFJBTV8xR3gxNjsKLQkJCQlicmVh azsKLQkJCWNhc2UgMjoKLQkJCQlhc3QtPmRyYW1fdHlwZSA9IEFTVF9EUkFNXzJHeDE2OwotCQkJ CWJyZWFrOwotCQkJY2FzZSAzOgotCQkJCWFzdC0+ZHJhbV90eXBlID0gQVNUX0RSQU1fNEd4MTY7 Ci0JCQkJYnJlYWs7Ci0JCQl9Ci0JCX0gZWxzZSB7Ci0JCQlzd2l0Y2ggKGRhdGEgJiAweDBjKSB7 Ci0JCQljYXNlIDA6Ci0JCQljYXNlIDQ6Ci0JCQkJYXN0LT5kcmFtX3R5cGUgPSBBU1RfRFJBTV81 MTJNeDE2OwotCQkJCWJyZWFrOwotCQkJY2FzZSA4OgotCQkJCWlmIChkYXRhICYgMHg0MCkKLQkJ CQkJYXN0LT5kcmFtX3R5cGUgPSBBU1RfRFJBTV8xR3gxNjsKLQkJCQllbHNlCi0JCQkJCWFzdC0+ ZHJhbV90eXBlID0gQVNUX0RSQU1fNTEyTXgzMjsKLQkJCQlicmVhazsKLQkJCWNhc2UgMHhjOgot CQkJCWFzdC0+ZHJhbV90eXBlID0gQVNUX0RSQU1fMUd4MzI7Ci0JCQkJYnJlYWs7Ci0JCQl9Ci0J CX0KKwlpZiAobWNyX2NmZyAmIDB4NDApCisJCWFzdC0+ZHJhbV9idXNfd2lkdGggPSAxNjsKKwll bHNlCisJCWFzdC0+ZHJhbV9idXNfd2lkdGggPSAzMjsKIAotCQlkYXRhID0gYXN0X3JlYWQzMihh c3QsIDB4MTAxMjApOwotCQlkYXRhMiA9IGFzdF9yZWFkMzIoYXN0LCAweDEwMTcwKTsKLQkJaWYg KGRhdGEyICYgMHgyMDAwKQotCQkJcmVmX3BsbCA9IDE0MzE4OwotCQllbHNlCi0JCQlyZWZfcGxs ID0gMTIwMDA7Ci0KLQkJZGVudW0gPSBkYXRhICYgMHgxZjsKLQkJbnVtID0gKGRhdGEgJiAweDNm ZTApID4+IDU7Ci0JCWRhdGEgPSAoZGF0YSAmIDB4YzAwMCkgPj4gMTQ7Ci0JCXN3aXRjaCAoZGF0 YSkgewotCQljYXNlIDM6Ci0JCQlkaXYgPSAweDQ7CisJaWYgKGFzdC0+Y2hpcCA9PSBBU1QyMzAw IHx8IGFzdC0+Y2hpcCA9PSBBU1QyNDAwKSB7CisJCXN3aXRjaCAobWNyX2NmZyAmIDB4MDMpIHsK KwkJY2FzZSAwOgorCQkJYXN0LT5kcmFtX3R5cGUgPSBBU1RfRFJBTV81MTJNeDE2OwogCQkJYnJl YWs7Ci0JCWNhc2UgMjoKKwkJZGVmYXVsdDoKIAkJY2FzZSAxOgotCQkJZGl2ID0gMHgyOworCQkJ YXN0LT5kcmFtX3R5cGUgPSBBU1RfRFJBTV8xR3gxNjsKIAkJCWJyZWFrOwotCQlkZWZhdWx0Ogot CQkJZGl2ID0gMHgxOworCQljYXNlIDI6CisJCQlhc3QtPmRyYW1fdHlwZSA9IEFTVF9EUkFNXzJH eDE2OworCQkJYnJlYWs7CisJCWNhc2UgMzoKKwkJCWFzdC0+ZHJhbV90eXBlID0gQVNUX0RSQU1f NEd4MTY7CisJCQlicmVhazsKKwkJfQorCX0gZWxzZSB7CisJCXN3aXRjaCAobWNyX2NmZyAmIDB4 MGMpIHsKKwkJY2FzZSAwOgorCQljYXNlIDQ6CisJCQlhc3QtPmRyYW1fdHlwZSA9IEFTVF9EUkFN XzUxMk14MTY7CisJCQlicmVhazsKKwkJY2FzZSA4OgorCQkJaWYgKG1jcl9jZmcgJiAweDQwKQor CQkJCWFzdC0+ZHJhbV90eXBlID0gQVNUX0RSQU1fMUd4MTY7CisJCQllbHNlCisJCQkJYXN0LT5k cmFtX3R5cGUgPSBBU1RfRFJBTV81MTJNeDMyOworCQkJYnJlYWs7CisJCWNhc2UgMHhjOgorCQkJ YXN0LT5kcmFtX3R5cGUgPSBBU1RfRFJBTV8xR3gzMjsKIAkJCWJyZWFrOwogCQl9Ci0JCWFzdC0+ bWNsayA9IHJlZl9wbGwgKiAobnVtICsgMikgLyAoZGVudW0gKyAyKSAqIChkaXYgKiAxMDAwKTsK IAl9CisKKwlpZiAobWNyX3NjdV9zdHJhcCAmIDB4MjAwMCkKKwkJcmVmX3BsbCA9IDE0MzE4Owor CWVsc2UKKwkJcmVmX3BsbCA9IDEyMDAwOworCisJZGVudW0gPSBtY3Jfc2N1X21wbGwgJiAweDFm OworCW51bSA9IChtY3Jfc2N1X21wbGwgJiAweDNmZTApID4+IDU7CisJZHNlbCA9IChtY3Jfc2N1 X21wbGwgJiAweGMwMDApID4+IDE0OworCXN3aXRjaCAoZHNlbCkgeworCWNhc2UgMzoKKwkJZGl2 ID0gMHg0OworCQlicmVhazsKKwljYXNlIDI6CisJY2FzZSAxOgorCQlkaXYgPSAweDI7CisJCWJy ZWFrOworCWRlZmF1bHQ6CisJCWRpdiA9IDB4MTsKKwkJYnJlYWs7CisJfQorCWFzdC0+bWNsayA9 IHJlZl9wbGwgKiAobnVtICsgMikgLyAoZGVudW0gKyAyKSAqIChkaXYgKiAxMDAwKTsKIAlyZXR1 cm4gMDsKIH0KIApkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2FzdC9hc3RfcG9zdC5jIGIv ZHJpdmVycy9ncHUvZHJtL2FzdC9hc3RfcG9zdC5jCmluZGV4IDZjNTM5MWMuLjY0NTQ5Y2UgMTAw NjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9hc3QvYXN0X3Bvc3QuYworKysgYi9kcml2ZXJzL2dw dS9kcm0vYXN0L2FzdF9wb3N0LmMKQEAgLTM3OSwxNyArMzc5LDE0IEBAIHZvaWQgYXN0X3Bvc3Rf Z3B1KHN0cnVjdCBkcm1fZGV2aWNlICpkZXYpCiAJYXN0X29wZW5fa2V5KGFzdCk7CiAJYXN0X3Nl dF9kZWZfZXh0X3JlZyhkZXYpOwogCi0JaWYgKGFzdC0+RGlzYWJsZVAyQSA9PSBmYWxzZSkKLQl7 CisJaWYgKGFzdC0+Y29uZmlnX21vZGUgPT0gYXN0X3VzZV9wMmEpIHsKIAkJaWYgKGFzdC0+Y2hp cCA9PSBBU1QyMzAwIHx8IGFzdC0+Y2hpcCA9PSBBU1QyNDAwKQogCQkJYXN0X2luaXRfZHJhbV8y MzAwKGRldik7CiAJCWVsc2UKIAkJCWFzdF9pbml0X2RyYW1fcmVnKGRldik7CiAKIAkJYXN0X2lu aXRfM3JkdHgoZGV2KTsKLQl9Ci0JZWxzZQotCXsKKwl9IGVsc2UgewogCQlpZiAoYXN0LT50eF9j aGlwX3R5cGUgIT0gQVNUX1RYX05PTkUpCiAJCQlhc3Rfc2V0X2luZGV4X3JlZ19tYXNrKGFzdCwg QVNUX0lPX0NSVENfUE9SVCwgMHhhMywgMHhjZiwgMHg4MCk7CS8qIEVuYWJsZSBEVk8gKi8KIAl9 CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2 ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9s aXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK