From: Dalon Westergreen <dwesterg@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3] arm: socfpga: fix issue with warm reset when CSEL is 0
Date: Sun, 05 Mar 2017 09:38:10 -0800 [thread overview]
Message-ID: <1488735490.16517.93.camel@gmail.com> (raw)
In-Reply-To: <1488293105.6894.6.camel@gmail.com>
On Tue, 2017-02-28 at 06:45 -0800, Dalon Westergreen wrote:
> On Mon, 2017-02-20 at 06:35 -0800, Dalon Westergreen wrote:
> >
> > On Mon, 2017-02-20 at 15:24 +0100, Marek Vasut wrote:
> > >
> > >
> > > On 02/20/2017 03:21 PM, Dalon Westergreen wrote:
> > > >
> > > >
> > > >
> > > > On Mon, 2017-02-20 at 15:14 +0100, Marek Vasut wrote:
> > > > >
> > > > >
> > > > >
> > > > > On 02/20/2017 03:10 PM, Dalon Westergreen wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > On Mon, 2017-02-20 at 10:07 +0100, Marek Vasut wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > On 02/18/2017 02:34 AM, Dalon Westergreen wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > > > > > configuration for the device. This can lead to a boot failure
> > > > > > > > on warm resets. This patch disables warm resets when CSEL=0.
> > > > > > > > This results in the clock and pll configurations being reset
> > > > > > > > on any reset issued when CSEL=0.
> > > > > > > >
> > > > > > > > Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
> > > > > > >
> > > > > > > What about my suggestion for V2 about just loading function
> > > > > > > pointer
> > > > > > > into
> > > > > > > the reset jump address register ?
> > > > > >
> > > > > > Frankly, i really dont like relying on the existence of a snippet of
> > > > > > code in
> > > > > > the
> > > > > > onchip ram being untouched to ensure a reboot/reset will occur for
> > > > > > this
> > > > > > csel=0
> > > > > > case. i am certain this case is rarely used, and confident that it
> > > > > > isnt
> > > > > > being
> > > > > > used while trying to preserve sdram contents.
> > > > >
> > > > > Well, you already rely on such snippet, it's SPL. If you corrupt SPL
> > > > > and
> > > > > do warm reset, your system hangs, I had that multiple times :)
> > > >
> > > > True. I would argue to just use cold resets but i think arria 10 has
> > > > more
> > > > use
> > > > for the warm reset case.
> > >
> > > OK
> > >
> > > >
> > > >
> > > >
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > the downside is that the scorecard is reset every boot. so the
> > > > > > bootrom
> > > > > > will
> > > > > > retry all the spl images again resulting in possibly longer boot
> > > > > > times.
> > > > >
> > > > > Is that significant ?
> > > >
> > > > The watchdog timeout is on the order of 1.5 seconds. That would be for
> > > > each
> > > > failed spl.
> > >
> > > Hm, OK. But then your system is kinda broken, so you should expect this
> > > I guess.
> >
> > My thought exactly... I would like to see if Chin Liang or Dinh have any
> > comments?
>
> Chin Liang, Dinh, any comments?
Marek, I would like to propose we move forward with this patch?
--dalon
>
> >
> > >
> > >
> > >
> > > [...]
> > >
next prev parent reply other threads:[~2017-03-05 17:38 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-18 1:34 [U-Boot] [PATCH v3] arm: socfpga: fix issue with warm reset when CSEL is 0 Dalon Westergreen
2017-02-20 9:07 ` Marek Vasut
2017-02-20 14:10 ` Dalon Westergreen
2017-02-20 14:14 ` Marek Vasut
2017-02-20 14:21 ` Dalon Westergreen
2017-02-20 14:24 ` Marek Vasut
2017-02-20 14:35 ` Dalon Westergreen
2017-02-20 14:38 ` Marek Vasut
2017-02-28 14:45 ` Dalon Westergreen
2017-03-05 17:38 ` Dalon Westergreen [this message]
2017-03-05 17:49 ` Marek Vasut
2017-03-06 2:25 ` Dalon Westergreen
2017-03-07 3:46 ` Marek Vasut
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