Re: [PATCH v3 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Paulo Zanoni <paulo.r.zanoni@intel.com>]

Em Ter, 2017-03-14 às 15:45 -0700, Dhinakaran Pandiyan escreveu:
> According to BSpec, "The CD clock frequency must be at least twice
> the
> frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> default. This check is needed because BXT and GLK support cdclk
> frequencies less than 192 MHz.
> 
> v2: Include other Gen9 platforms too for completeness.(Paulo)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index dd350642..dd3ad52 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1458,6 +1458,18 @@ static int
> bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>  			pixel_rate = max(432000, pixel_rate);
>  	}
>  
> +	/* According to BSpec, "The CD clock frequency must be at
> least twice
> +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by
> default.
> +	 * The check for GLK has to be adjusted as the platform can
> output
> +	 * two pixels per clock.
> +	 */
> +	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
> +		if (IS_GEMINILAKE(dev_priv))
> +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> +		else
> +			pixel_rate = max(2 * 96000, pixel_rate);
> +	}
> +
>  	return pixel_rate;
>  }
>  
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