diff for duplicates of <1491147496.3480.5.camel@baylibre.com> diff --git a/a/1.txt b/N1/1.txt index 234ae81..8b74ce0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -47,19 +47,19 @@ to pay attention to that if you port your NAND work the gx family. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- -> ?drivers/clk/meson/meson8b.c | 53 +> drivers/clk/meson/meson8b.c | 53 > +++++++++++++++++++++++++++++++++++++++++++++ -> ?drivers/clk/meson/meson8b.h |??6 ++++- -> ?2 files changed, 58 insertions(+), 1 deletion(-) +> drivers/clk/meson/meson8b.h | 6 ++++- +> 2 files changed, 58 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > index e9985503165c..b7f3cf8ed386 100644 > --- a/drivers/clk/meson/meson8b.c > +++ b/drivers/clk/meson/meson8b.c > @@ -403,6 +403,53 @@ struct clk_gate meson8b_clk81 = { -> ? }, -> ?}; -> ? +> }, +> }; +> > +static u32 mux_table_nand[] = { 0, 1, 2, 3, 4 }; You can drop this table, you don't need it. @@ -132,65 +132,65 @@ Could you give it try ? > + }, > +}; > + -> ?/* Everything Else (EE) domain gates */ -> ? -> ?static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); +> /* Everything Else (EE) domain gates */ +> +> static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); > @@ -584,6 +631,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data > = { -> ? [CLKID_MPLL0] ????= &meson8b_mpll0.hw, -> ? [CLKID_MPLL1] ????= &meson8b_mpll1.hw, -> ? [CLKID_MPLL2] ????= &meson8b_mpll2.hw, -> + [CLKID_NAND_SEL] ????= &meson8b_nand_clk_sel.hw, -> + [CLKID_NAND_DIV] ????= &meson8b_nand_clk_div.hw, -> + [CLKID_NAND_CLK] ????= &meson8b_nand_clk_gate.hw, -> ? }, -> ? .num = CLK_NR_CLKS, -> ?}; +> [CLKID_MPLL0] = &meson8b_mpll0.hw, +> [CLKID_MPLL1] = &meson8b_mpll1.hw, +> [CLKID_MPLL2] = &meson8b_mpll2.hw, +> + [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, +> + [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, +> + [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, +> }, +> .num = CLK_NR_CLKS, +> }; > @@ -679,14 +729,17 @@ static struct clk_gate *const meson8b_clk_gates[] = { -> ? &meson8b_ao_ahb_sram, -> ? &meson8b_ao_ahb_bus, -> ? &meson8b_ao_iface, +> &meson8b_ao_ahb_sram, +> &meson8b_ao_ahb_bus, +> &meson8b_ao_iface, > + &meson8b_nand_clk_gate, -> ?}; -> ? -> ?static struct clk_mux *const meson8b_clk_muxes[] = { -> ? &meson8b_mpeg_clk_sel, +> }; +> +> static struct clk_mux *const meson8b_clk_muxes[] = { +> &meson8b_mpeg_clk_sel, > + &meson8b_nand_clk_sel, -> ?}; -> ? -> ?static struct clk_divider *const meson8b_clk_dividers[] = { -> ? &meson8b_mpeg_clk_div, +> }; +> +> static struct clk_divider *const meson8b_clk_dividers[] = { +> &meson8b_mpeg_clk_div, > + &meson8b_nand_clk_div, -> ?}; -> ? -> ?static int meson8b_clkc_probe(struct platform_device *pdev) +> }; +> +> static int meson8b_clkc_probe(struct platform_device *pdev) > diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h > index 3881defc8644..cbb8001b5fe8 100644 > --- a/drivers/clk/meson/meson8b.h > +++ b/drivers/clk/meson/meson8b.h > @@ -37,6 +37,7 @@ -> ?#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet +> #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet > */ -> ?#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data +> #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data > sheet */ -> ?#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet +> #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet > */ > +#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet > */ -> ?#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data +> #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data > sheet */ -> ?#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ -> ?#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ +> #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ +> #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ > @@ -160,8 +161,11 @@ -> ?#define CLKID_MPLL0 93 -> ?#define CLKID_MPLL1 94 -> ?#define CLKID_MPLL2 95 +> #define CLKID_MPLL0 93 +> #define CLKID_MPLL1 94 +> #define CLKID_MPLL2 95 > +#define CLKID_NAND_SEL 96 > +#define CLKID_NAND_DIV 97 > +#define CLKID_NAND_CLK 98 -> ? +> > -#define CLK_NR_CLKS 96 > +#define CLK_NR_CLKS 99 -> ? -> ?/* include the CLKIDs that have been made part of the stable DT binding */ -> ?#include <dt-bindings/clock/meson8b-clkc.h> +> +> /* include the CLKIDs that have been made part of the stable DT binding */ +> #include <dt-bindings/clock/meson8b-clkc.h> diff --git a/a/content_digest b/N1/content_digest index 0636cb2..740ae73 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,17 @@ "ref\020170401131001.9988-1-martin.blumenstingl@googlemail.com\0" "ref\020170401131001.9988-2-martin.blumenstingl@googlemail.com\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH 1/1] clk: meson: meson8b: add support for the NAND clocks\0" + "From\0Jerome Brunet <jbrunet@baylibre.com>\0" + "Subject\0Re: [PATCH 1/1] clk: meson: meson8b: add support for the NAND clocks\0" "Date\0Sun, 02 Apr 2017 17:38:16 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Martin Blumenstingl <martin.blumenstingl@googlemail.com>" + linux-clk@vger.kernel.org + " linux-amlogic@lists.infradead.org\0" + "Cc\0carlo@caione.org" + khilman@baylibre.com + linux-arm-kernel@lists.infradead.org + mturquette@baylibre.com + Stephen Boyd <sboyd@codeaurora.org> + " narmstrong@baylibre.com\0" "\00:1\0" "b\0" "On Sat, 2017-04-01 at 15:10 +0200, Martin Blumenstingl wrote:\n" @@ -55,19 +63,19 @@ "> \n" "> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n" "> ---\n" - "> ?drivers/clk/meson/meson8b.c | 53\n" + "> \302\240drivers/clk/meson/meson8b.c | 53\n" "> +++++++++++++++++++++++++++++++++++++++++++++\n" - "> ?drivers/clk/meson/meson8b.h |??6 ++++-\n" - "> ?2 files changed, 58 insertions(+), 1 deletion(-)\n" + "> \302\240drivers/clk/meson/meson8b.h |\302\240\302\2406 ++++-\n" + "> \302\2402 files changed, 58 insertions(+), 1 deletion(-)\n" "> \n" "> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c\n" "> index e9985503165c..b7f3cf8ed386 100644\n" "> --- a/drivers/clk/meson/meson8b.c\n" "> +++ b/drivers/clk/meson/meson8b.c\n" "> @@ -403,6 +403,53 @@ struct clk_gate meson8b_clk81 = {\n" - "> ?\t},\n" - "> ?};\n" - "> ?\n" + "> \302\240\t},\n" + "> \302\240};\n" + "> \302\240\n" "> +static u32 mux_table_nand[]\t= { 0, 1, 2, 3, 4 };\n" "You can drop this table, you don't need it.\n" "\n" @@ -140,67 +148,67 @@ "> +\t},\n" "> +};\n" "> +\n" - "> ?/* Everything Else (EE) domain gates */\n" - "> ?\n" - "> ?static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);\n" + "> \302\240/* Everything Else (EE) domain gates */\n" + "> \302\240\n" + "> \302\240static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);\n" "> @@ -584,6 +631,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data\n" "> = {\n" - "> ?\t\t[CLKID_MPLL0]\t\t????= &meson8b_mpll0.hw,\n" - "> ?\t\t[CLKID_MPLL1]\t\t????= &meson8b_mpll1.hw,\n" - "> ?\t\t[CLKID_MPLL2]\t\t????= &meson8b_mpll2.hw,\n" - "> +\t\t[CLKID_NAND_SEL]\t????= &meson8b_nand_clk_sel.hw,\n" - "> +\t\t[CLKID_NAND_DIV]\t????= &meson8b_nand_clk_div.hw,\n" - "> +\t\t[CLKID_NAND_CLK]\t????= &meson8b_nand_clk_gate.hw,\n" - "> ?\t},\n" - "> ?\t.num = CLK_NR_CLKS,\n" - "> ?};\n" + "> \302\240\t\t[CLKID_MPLL0]\t\t\302\240\302\240\302\240\302\240= &meson8b_mpll0.hw,\n" + "> \302\240\t\t[CLKID_MPLL1]\t\t\302\240\302\240\302\240\302\240= &meson8b_mpll1.hw,\n" + "> \302\240\t\t[CLKID_MPLL2]\t\t\302\240\302\240\302\240\302\240= &meson8b_mpll2.hw,\n" + "> +\t\t[CLKID_NAND_SEL]\t\302\240\302\240\302\240\302\240= &meson8b_nand_clk_sel.hw,\n" + "> +\t\t[CLKID_NAND_DIV]\t\302\240\302\240\302\240\302\240= &meson8b_nand_clk_div.hw,\n" + "> +\t\t[CLKID_NAND_CLK]\t\302\240\302\240\302\240\302\240= &meson8b_nand_clk_gate.hw,\n" + "> \302\240\t},\n" + "> \302\240\t.num = CLK_NR_CLKS,\n" + "> \302\240};\n" "> @@ -679,14 +729,17 @@ static struct clk_gate *const meson8b_clk_gates[] = {\n" - "> ?\t&meson8b_ao_ahb_sram,\n" - "> ?\t&meson8b_ao_ahb_bus,\n" - "> ?\t&meson8b_ao_iface,\n" + "> \302\240\t&meson8b_ao_ahb_sram,\n" + "> \302\240\t&meson8b_ao_ahb_bus,\n" + "> \302\240\t&meson8b_ao_iface,\n" "> +\t&meson8b_nand_clk_gate,\n" - "> ?};\n" - "> ?\n" - "> ?static struct clk_mux *const meson8b_clk_muxes[] = {\n" - "> ?\t&meson8b_mpeg_clk_sel,\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240static struct clk_mux *const meson8b_clk_muxes[] = {\n" + "> \302\240\t&meson8b_mpeg_clk_sel,\n" "> +\t&meson8b_nand_clk_sel,\n" - "> ?};\n" - "> ?\n" - "> ?static struct clk_divider *const meson8b_clk_dividers[] = {\n" - "> ?\t&meson8b_mpeg_clk_div,\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240static struct clk_divider *const meson8b_clk_dividers[] = {\n" + "> \302\240\t&meson8b_mpeg_clk_div,\n" "> +\t&meson8b_nand_clk_div,\n" - "> ?};\n" - "> ?\n" - "> ?static int meson8b_clkc_probe(struct platform_device *pdev)\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240static int meson8b_clkc_probe(struct platform_device *pdev)\n" "> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h\n" "> index 3881defc8644..cbb8001b5fe8 100644\n" "> --- a/drivers/clk/meson/meson8b.h\n" "> +++ b/drivers/clk/meson/meson8b.h\n" "> @@ -37,6 +37,7 @@\n" - "> ?#define HHI_GCLK_AO\t\t\t0x154 /* 0x55 offset in data sheet\n" + "> \302\240#define HHI_GCLK_AO\t\t\t0x154 /* 0x55 offset in data sheet\n" "> */\n" - "> ?#define HHI_SYS_CPU_CLK_CNTL1\t\t0x15c /* 0x57 offset in data\n" + "> \302\240#define HHI_SYS_CPU_CLK_CNTL1\t\t0x15c /* 0x57 offset in data\n" "> sheet */\n" - "> ?#define HHI_MPEG_CLK_CNTL\t\t0x174 /* 0x5d offset in data sheet\n" + "> \302\240#define HHI_MPEG_CLK_CNTL\t\t0x174 /* 0x5d offset in data sheet\n" "> */\n" "> +#define HHI_NAND_CLK_CNTL\t\t0x25c /* 0x97 offset in data sheet\n" "> */\n" - "> ?#define HHI_MPLL_CNTL\t\t\t0x280 /* 0xa0 offset in data\n" + "> \302\240#define HHI_MPLL_CNTL\t\t\t0x280 /* 0xa0 offset in data\n" "> sheet */\n" - "> ?#define HHI_SYS_PLL_CNTL\t\t0x300 /* 0xc0 offset in data sheet */\n" - "> ?#define HHI_VID_PLL_CNTL\t\t0x320 /* 0xc8 offset in data sheet */\n" + "> \302\240#define HHI_SYS_PLL_CNTL\t\t0x300 /* 0xc0 offset in data sheet */\n" + "> \302\240#define HHI_VID_PLL_CNTL\t\t0x320 /* 0xc8 offset in data sheet */\n" "> @@ -160,8 +161,11 @@\n" - "> ?#define CLKID_MPLL0\t\t93\n" - "> ?#define CLKID_MPLL1\t\t94\n" - "> ?#define CLKID_MPLL2\t\t95\n" + "> \302\240#define CLKID_MPLL0\t\t93\n" + "> \302\240#define CLKID_MPLL1\t\t94\n" + "> \302\240#define CLKID_MPLL2\t\t95\n" "> +#define CLKID_NAND_SEL\t\t96\n" "> +#define CLKID_NAND_DIV\t\t97\n" "> +#define CLKID_NAND_CLK\t\t98\n" - "> ?\n" + "> \302\240\n" "> -#define CLK_NR_CLKS\t\t96\n" "> +#define CLK_NR_CLKS\t\t99\n" - "> ?\n" - "> ?/* include the CLKIDs that have been made part of the stable DT binding */\n" - > ?#include <dt-bindings/clock/meson8b-clkc.h> + "> \302\240\n" + "> \302\240/* include the CLKIDs that have been made part of the stable DT binding */\n" + "> \302\240#include <dt-bindings/clock/meson8b-clkc.h>" -5f6c343155988ad447480111b4ddf083761fa3ed3bbffd3e3794c48dc4f5db77 +ecd602498bd9a5483dd5827c634cadffaaa96d6af6a2aacb901f951f86e0a237
diff --git a/a/content_digest b/N2/content_digest index 0636cb2..707ae41 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,7 +3,7 @@ "From\0jbrunet@baylibre.com (Jerome Brunet)\0" "Subject\0[PATCH 1/1] clk: meson: meson8b: add support for the NAND clocks\0" "Date\0Sun, 02 Apr 2017 17:38:16 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Sat, 2017-04-01 at 15:10 +0200, Martin Blumenstingl wrote:\n" @@ -203,4 +203,4 @@ "> ?/* include the CLKIDs that have been made part of the stable DT binding */\n" > ?#include <dt-bindings/clock/meson8b-clkc.h> -5f6c343155988ad447480111b4ddf083761fa3ed3bbffd3e3794c48dc4f5db77 +057a61376d6519d385817a1f78ef87d2b79af5709854d9430e70fd3e574cae67
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