diff for duplicates of <1491408370.9650.24.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index 6bc3ed8..e6e12f6 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,57 +1,68 @@ -SGkgU3RlcGhlbiwNCg0KT24gVHVlLCAyMDE3LTA0LTA0IGF0IDE4OjM1IC0wNzAwLCBTdGVwaGVu -IEJveWQgd3JvdGU6DQo+ID4gK8KgwqDCoMKgwqAucGxsX3RhYmxlID0gKHN0cnVjdCBwbGxfb2Zf -dGFibGUgW10pew0KPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHsNCj4gPiArwqDCoMKg -wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgLnByYXRlID0gMjcwMDAwMDAsDQo+ -IA0KPiBDYW4gdGhpcyBiZSBhbm90aGVyIGNsayBpbiB0aGUgZnJhbWV3b3JrIGluc3RlYWQgb2Yg -aGFyZGNvZGluZw0KPiB0aGUgcGFyZW50IHJhdGU/DQoNCkluIGZhY3QgdGhlcmUgaXMgYW5vdGhl -ciBjbGsgaW4gdGhlIGZyYW1ld29yayB0aGF0IHJlcHJlc2VudHMgdGhpcyBwYXJlbnQgY2xvY2su -IEJ1dCB0aGlzIGZpZWxkIGlzIG5lZWRlZCB0byBnZXQNCmFwcHJvcHJpYXRlIHBsbF9jZmdfdGFi -bGUgYXMgaXQgZGVwZW5kcyBvbiBwYXJlbnQgY2xvY2sgZnJlcXVlbmN5LiBCZWxvdyBpbiBwbGxf -Y2ZnX2dldCBmdW5jdGlvbiB3ZSBhcmUgc2VhcmNoaW5nIGZvcg0KdGhlIGNvcnJlY3QgdGFibGUg -Y29tcGFyaW5nIC5wYXJlbnRfbm9kZSBmaWVsZCB3aXRoIHJlYWwgaGFyZHdhcmUgcGFyZW50IGNs -b2NrIGZyZXF1ZW5jeToNCi0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0+OC0tLS0t -LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQ0KZm9yIChpID0gMDsgcGxsX3RhYmxlW2ld -LnByYXRlICE9IDA7IGkrKykNCsKgIMKgIGlmIChwbGxfdGFibGVbaV0ucHJhdGUgPT0gcHJhdGUp -DQrCoCDCoCDCoCDCoCByZXR1cm4gcGxsX3RhYmxlW2ldLnBsbF9jZmdfdGFibGU7DQotLS0tLS0t -LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tPjgtLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t -LS0tLS0tLS0NCg0KPiANCj4gPiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg -wqDCoMKgLnBsbF9jZmdfdGFibGUgPSAoc3RydWN0IHBsbF9jZmcgW10pew0KPiA+ICvCoMKgwqDC -oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgeyAyNTIw -MDAwMCwgMSwgODQsIDkwIH0sDQo+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg -wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqB7IDUwMDAwMDAwLCAxLCAxMDAsIDU0IH0sDQo+ID4g -K8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg -wqB7IDc0MjUwMDAwLCAxLCA0NCwgMTYgfSwNCj4gPiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg -wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHsgfSwNCj4gPiArwqDCoMKgwqDCoMKg -wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgfSwNCj4gPiArwqDCoMKgwqDCoMKgwqDCoMKg -wqDCoMKgwqB9LA0KPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoC8qIFVzZWQgYXMgbGlz -dCBsaW1pdGVyICovDQo+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgeyB9LA0KPiANCj4g -VGhlcmUncyBvbmx5IGV2ZXIgb25lLCBzbyBJJ20gY29uZnVzZWQgd2h5IHdlJ3JlIG1ha2luZyBh -IGxpc3QuDQoNCkJ5IHRoaXMgcGF0Y2ggd2Ugb25seSBhZGQgc3VwcG9ydCBvZiBjb3JlIGFyYyBw -bGwgYW5kIHBndSBwbGwgYW5kIHRvZGF5IHRoZXkgYXJlIGNsb2NrZWQgYnkgdGhlIG9ubHkgcGFy -ZW50IGNsb2Nrcw0KaW50cm9kdWNlZCBoZXJlLiBCdXQgb3RoZXIgcGxscyBvbiBheHMxMHggbWF5 -IGJlIGRyaXZlbiBieSBkaWZmZXJlbnQgb3IgY29uZmlndXJhYmxlIGNsb2Nrcywgc28gaW4gc3Vj -aCBjYXNlcyB3ZSB3aWxsDQpoYXZlIG1vcmUgdGhhbiBvbmUgZW50cnkgaW4gdGhpcyBsaXN0LiBB -bmQgd2UgYXJlIGdvaW5nIHRvIGFkZCBtb3JlIHN1cHBvcnRlZCBwbGxzIHRvIHRoaXMgZHJpdmVy -IGluIHRoZSBuZWFyZXN0IGZ1dHVyZS4NCg0KPiA+ICsNCj4gPiArwqDCoMKgwqDCoGNsayA9IGNs -a19yZWdpc3RlcihOVUxMLCAmcGxsX2Nsay0+aHcpOw0KPiA+ICvCoMKgwqDCoMKgaWYgKElTX0VS -UihjbGspKSB7DQo+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgcHJfZXJyKCJmYWlsZWQg -dG8gcmVnaXN0ZXIgJXMgY2xvY2sgKCVsZClcbiIsDQo+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKg -wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqBub2RlLT5uYW1lLCBQVFJfRVJS -KGNsaykpOw0KPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoGtmcmVlKHBsbF9jbGspOw0K -PiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHJldHVybjsNCj4gPiArwqDCoMKgwqDCoH0N -Cj4gPiArDQo+ID4gK8KgwqDCoMKgwqBvZl9jbGtfYWRkX3Byb3ZpZGVyKG5vZGUsIG9mX2Nsa19z -cmNfc2ltcGxlX2dldCwgY2xrKTsNCj4gDQo+IENhbiB5b3UgcGxlYXNlIHVzZSB0aGUgY2xrX2h3 -IGJhc2VkIHByb3ZpZGVyIGFuZCBjbGsgcmVnaXN0cmF0aW9uDQo+IGZ1bmN0aW9ucz8NCg0KU3Vy -ZS4gQ291bGQgeW91IGJlIHNvIGtpbmQgdG8gZXhwbGFpbiB3aGF0IGlzIHRoZSBkaWZmZXJlbmNl -IGJldHdlZW4gaHcgYW5kIG5vbi1odyBiYXNlZCBwcm92aWRlciBhbmQgY2xrIHJlZ2lzdHJhdGlv -bg0KZnVuY3Rpb25zIHBsZWFzZT8gSW4gd2hpY2ggY2FzZXMgdGhleSBhcmUgcHJlZmVycmVkP8Kg -DQoNCj4gDQo+ID4gK30NCj4gPiArDQo+ID4gK0NMS19PRl9ERUNMQVJFKGF4czEweF9wbGxfY2xv -Y2ssICJzbnBzLGF4czEweC1hcmMtcGxsLWNsb2NrIiwgb2ZfcGxsX2Nsa19zZXR1cCk7DQo+IA0K -PiBEb2VzIHRoaXMgbmVlZCB0byBiZSBDTEtfT0ZfREVDTEFSRV9EUklWRVI/IEkgbWVhbiBkb2Vz -IHRoZQ0KPiBkcml2ZXIgbmVlZCB0byBwcm9iZSBhbmQgYWxzbyBoYXZlIHRoaXMgb2YgZGVjbGFy -ZSBoYXBwZW4/IElzIHRoZQ0KPiBQTEwgc3BlY2lhbCBhbmQgbmVlZHMgdG8gYmUgdXNlZCBmb3Ig -dGhlIHRpbWVycz8NCg0KSXQgaXMgc3BlY2lhbCBhbmQgaXMgdXNlZCBmb3IgdGhlIHRpbWVycywg -c28gd2UgaGF2ZSB0byBDTEtfT0ZfREVDTEFSRSBpdC4gT24gdGhlIG90aGVyIGhhbmQgc2ltaWxh -ciBwbGwgaXMgdXNlZCB0bw0KZHJpdmUgUEdVIGNsb2NrIGZyZXF1ZW5jeSBhbmQgb3RoZXIgc3Vi -c3lzdGVtcyBhbmQgc28gd2UgYWRkIHVzdWFsIHByb2JlIGZ1bmMuDQoNCi0tIA0KQmVzdCByZWdh -cmRzLA0KVmxhZCBaYWtoYXJvdiA8dnpha2hhckBzeW5vcHN5cy5jb20+ +Hi Stephen, + +On Tue, 2017-04-04@18:35 -0700, Stephen Boyd wrote: +> > +?????.pll_table = (struct pll_of_table []){ +> > +?????????????{ +> > +?????????????????????.prate = 27000000, +> +> Can this be another clk in the framework instead of hardcoding +> the parent rate? + +In fact there is another clk in the framework that represents this parent clock. But this field is needed to get +appropriate pll_cfg_table as it depends on parent clock frequency. Below in pll_cfg_get function we are searching for +the correct table comparing .parent_node field with real hardware parent clock frequency: +---------------------------------->8------------------------------------ +for (i = 0; pll_table[i].prate != 0; i++) +? ? if (pll_table[i].prate == prate) +? ? ? ? return pll_table[i].pll_cfg_table; +---------------------------------->8------------------------------------ + +> +> > +?????????????????????.pll_cfg_table = (struct pll_cfg []){ +> > +?????????????????????????????{ 25200000, 1, 84, 90 }, +> > +?????????????????????????????{ 50000000, 1, 100, 54 }, +> > +?????????????????????????????{ 74250000, 1, 44, 16 }, +> > +?????????????????????????????{ }, +> > +?????????????????????}, +> > +?????????????}, +> > +?????????????/* Used as list limiter */ +> > +?????????????{ }, +> +> There's only ever one, so I'm confused why we're making a list. + +By this patch we only add support of core arc pll and pgu pll and today they are clocked by the only parent clocks +introduced here. But other plls on axs10x may be driven by different or configurable clocks, so in such cases we will +have more than one entry in this list. And we are going to add more supported plls to this driver in the nearest future. + +> > + +> > +?????clk = clk_register(NULL, &pll_clk->hw); +> > +?????if (IS_ERR(clk)) { +> > +?????????????pr_err("failed to register %s clock (%ld)\n", +> > +?????????????????????????????node->name, PTR_ERR(clk)); +> > +?????????????kfree(pll_clk); +> > +?????????????return; +> > +?????} +> > + +> > +?????of_clk_add_provider(node, of_clk_src_simple_get, clk); +> +> Can you please use the clk_hw based provider and clk registration +> functions? + +Sure. Could you be so kind to explain what is the difference between hw and non-hw based provider and clk registration +functions please? In which cases they are preferred?? + +> +> > +} +> > + +> > +CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock", of_pll_clk_setup); +> +> Does this need to be CLK_OF_DECLARE_DRIVER? I mean does the +> driver need to probe and also have this of declare happen? Is the +> PLL special and needs to be used for the timers? + +It is special and is used for the timers, so we have to CLK_OF_DECLARE it. On the other hand similar pll is used to +drive PGU clock frequency and other subsystems and so we add usual probe func. + +-- +Best regards, +Vlad Zakharov <vzakhar at synopsys.com> diff --git a/a/content_digest b/N1/content_digest index ee1f5ab..b6d5cce 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,74 +1,78 @@ "ref\01487682670-4164-1-git-send-email-vzakhar@synopsys.com\0" "ref\020170405013525.GJ18246@codeaurora.org\0" - "From\0Vlad Zakharov <Vladislav.Zakharov@synopsys.com>\0" - "Subject\0Re: [PATCH v2] clk/axs10x: introduce AXS10X pll driver\0" + "From\0Vladislav.Zakharov@synopsys.com (Vlad Zakharov)\0" + "Subject\0[PATCH v2] clk/axs10x: introduce AXS10X pll driver\0" "Date\0Wed, 5 Apr 2017 16:06:11 +0000\0" - "To\0sboyd@codeaurora.org <sboyd@codeaurora.org>\0" - "Cc\0mark.rutland@arm.com <mark.rutland@arm.com>" - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - Jose.Abreu@synopsys.com <Jose.Abreu@synopsys.com> - mturquette@baylibre.com <mturquette@baylibre.com> - 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"Y2ssICJzbnBzLGF4czEweC1hcmMtcGxsLWNsb2NrIiwgb2ZfcGxsX2Nsa19zZXR1cCk7DQo+IA0K\n" - "PiBEb2VzIHRoaXMgbmVlZCB0byBiZSBDTEtfT0ZfREVDTEFSRV9EUklWRVI/IEkgbWVhbiBkb2Vz\n" - "IHRoZQ0KPiBkcml2ZXIgbmVlZCB0byBwcm9iZSBhbmQgYWxzbyBoYXZlIHRoaXMgb2YgZGVjbGFy\n" - "ZSBoYXBwZW4/IElzIHRoZQ0KPiBQTEwgc3BlY2lhbCBhbmQgbmVlZHMgdG8gYmUgdXNlZCBmb3Ig\n" - "dGhlIHRpbWVycz8NCg0KSXQgaXMgc3BlY2lhbCBhbmQgaXMgdXNlZCBmb3IgdGhlIHRpbWVycywg\n" - "c28gd2UgaGF2ZSB0byBDTEtfT0ZfREVDTEFSRSBpdC4gT24gdGhlIG90aGVyIGhhbmQgc2ltaWxh\n" - "ciBwbGwgaXMgdXNlZCB0bw0KZHJpdmUgUEdVIGNsb2NrIGZyZXF1ZW5jeSBhbmQgb3RoZXIgc3Vi\n" - "c3lzdGVtcyBhbmQgc28gd2UgYWRkIHVzdWFsIHByb2JlIGZ1bmMuDQoNCi0tIA0KQmVzdCByZWdh\n" - cmRzLA0KVmxhZCBaYWtoYXJvdiA8dnpha2hhckBzeW5vcHN5cy5jb20+ + "Hi Stephen,\n" + "\n" + "On Tue, 2017-04-04@18:35 -0700, Stephen Boyd wrote:\n" + "> > +?????.pll_table = (struct pll_of_table []){\n" + "> > +?????????????{\n" + "> > +?????????????????????.prate = 27000000,\n" + "> \n" + "> Can this be another clk in the framework instead of hardcoding\n" + "> the parent rate?\n" + "\n" + "In fact there is another clk in the framework that represents this parent clock. But this field is needed to get\n" + "appropriate pll_cfg_table as it depends on parent clock frequency. Below in pll_cfg_get function we are searching for\n" + "the correct table comparing .parent_node field with real hardware parent clock frequency:\n" + "---------------------------------->8------------------------------------\n" + "for (i = 0; pll_table[i].prate != 0; i++)\n" + "? ? if (pll_table[i].prate == prate)\n" + "? ? ? ? return pll_table[i].pll_cfg_table;\n" + "---------------------------------->8------------------------------------\n" + "\n" + "> \n" + "> > +?????????????????????.pll_cfg_table = (struct pll_cfg []){\n" + "> > +?????????????????????????????{ 25200000, 1, 84, 90 },\n" + "> > +?????????????????????????????{ 50000000, 1, 100, 54 },\n" + "> > +?????????????????????????????{ 74250000, 1, 44, 16 },\n" + "> > +?????????????????????????????{ },\n" + "> > +?????????????????????},\n" + "> > +?????????????},\n" + "> > +?????????????/* Used as list limiter */\n" + "> > +?????????????{ },\n" + "> \n" + "> There's only ever one, so I'm confused why we're making a list.\n" + "\n" + "By this patch we only add support of core arc pll and pgu pll and today they are clocked by the only parent clocks\n" + "introduced here. But other plls on axs10x may be driven by different or configurable clocks, so in such cases we will\n" + "have more than one entry in this list. And we are going to add more supported plls to this driver in the nearest future.\n" + "\n" + "> > +\n" + "> > +?????clk = clk_register(NULL, &pll_clk->hw);\n" + "> > +?????if (IS_ERR(clk)) {\n" + "> > +?????????????pr_err(\"failed to register %s clock (%ld)\\n\",\n" + "> > +?????????????????????????????node->name, PTR_ERR(clk));\n" + "> > +?????????????kfree(pll_clk);\n" + "> > +?????????????return;\n" + "> > +?????}\n" + "> > +\n" + "> > +?????of_clk_add_provider(node, of_clk_src_simple_get, clk);\n" + "> \n" + "> Can you please use the clk_hw based provider and clk registration\n" + "> functions?\n" + "\n" + "Sure. Could you be so kind to explain what is the difference between hw and non-hw based provider and clk registration\n" + "functions please? In which cases they are preferred??\n" + "\n" + "> \n" + "> > +}\n" + "> > +\n" + "> > +CLK_OF_DECLARE(axs10x_pll_clock, \"snps,axs10x-arc-pll-clock\", of_pll_clk_setup);\n" + "> \n" + "> Does this need to be CLK_OF_DECLARE_DRIVER? I mean does the\n" + "> driver need to probe and also have this of declare happen? Is the\n" + "> PLL special and needs to be used for the timers?\n" + "\n" + "It is special and is used for the timers, so we have to CLK_OF_DECLARE it. On the other hand similar pll is used to\n" + "drive PGU clock frequency and other subsystems and so we add usual probe func.\n" + "\n" + "-- \n" + "Best regards,\n" + Vlad Zakharov <vzakhar at synopsys.com> -9fb937275697cc964e479c4649e5e1ddbad845373e30cc0701c03129666915ad +607c58027540a9026938c2e1e461fd9f2c82bbcf204ed15991fc4a444b52f4bb
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But this field is needed to get +appropriate pll_cfg_table as it depends on parent clock frequency. Below in pll_cfg_get function we are searching for +the correct table comparing .parent_node field with real hardware parent clock frequency: +---------------------------------->8------------------------------------ +for (i = 0; pll_table[i].prate != 0; i++) + if (pll_table[i].prate == prate) + return pll_table[i].pll_cfg_table; +---------------------------------->8------------------------------------ + +> +> > + .pll_cfg_table = (struct pll_cfg []){ +> > + { 25200000, 1, 84, 90 }, +> > + { 50000000, 1, 100, 54 }, +> > + { 74250000, 1, 44, 16 }, +> > + { }, +> > + }, +> > + }, +> > + /* Used as list limiter */ +> > + { }, +> +> There's only ever one, so I'm confused why we're making a list. + +By this patch we only add support of core arc pll and pgu pll and today they are clocked by the only parent clocks +introduced here. But other plls on axs10x may be driven by different or configurable clocks, so in such cases we will +have more than one entry in this list. And we are going to add more supported plls to this driver in the nearest future. + +> > + +> > + clk = clk_register(NULL, &pll_clk->hw); +> > + if (IS_ERR(clk)) { +> > + pr_err("failed to register %s clock (%ld)\n", +> > + node->name, PTR_ERR(clk)); +> > + kfree(pll_clk); +> > + return; +> > + } +> > + +> > + of_clk_add_provider(node, of_clk_src_simple_get, clk); +> +> Can you please use the clk_hw based provider and clk registration +> functions? + +Sure. Could you be so kind to explain what is the difference between hw and non-hw based provider and clk registration +functions please? In which cases they are preferred? + +> +> > +} +> > + +> > +CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock", of_pll_clk_setup); +> +> Does this need to be CLK_OF_DECLARE_DRIVER? I mean does the +> driver need to probe and also have this of declare happen? Is the +> PLL special and needs to be used for the timers? + +It is special and is used for the timers, so we have to CLK_OF_DECLARE it. On the other hand similar pll is used to +drive PGU clock frequency and other subsystems and so we add usual probe func. + +-- +Best regards, +Vlad Zakharov <vzakhar@synopsys.com> diff --git a/a/content_digest b/N2/content_digest index ee1f5ab..26f5621 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -13,62 +13,73 @@ " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" "\00:1\0" "b\0" - "SGkgU3RlcGhlbiwNCg0KT24gVHVlLCAyMDE3LTA0LTA0IGF0IDE4OjM1IC0wNzAwLCBTdGVwaGVu\n" - "IEJveWQgd3JvdGU6DQo+ID4gK8KgwqDCoMKgwqAucGxsX3RhYmxlID0gKHN0cnVjdCBwbGxfb2Zf\n" - "dGFibGUgW10pew0KPiA+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHsNCj4gPiArwqDCoMKg\n" - "wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgLnByYXRlID0gMjcwMDAwMDAsDQo+\n" - "IA0KPiBDYW4gdGhpcyBiZSBhbm90aGVyIGNsayBpbiB0aGUgZnJhbWV3b3JrIGluc3RlYWQgb2Yg\n" - "aGFyZGNvZGluZw0KPiB0aGUgcGFyZW50IHJhdGU/DQoNCkluIGZhY3QgdGhlcmUgaXMgYW5vdGhl\n" - "ciBjbGsgaW4gdGhlIGZyYW1ld29yayB0aGF0IHJlcHJlc2VudHMgdGhpcyBwYXJlbnQgY2xvY2su\n" - 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"bg0KZnVuY3Rpb25zIHBsZWFzZT8gSW4gd2hpY2ggY2FzZXMgdGhleSBhcmUgcHJlZmVycmVkP8Kg\n" - "DQoNCj4gDQo+ID4gK30NCj4gPiArDQo+ID4gK0NMS19PRl9ERUNMQVJFKGF4czEweF9wbGxfY2xv\n" - "Y2ssICJzbnBzLGF4czEweC1hcmMtcGxsLWNsb2NrIiwgb2ZfcGxsX2Nsa19zZXR1cCk7DQo+IA0K\n" - "PiBEb2VzIHRoaXMgbmVlZCB0byBiZSBDTEtfT0ZfREVDTEFSRV9EUklWRVI/IEkgbWVhbiBkb2Vz\n" - "IHRoZQ0KPiBkcml2ZXIgbmVlZCB0byBwcm9iZSBhbmQgYWxzbyBoYXZlIHRoaXMgb2YgZGVjbGFy\n" - "ZSBoYXBwZW4/IElzIHRoZQ0KPiBQTEwgc3BlY2lhbCBhbmQgbmVlZHMgdG8gYmUgdXNlZCBmb3Ig\n" - "dGhlIHRpbWVycz8NCg0KSXQgaXMgc3BlY2lhbCBhbmQgaXMgdXNlZCBmb3IgdGhlIHRpbWVycywg\n" - "c28gd2UgaGF2ZSB0byBDTEtfT0ZfREVDTEFSRSBpdC4gT24gdGhlIG90aGVyIGhhbmQgc2ltaWxh\n" - "ciBwbGwgaXMgdXNlZCB0bw0KZHJpdmUgUEdVIGNsb2NrIGZyZXF1ZW5jeSBhbmQgb3RoZXIgc3Vi\n" - "c3lzdGVtcyBhbmQgc28gd2UgYWRkIHVzdWFsIHByb2JlIGZ1bmMuDQoNCi0tIA0KQmVzdCByZWdh\n" - cmRzLA0KVmxhZCBaYWtoYXJvdiA8dnpha2hhckBzeW5vcHN5cy5jb20+ + "Hi Stephen,\n" + "\n" + "On Tue, 2017-04-04 at 18:35 -0700, Stephen Boyd wrote:\n" + "> > +\302\240\302\240\302\240\302\240\302\240.pll_table = (struct pll_of_table []){\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.prate = 27000000,\n" + "> \n" + "> Can this be another clk in the framework instead of hardcoding\n" + "> the parent rate?\n" + "\n" + "In fact there is another clk in the framework that represents this parent clock. But this field is needed to get\n" + "appropriate pll_cfg_table as it depends on parent clock frequency. Below in pll_cfg_get function we are searching for\n" + "the correct table comparing .parent_node field with real hardware parent clock frequency:\n" + "---------------------------------->8------------------------------------\n" + "for (i = 0; pll_table[i].prate != 0; i++)\n" + "\302\240 \302\240 if (pll_table[i].prate == prate)\n" + "\302\240 \302\240 \302\240 \302\240 return pll_table[i].pll_cfg_table;\n" + "---------------------------------->8------------------------------------\n" + "\n" + "> \n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.pll_cfg_table = (struct pll_cfg []){\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ 25200000, 1, 84, 90 },\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ 50000000, 1, 100, 54 },\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ 74250000, 1, 44, 16 },\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ },\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240},\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240},\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Used as list limiter */\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ },\n" + "> \n" + "> There's only ever one, so I'm confused why we're making a list.\n" + "\n" + "By this patch we only add support of core arc pll and pgu pll and today they are clocked by the only parent clocks\n" + "introduced here. But other plls on axs10x may be driven by different or configurable clocks, so in such cases we will\n" + "have more than one entry in this list. And we are going to add more supported plls to this driver in the nearest future.\n" + "\n" + "> > +\n" + "> > +\302\240\302\240\302\240\302\240\302\240clk = clk_register(NULL, &pll_clk->hw);\n" + "> > +\302\240\302\240\302\240\302\240\302\240if (IS_ERR(clk)) {\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240pr_err(\"failed to register %s clock (%ld)\\n\",\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240node->name, PTR_ERR(clk));\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240kfree(pll_clk);\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return;\n" + "> > +\302\240\302\240\302\240\302\240\302\240}\n" + "> > +\n" + "> > +\302\240\302\240\302\240\302\240\302\240of_clk_add_provider(node, of_clk_src_simple_get, clk);\n" + "> \n" + "> Can you please use the clk_hw based provider and clk registration\n" + "> functions?\n" + "\n" + "Sure. Could you be so kind to explain what is the difference between hw and non-hw based provider and clk registration\n" + "functions please? In which cases they are preferred?\302\240\n" + "\n" + "> \n" + "> > +}\n" + "> > +\n" + "> > +CLK_OF_DECLARE(axs10x_pll_clock, \"snps,axs10x-arc-pll-clock\", of_pll_clk_setup);\n" + "> \n" + "> Does this need to be CLK_OF_DECLARE_DRIVER? I mean does the\n" + "> driver need to probe and also have this of declare happen? Is the\n" + "> PLL special and needs to be used for the timers?\n" + "\n" + "It is special and is used for the timers, so we have to CLK_OF_DECLARE it. On the other hand similar pll is used to\n" + "drive PGU clock frequency and other subsystems and so we add usual probe func.\n" + "\n" + "-- \n" + "Best regards,\n" + Vlad Zakharov <vzakhar@synopsys.com> -9fb937275697cc964e479c4649e5e1ddbad845373e30cc0701c03129666915ad +94e63ed268dc4670ff21773c16c711c41bc258a2ef31b9af64e871c872bfbf39
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