diff for duplicates of <1492518695.24567.56.camel@linux.intel.com> diff --git a/a/1.txt b/N1/1.txt index 682bb7a..4b8f0f4 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,4 +1,4 @@ -On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote: +On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote: > This patch adds support for the DW AXI DMAC controller. > > DW AXI DMAC is a part of upcoming development board from Synopsys. @@ -22,7 +22,7 @@ On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote: > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of -> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the +> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ @@ -56,7 +56,7 @@ Can't you have this in one header? > +#include "dmaengine.h" > +#include "virt-dma.h" -> +#define AXI_DMA_BUSWIDTHS ??\ +> +#define AXI_DMA_BUSWIDTHS \ > + (DMA_SLAVE_BUSWIDTH_1_BYTE | \ > + DMA_SLAVE_BUSWIDTH_2_BYTES | \ > + DMA_SLAVE_BUSWIDTH_4_BYTES | \ @@ -128,7 +128,7 @@ makes perplexity for nothing here) > +static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, > dma_addr_t src, -> + ???dma_addr_t dst, size_t len) +> + dma_addr_t dst, size_t len) > +{ > + u32 max_width = chan->chip->dw->hdata->m_data_width; @@ -164,7 +164,7 @@ Can you elaborate why virtual channel management is not working for you? > +/* Called in chan locked context */ > +static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, -> + ??????struct axi_dma_desc *first) +> + struct axi_dma_desc *first) > +{ > + u32 reg, irq_mask; @@ -218,11 +218,11 @@ Redundant __func__ parameter for debug prints. > +static struct dma_async_tx_descriptor * > +dma_chan_prep_dma_sg(struct dma_chan *dchan, -> + ?????struct scatterlist *dst_sg, unsigned int +> + struct scatterlist *dst_sg, unsigned int > dst_nents, -> + ?????struct scatterlist *src_sg, unsigned int +> + struct scatterlist *src_sg, unsigned int > src_nents, -> + ?????unsigned long flags) +> + unsigned long flags) > +{ > + struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); > + struct axi_dma_desc *first = NULL, *desc = NULL, *prev = @@ -256,7 +256,7 @@ Ditto for __func__. If we need those checks they should go to dmaengine.h/dmaengine.c. > +static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, -> + ???struct axi_dma_desc *desc_head) +> + struct axi_dma_desc *desc_head) > +{ > + struct axi_dma_desc *desc; > + @@ -301,7 +301,7 @@ processed successfully. > + val = axi_dma_ioread32(chan->chip, DMAC_CHEN); > + val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | -> + ???????BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; +> + BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; > + axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); You have helpers which you don't use. Why? @@ -337,7 +337,7 @@ at least once. > + val = axi_dma_ioread32(chan->chip, DMAC_CHEN); > + val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); -> + val |=??(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); +> + val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); > + axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); Use helper. @@ -435,13 +435,13 @@ Ditto. > + > + ret = devm_request_irq(chip->dev, chip->irq, > dw_axi_dma_intretupt, -> + ???????IRQF_SHARED, DRV_NAME, chip); +> + IRQF_SHARED, DRV_NAME, chip); > + if (ret) > + return ret; > + > + /* Lli address must be aligned to a 64-byte boundary */ > + dw->desc_pool = dmam_pool_create(DRV_NAME, chip->dev, -> + ?sizeof(struct axi_dma_desc), +> + sizeof(struct axi_dma_desc), > 64, 0); > + if (!dw->desc_pool) { > + dev_err(chip->dev, "No memory for descriptors dma @@ -495,11 +495,11 @@ Ditto. > + pm_runtime_enable(chip->dev); > + > + /* -> + ?* We can't just call pm_runtime_get here instead of -> + ?* pm_runtime_get_noresume + axi_dma_runtime_resume because +> + * We can't just call pm_runtime_get here instead of +> + * pm_runtime_get_noresume + axi_dma_runtime_resume because > we need -> + ?* driver to work also without Runtime PM. -> + ?*/ +> + * driver to work also without Runtime PM. +> + */ > + pm_runtime_get_noresume(chip->dev); > + ret = axi_dma_runtime_resume(chip->dev); > + if (ret < 0) @@ -515,7 +515,7 @@ Ditto. > + > + dev_info(chip->dev, "DesignWare AXI DMA Controller, %d > channels\n", -> + ?dw->hdata->nr_channels); +> + dw->hdata->nr_channels); > + > + return 0; > + @@ -830,5 +830,9 @@ GENMASK() > +}; -- -Andy Shevchenko <andriy.shevchenko at linux.intel.com> +Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Intel Finland Oy +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 4d69067..09dc0ca 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,12 +1,21 @@ "ref\01491573855-1039-1-git-send-email-Eugeniy.Paltsev@synopsys.com\0" "ref\01491573855-1039-3-git-send-email-Eugeniy.Paltsev@synopsys.com\0" - "From\0andriy.shevchenko@linux.intel.com (Andy Shevchenko)\0" - "Subject\0[PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver\0" + "ref\01491573855-1039-3-git-send-email-Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org\0" + "From\0Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>\0" + "Subject\0Re: [PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver\0" "Date\0Tue, 18 Apr 2017 15:31:35 +0300\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0Eugeniy Paltsev <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>" + " dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "Cc\0linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + Dan Williams <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> + Vinod Koul <vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + " Alexey Brodkin <Alexey.Brodkin-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>\0" "\00:1\0" "b\0" - "On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote:\n" + "On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote:\n" "> This patch adds support for the DW AXI DMAC controller.\n" "> \n" "> DW AXI DMAC is a part of upcoming development board from Synopsys.\n" @@ -30,7 +39,7 @@ "> + *\n" "> + * This program is distributed in the hope that it will be useful,\n" "> + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n" - "> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the\n" + "> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\302\240\302\240See the\n" "> + * GNU General Public License for more details.\n" "> + *\n" "> + */\n" @@ -64,7 +73,7 @@ "> +#include \"dmaengine.h\"\n" "> +#include \"virt-dma.h\"\n" "\n" - "> +#define AXI_DMA_BUSWIDTHS\t\t??\\\n" + "> +#define AXI_DMA_BUSWIDTHS\t\t\302\240\302\240\\\n" "> +\t(DMA_SLAVE_BUSWIDTH_1_BYTE\t| \\\n" "> +\tDMA_SLAVE_BUSWIDTH_2_BYTES\t| \\\n" "> +\tDMA_SLAVE_BUSWIDTH_4_BYTES\t| \\\n" @@ -136,7 +145,7 @@ "\n" "> +static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan,\n" "> dma_addr_t src,\n" - "> +\t\t\t\t???dma_addr_t dst, size_t len)\n" + "> +\t\t\t\t\302\240\302\240\302\240dma_addr_t dst, size_t len)\n" "> +{\n" "> +\tu32 max_width = chan->chip->dw->hdata->m_data_width;\n" "\n" @@ -172,7 +181,7 @@ "\n" "> +/* Called in chan locked context */\n" "> +static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,\n" - "> +\t\t\t\t??????struct axi_dma_desc *first)\n" + "> +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240struct axi_dma_desc *first)\n" "> +{\n" "\n" "> +\tu32 reg, irq_mask;\n" @@ -226,11 +235,11 @@ "\n" "> +static struct dma_async_tx_descriptor *\n" "> +dma_chan_prep_dma_sg(struct dma_chan *dchan,\n" - "> +\t\t?????struct scatterlist *dst_sg, unsigned int\n" + "> +\t\t\302\240\302\240\302\240\302\240\302\240struct scatterlist *dst_sg, unsigned int\n" "> dst_nents,\n" - "> +\t\t?????struct scatterlist *src_sg, unsigned int\n" + "> +\t\t\302\240\302\240\302\240\302\240\302\240struct scatterlist *src_sg, unsigned int\n" "> src_nents,\n" - "> +\t\t?????unsigned long flags)\n" + "> +\t\t\302\240\302\240\302\240\302\240\302\240unsigned long flags)\n" "> +{\n" "> +\tstruct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);\n" "> +\tstruct axi_dma_desc *first = NULL, *desc = NULL, *prev =\n" @@ -264,7 +273,7 @@ "If we need those checks they should go to dmaengine.h/dmaengine.c.\n" "\n" "> +static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,\n" - "> +\t\t\t\t???struct axi_dma_desc *desc_head)\n" + "> +\t\t\t\t\302\240\302\240\302\240struct axi_dma_desc *desc_head)\n" "> +{\n" "> +\tstruct axi_dma_desc *desc;\n" "> +\n" @@ -309,7 +318,7 @@ "\n" "> +\tval = axi_dma_ioread32(chan->chip, DMAC_CHEN);\n" "> +\tval |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |\n" - "> +\t???????BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;\n" + "> +\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;\n" "> +\taxi_dma_iowrite32(chan->chip, DMAC_CHEN, val);\n" "\n" "You have helpers which you don't use. Why?\n" @@ -345,7 +354,7 @@ "\n" "> +\tval = axi_dma_ioread32(chan->chip, DMAC_CHEN);\n" "> +\tval &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);\n" - "> +\tval |=??(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);\n" + "> +\tval |=\302\240\302\240(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);\n" "> +\taxi_dma_iowrite32(chan->chip, DMAC_CHEN, val);\n" "\n" "Use helper.\n" @@ -443,13 +452,13 @@ "> +\n" "> +\tret = devm_request_irq(chip->dev, chip->irq,\n" "> dw_axi_dma_intretupt,\n" - "> +\t\t\t???????IRQF_SHARED, DRV_NAME, chip);\n" + "> +\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240IRQF_SHARED, DRV_NAME, chip);\n" "> +\tif (ret)\n" "> +\t\treturn ret;\n" "> +\n" "> +\t/* Lli address must be aligned to a 64-byte boundary */\n" "> +\tdw->desc_pool = dmam_pool_create(DRV_NAME, chip->dev,\n" - "> +\t\t\t\t\t?sizeof(struct axi_dma_desc),\n" + "> +\t\t\t\t\t\302\240sizeof(struct axi_dma_desc),\n" "> 64, 0);\n" "> +\tif (!dw->desc_pool) {\n" "> +\t\tdev_err(chip->dev, \"No memory for descriptors dma\n" @@ -503,11 +512,11 @@ "> +\tpm_runtime_enable(chip->dev);\n" "> +\n" "> +\t/*\n" - "> +\t?* We can't just call pm_runtime_get here instead of\n" - "> +\t?* pm_runtime_get_noresume + axi_dma_runtime_resume because\n" + "> +\t\302\240* We can't just call pm_runtime_get here instead of\n" + "> +\t\302\240* pm_runtime_get_noresume + axi_dma_runtime_resume because\n" "> we need\n" - "> +\t?* driver to work also without Runtime PM.\n" - "> +\t?*/\n" + "> +\t\302\240* driver to work also without Runtime PM.\n" + "> +\t\302\240*/\n" "> +\tpm_runtime_get_noresume(chip->dev);\n" "> +\tret = axi_dma_runtime_resume(chip->dev);\n" "> +\tif (ret < 0)\n" @@ -523,7 +532,7 @@ "> +\n" "> +\tdev_info(chip->dev, \"DesignWare AXI DMA Controller, %d\n" "> channels\\n\",\n" - "> +\t\t?dw->hdata->nr_channels);\n" + "> +\t\t\302\240dw->hdata->nr_channels);\n" "> +\n" "> +\treturn 0;\n" "> +\n" @@ -838,7 +847,11 @@ "> +};\n" "\n" "-- \n" - "Andy Shevchenko <andriy.shevchenko at linux.intel.com>\n" - Intel Finland Oy + "Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>\n" + "Intel Finland Oy\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -75ff9bb89965ee9fce5164880cba04c13f3670210bfcf6eb2092c4cb0de11b84 +a79aa3cc263bcd1ac4d5a5168e73973d56edf4c28ff26a5cc3d71089f5bb5409
diff --git a/a/1.txt b/N2/1.txt index 682bb7a..11d7727 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,4 +1,4 @@ -On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote: +On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote: > This patch adds support for the DW AXI DMAC controller. > > DW AXI DMAC is a part of upcoming development board from Synopsys. @@ -22,7 +22,7 @@ On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote: > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of -> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the +> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ @@ -56,7 +56,7 @@ Can't you have this in one header? > +#include "dmaengine.h" > +#include "virt-dma.h" -> +#define AXI_DMA_BUSWIDTHS ??\ +> +#define AXI_DMA_BUSWIDTHS \ > + (DMA_SLAVE_BUSWIDTH_1_BYTE | \ > + DMA_SLAVE_BUSWIDTH_2_BYTES | \ > + DMA_SLAVE_BUSWIDTH_4_BYTES | \ @@ -128,7 +128,7 @@ makes perplexity for nothing here) > +static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, > dma_addr_t src, -> + ???dma_addr_t dst, size_t len) +> + dma_addr_t dst, size_t len) > +{ > + u32 max_width = chan->chip->dw->hdata->m_data_width; @@ -164,7 +164,7 @@ Can you elaborate why virtual channel management is not working for you? > +/* Called in chan locked context */ > +static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, -> + ??????struct axi_dma_desc *first) +> + struct axi_dma_desc *first) > +{ > + u32 reg, irq_mask; @@ -218,11 +218,11 @@ Redundant __func__ parameter for debug prints. > +static struct dma_async_tx_descriptor * > +dma_chan_prep_dma_sg(struct dma_chan *dchan, -> + ?????struct scatterlist *dst_sg, unsigned int +> + struct scatterlist *dst_sg, unsigned int > dst_nents, -> + ?????struct scatterlist *src_sg, unsigned int +> + struct scatterlist *src_sg, unsigned int > src_nents, -> + ?????unsigned long flags) +> + unsigned long flags) > +{ > + struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); > + struct axi_dma_desc *first = NULL, *desc = NULL, *prev = @@ -256,7 +256,7 @@ Ditto for __func__. If we need those checks they should go to dmaengine.h/dmaengine.c. > +static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, -> + ???struct axi_dma_desc *desc_head) +> + struct axi_dma_desc *desc_head) > +{ > + struct axi_dma_desc *desc; > + @@ -301,7 +301,7 @@ processed successfully. > + val = axi_dma_ioread32(chan->chip, DMAC_CHEN); > + val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | -> + ???????BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; +> + BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; > + axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); You have helpers which you don't use. Why? @@ -337,7 +337,7 @@ at least once. > + val = axi_dma_ioread32(chan->chip, DMAC_CHEN); > + val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); -> + val |=??(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); +> + val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); > + axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); Use helper. @@ -435,13 +435,13 @@ Ditto. > + > + ret = devm_request_irq(chip->dev, chip->irq, > dw_axi_dma_intretupt, -> + ???????IRQF_SHARED, DRV_NAME, chip); +> + IRQF_SHARED, DRV_NAME, chip); > + if (ret) > + return ret; > + > + /* Lli address must be aligned to a 64-byte boundary */ > + dw->desc_pool = dmam_pool_create(DRV_NAME, chip->dev, -> + ?sizeof(struct axi_dma_desc), +> + sizeof(struct axi_dma_desc), > 64, 0); > + if (!dw->desc_pool) { > + dev_err(chip->dev, "No memory for descriptors dma @@ -495,11 +495,11 @@ Ditto. > + pm_runtime_enable(chip->dev); > + > + /* -> + ?* We can't just call pm_runtime_get here instead of -> + ?* pm_runtime_get_noresume + axi_dma_runtime_resume because +> + * We can't just call pm_runtime_get here instead of +> + * pm_runtime_get_noresume + axi_dma_runtime_resume because > we need -> + ?* driver to work also without Runtime PM. -> + ?*/ +> + * driver to work also without Runtime PM. +> + */ > + pm_runtime_get_noresume(chip->dev); > + ret = axi_dma_runtime_resume(chip->dev); > + if (ret < 0) @@ -515,7 +515,7 @@ Ditto. > + > + dev_info(chip->dev, "DesignWare AXI DMA Controller, %d > channels\n", -> + ?dw->hdata->nr_channels); +> + dw->hdata->nr_channels); > + > + return 0; > + @@ -830,5 +830,5 @@ GENMASK() > +}; -- -Andy Shevchenko <andriy.shevchenko at linux.intel.com> +Andy Shevchenko <andriy.shevchenko@linux.intel.com> Intel Finland Oy diff --git a/a/content_digest b/N2/content_digest index 4d69067..d6f8b4a 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,12 +1,20 @@ "ref\01491573855-1039-1-git-send-email-Eugeniy.Paltsev@synopsys.com\0" "ref\01491573855-1039-3-git-send-email-Eugeniy.Paltsev@synopsys.com\0" - "From\0andriy.shevchenko@linux.intel.com (Andy Shevchenko)\0" - "Subject\0[PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver\0" + "From\0Andy Shevchenko <andriy.shevchenko@linux.intel.com>\0" + "Subject\0Re: [PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver\0" "Date\0Tue, 18 Apr 2017 15:31:35 +0300\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>" + " dmaengine@vger.kernel.org\0" + "Cc\0linux-kernel@vger.kernel.org" + devicetree@vger.kernel.org + linux-snps-arc@lists.infradead.org + Dan Williams <dan.j.williams@intel.com> + Vinod Koul <vinod.koul@intel.com> + Rob Herring <robh+dt@kernel.org> + " Alexey Brodkin <Alexey.Brodkin@synopsys.com>\0" "\00:1\0" "b\0" - "On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote:\n" + "On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote:\n" "> This patch adds support for the DW AXI DMAC controller.\n" "> \n" "> DW AXI DMAC is a part of upcoming development board from Synopsys.\n" @@ -30,7 +38,7 @@ "> + *\n" "> + * This program is distributed in the hope that it will be useful,\n" "> + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n" - "> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the\n" + "> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\302\240\302\240See the\n" "> + * GNU General Public License for more details.\n" "> + *\n" "> + */\n" @@ -64,7 +72,7 @@ "> +#include \"dmaengine.h\"\n" "> +#include \"virt-dma.h\"\n" "\n" - "> +#define AXI_DMA_BUSWIDTHS\t\t??\\\n" + "> +#define AXI_DMA_BUSWIDTHS\t\t\302\240\302\240\\\n" "> +\t(DMA_SLAVE_BUSWIDTH_1_BYTE\t| \\\n" "> +\tDMA_SLAVE_BUSWIDTH_2_BYTES\t| \\\n" "> +\tDMA_SLAVE_BUSWIDTH_4_BYTES\t| \\\n" @@ -136,7 +144,7 @@ "\n" "> +static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan,\n" "> dma_addr_t src,\n" - "> +\t\t\t\t???dma_addr_t dst, size_t len)\n" + "> +\t\t\t\t\302\240\302\240\302\240dma_addr_t dst, size_t len)\n" "> +{\n" "> +\tu32 max_width = chan->chip->dw->hdata->m_data_width;\n" "\n" @@ -172,7 +180,7 @@ "\n" "> +/* Called in chan locked context */\n" "> +static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,\n" - "> +\t\t\t\t??????struct axi_dma_desc *first)\n" + "> +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240struct axi_dma_desc *first)\n" "> +{\n" "\n" "> +\tu32 reg, irq_mask;\n" @@ -226,11 +234,11 @@ "\n" "> +static struct dma_async_tx_descriptor *\n" "> +dma_chan_prep_dma_sg(struct dma_chan *dchan,\n" - "> +\t\t?????struct scatterlist *dst_sg, unsigned int\n" + "> +\t\t\302\240\302\240\302\240\302\240\302\240struct scatterlist *dst_sg, unsigned int\n" "> dst_nents,\n" - "> +\t\t?????struct scatterlist *src_sg, unsigned int\n" + "> +\t\t\302\240\302\240\302\240\302\240\302\240struct scatterlist *src_sg, unsigned int\n" "> src_nents,\n" - "> +\t\t?????unsigned long flags)\n" + "> +\t\t\302\240\302\240\302\240\302\240\302\240unsigned long flags)\n" "> +{\n" "> +\tstruct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);\n" "> +\tstruct axi_dma_desc *first = NULL, *desc = NULL, *prev =\n" @@ -264,7 +272,7 @@ "If we need those checks they should go to dmaengine.h/dmaengine.c.\n" "\n" "> +static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,\n" - "> +\t\t\t\t???struct axi_dma_desc *desc_head)\n" + "> +\t\t\t\t\302\240\302\240\302\240struct axi_dma_desc *desc_head)\n" "> +{\n" "> +\tstruct axi_dma_desc *desc;\n" "> +\n" @@ -309,7 +317,7 @@ "\n" "> +\tval = axi_dma_ioread32(chan->chip, DMAC_CHEN);\n" "> +\tval |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |\n" - "> +\t???????BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;\n" + "> +\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;\n" "> +\taxi_dma_iowrite32(chan->chip, DMAC_CHEN, val);\n" "\n" "You have helpers which you don't use. Why?\n" @@ -345,7 +353,7 @@ "\n" "> +\tval = axi_dma_ioread32(chan->chip, DMAC_CHEN);\n" "> +\tval &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);\n" - "> +\tval |=??(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);\n" + "> +\tval |=\302\240\302\240(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);\n" "> +\taxi_dma_iowrite32(chan->chip, DMAC_CHEN, val);\n" "\n" "Use helper.\n" @@ -443,13 +451,13 @@ "> +\n" "> +\tret = devm_request_irq(chip->dev, chip->irq,\n" "> dw_axi_dma_intretupt,\n" - "> +\t\t\t???????IRQF_SHARED, DRV_NAME, chip);\n" + "> +\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240IRQF_SHARED, DRV_NAME, chip);\n" "> +\tif (ret)\n" "> +\t\treturn ret;\n" "> +\n" "> +\t/* Lli address must be aligned to a 64-byte boundary */\n" "> +\tdw->desc_pool = dmam_pool_create(DRV_NAME, chip->dev,\n" - "> +\t\t\t\t\t?sizeof(struct axi_dma_desc),\n" + "> +\t\t\t\t\t\302\240sizeof(struct axi_dma_desc),\n" "> 64, 0);\n" "> +\tif (!dw->desc_pool) {\n" "> +\t\tdev_err(chip->dev, \"No memory for descriptors dma\n" @@ -503,11 +511,11 @@ "> +\tpm_runtime_enable(chip->dev);\n" "> +\n" "> +\t/*\n" - "> +\t?* We can't just call pm_runtime_get here instead of\n" - "> +\t?* pm_runtime_get_noresume + axi_dma_runtime_resume because\n" + "> +\t\302\240* We can't just call pm_runtime_get here instead of\n" + "> +\t\302\240* pm_runtime_get_noresume + axi_dma_runtime_resume because\n" "> we need\n" - "> +\t?* driver to work also without Runtime PM.\n" - "> +\t?*/\n" + "> +\t\302\240* driver to work also without Runtime PM.\n" + "> +\t\302\240*/\n" "> +\tpm_runtime_get_noresume(chip->dev);\n" "> +\tret = axi_dma_runtime_resume(chip->dev);\n" "> +\tif (ret < 0)\n" @@ -523,7 +531,7 @@ "> +\n" "> +\tdev_info(chip->dev, \"DesignWare AXI DMA Controller, %d\n" "> channels\\n\",\n" - "> +\t\t?dw->hdata->nr_channels);\n" + "> +\t\t\302\240dw->hdata->nr_channels);\n" "> +\n" "> +\treturn 0;\n" "> +\n" @@ -838,7 +846,7 @@ "> +};\n" "\n" "-- \n" - "Andy Shevchenko <andriy.shevchenko at linux.intel.com>\n" + "Andy Shevchenko <andriy.shevchenko@linux.intel.com>\n" Intel Finland Oy -75ff9bb89965ee9fce5164880cba04c13f3670210bfcf6eb2092c4cb0de11b84 +33952dee6e69de571ca71297b862acf8c3cf53a8d4cbc690b1dbef56d715d2ac
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