diff for duplicates of <1492784977.16657.6.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index 886ca52..c5ce50a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,8 +2,8 @@ Hi Andy, thanks for respond. My comments are inlined below. -On Tue, 2017-04-18@15:31 +0300, Andy Shevchenko wrote: -> On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote: +On Tue, 2017-04-18 at 15:31 +0300, Andy Shevchenko wrote: +> On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote: > > This patch adds support for the DW AXI DMAC controller. > > > > DW AXI DMAC is a part of upcoming development board from Synopsys. @@ -41,7 +41,7 @@ Sure. > > +#include "dmaengine.h" > > +#include "virt-dma.h" -> > +#define AXI_DMA_BUSWIDTHS ??\ +> > +#define AXI_DMA_BUSWIDTHS \ > > + (DMA_SLAVE_BUSWIDTH_1_BYTE | \ > > + DMA_SLAVE_BUSWIDTH_2_BYTES | \ > > + DMA_SLAVE_BUSWIDTH_4_BYTES | \ @@ -118,7 +118,7 @@ But I can cut off this 'if' statment, if it is necessery. > > +} > > +static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, > > dma_addr_t src, -> > + ???dma_addr_t dst, size_t len) +> > + dma_addr_t dst, size_t len) > > +{ > > + u32 max_width = chan->chip->dw->hdata->m_data_width; > > + size_t sdl = (src | dst | len); @@ -158,7 +158,7 @@ mostly use array instead of list) > > +} > > +/* Called in chan locked context */ > > +static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, -> > + ??????struct axi_dma_desc *first) +> > + struct axi_dma_desc *first) > > +{ > > + u32 reg, irq_mask; > > + u8 lms = 0; @@ -213,11 +213,11 @@ Only for dma slave operations. > > +} > > +static struct dma_async_tx_descriptor * > > +dma_chan_prep_dma_sg(struct dma_chan *dchan, -> > + ?????struct scatterlist *dst_sg, unsigned int +> > + struct scatterlist *dst_sg, unsigned int > > dst_nents, -> > + ?????struct scatterlist *src_sg, unsigned int +> > + struct scatterlist *src_sg, unsigned int > > src_nents, -> > + ?????unsigned long flags) +> > + unsigned long flags) > > +{ > > + struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); > > + struct axi_dma_desc *first = NULL, *desc = NULL, *prev = @@ -255,7 +255,7 @@ Should I add something like "dma_sg_desc_invalid" function to dmaengine.h ? > > +static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, -> > + ???struct axi_dma_desc *desc_head) +> > + struct axi_dma_desc *desc_head) > > +{ > > + struct axi_dma_desc *desc; > > + @@ -302,7 +302,7 @@ overwritten by next transfer. > > + > > + val = axi_dma_ioread32(chan->chip, DMAC_CHEN); > > + val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | -> > + ???????BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; +> > + BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; > > + axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); > > You have helpers which you don't use. Why? @@ -339,7 +339,7 @@ Good idea. Will change to do {} while () here. > > + > > + val = axi_dma_ioread32(chan->chip, DMAC_CHEN); > > + val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); -> > + val |=??(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); +> > + val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); > > + axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); > > + > > + chan->is_paused = false; @@ -572,4 +572,4 @@ APB DMAC and AXI DMAC have completely different regmap. So there is no much sense to do that. -- -?Eugeniy Paltsev + Eugeniy Paltsev diff --git a/a/content_digest b/N1/content_digest index ad87eb9..55fb780 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,28 @@ "ref\01491573855-1039-1-git-send-email-Eugeniy.Paltsev@synopsys.com\0" "ref\01491573855-1039-3-git-send-email-Eugeniy.Paltsev@synopsys.com\0" "ref\01492518695.24567.56.camel@linux.intel.com\0" - "From\0Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev)\0" - "Subject\0[PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver\0" + "ref\01492518695.24567.56.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org\0" + "From\0Eugeniy Paltsev <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>\0" + "Subject\0Re: [PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver\0" "Date\0Fri, 21 Apr 2017 14:29:38 +0000\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>\0" + "Cc\0vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org <vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>" + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Alexey.Brodkin-HKixBCOQz3hWk0Htik3J/w@public.gmane.org <Alexey.Brodkin-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> + linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org <dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> + " dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>\0" "\00:1\0" "b\0" "Hi Andy,\n" "thanks for respond.\n" "My comments are inlined below.\n" "\n" - "On Tue, 2017-04-18@15:31 +0300, Andy Shevchenko wrote:\n" - "> On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote:\n" + "On Tue, 2017-04-18 at 15:31 +0300, Andy Shevchenko wrote:\n" + "> On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote:\n" "> > This patch adds support for the DW AXI DMAC controller.\n" "> >\n" "> > DW AXI DMAC is a part of upcoming development board from Synopsys.\n" @@ -50,7 +60,7 @@ "\n" "> > +#include \"dmaengine.h\"\n" "> > +#include \"virt-dma.h\"\n" - "> > +#define AXI_DMA_BUSWIDTHS\t\t??\\\n" + "> > +#define AXI_DMA_BUSWIDTHS\t\t\302\240\302\240\\\n" "> > +\t(DMA_SLAVE_BUSWIDTH_1_BYTE\t| \\\n" "> > +\tDMA_SLAVE_BUSWIDTH_2_BYTES\t| \\\n" "> > +\tDMA_SLAVE_BUSWIDTH_4_BYTES\t| \\\n" @@ -127,7 +137,7 @@ "> > +}\n" "> > +static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan,\n" "> > dma_addr_t src,\n" - "> > +\t\t\t\t???dma_addr_t dst, size_t len)\n" + "> > +\t\t\t\t\302\240\302\240\302\240dma_addr_t dst, size_t len)\n" "> > +{\n" "> > +\tu32 max_width = chan->chip->dw->hdata->m_data_width;\n" "> > +\tsize_t sdl = (src | dst | len);\n" @@ -167,7 +177,7 @@ "> > +}\n" "> > +/* Called in chan locked context */\n" "> > +static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,\n" - "> > +\t\t\t\t??????struct axi_dma_desc *first)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240struct axi_dma_desc *first)\n" "> > +{\n" "> > +\tu32 reg, irq_mask;\n" "> > +\tu8 lms = 0;\n" @@ -222,11 +232,11 @@ "> > +}\n" "> > +static struct dma_async_tx_descriptor *\n" "> > +dma_chan_prep_dma_sg(struct dma_chan *dchan,\n" - "> > +\t\t?????struct scatterlist *dst_sg, unsigned int\n" + "> > +\t\t\302\240\302\240\302\240\302\240\302\240struct scatterlist *dst_sg, unsigned int\n" "> > dst_nents,\n" - "> > +\t\t?????struct scatterlist *src_sg, unsigned int\n" + "> > +\t\t\302\240\302\240\302\240\302\240\302\240struct scatterlist *src_sg, unsigned int\n" "> > src_nents,\n" - "> > +\t\t?????unsigned long flags)\n" + "> > +\t\t\302\240\302\240\302\240\302\240\302\240unsigned long flags)\n" "> > +{\n" "> > +\tstruct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);\n" "> > +\tstruct axi_dma_desc *first = NULL, *desc = NULL, *prev =\n" @@ -264,7 +274,7 @@ "dmaengine.h ?\n" "\n" "> > +static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,\n" - "> > +\t\t\t\t???struct axi_dma_desc *desc_head)\n" + "> > +\t\t\t\t\302\240\302\240\302\240struct axi_dma_desc *desc_head)\n" "> > +{\n" "> > +\tstruct axi_dma_desc *desc;\n" "> > +\n" @@ -311,7 +321,7 @@ "> > +\n" "> > +\tval = axi_dma_ioread32(chan->chip, DMAC_CHEN);\n" "> > +\tval |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |\n" - "> > +\t???????BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;\n" + "> > +\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;\n" "> > +\taxi_dma_iowrite32(chan->chip, DMAC_CHEN, val);\n" ">\n" "> You have helpers which you don't use. Why?\n" @@ -348,7 +358,7 @@ "> > +\n" "> > +\tval = axi_dma_ioread32(chan->chip, DMAC_CHEN);\n" "> > +\tval &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);\n" - "> > +\tval |=??(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);\n" + "> > +\tval |=\302\240\302\240(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);\n" "> > +\taxi_dma_iowrite32(chan->chip, DMAC_CHEN, val);\n" "> > +\n" "> > +\tchan->is_paused = false;\n" @@ -581,6 +591,6 @@ "much sense to do that.\n" "\n" "--\n" - ?Eugeniy Paltsev + "\302\240Eugeniy Paltsev" -7b19815e7324c389b5f830058ca255dbfac6db2488b68d7cc1bc8a05ba1bf827 +614e66d9a393c7beb1011e011cc6abb3f1f257c040ad11cb656cfdadd70b6b04
diff --git a/a/1.txt b/N2/1.txt index 886ca52..c5ce50a 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -2,8 +2,8 @@ Hi Andy, thanks for respond. My comments are inlined below. -On Tue, 2017-04-18@15:31 +0300, Andy Shevchenko wrote: -> On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote: +On Tue, 2017-04-18 at 15:31 +0300, Andy Shevchenko wrote: +> On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote: > > This patch adds support for the DW AXI DMAC controller. > > > > DW AXI DMAC is a part of upcoming development board from Synopsys. @@ -41,7 +41,7 @@ Sure. > > +#include "dmaengine.h" > > +#include "virt-dma.h" -> > +#define AXI_DMA_BUSWIDTHS ??\ +> > +#define AXI_DMA_BUSWIDTHS \ > > + (DMA_SLAVE_BUSWIDTH_1_BYTE | \ > > + DMA_SLAVE_BUSWIDTH_2_BYTES | \ > > + DMA_SLAVE_BUSWIDTH_4_BYTES | \ @@ -118,7 +118,7 @@ But I can cut off this 'if' statment, if it is necessery. > > +} > > +static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, > > dma_addr_t src, -> > + ???dma_addr_t dst, size_t len) +> > + dma_addr_t dst, size_t len) > > +{ > > + u32 max_width = chan->chip->dw->hdata->m_data_width; > > + size_t sdl = (src | dst | len); @@ -158,7 +158,7 @@ mostly use array instead of list) > > +} > > +/* Called in chan locked context */ > > +static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, -> > + ??????struct axi_dma_desc *first) +> > + struct axi_dma_desc *first) > > +{ > > + u32 reg, irq_mask; > > + u8 lms = 0; @@ -213,11 +213,11 @@ Only for dma slave operations. > > +} > > +static struct dma_async_tx_descriptor * > > +dma_chan_prep_dma_sg(struct dma_chan *dchan, -> > + ?????struct scatterlist *dst_sg, unsigned int +> > + struct scatterlist *dst_sg, unsigned int > > dst_nents, -> > + ?????struct scatterlist *src_sg, unsigned int +> > + struct scatterlist *src_sg, unsigned int > > src_nents, -> > + ?????unsigned long flags) +> > + unsigned long flags) > > +{ > > + struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); > > + struct axi_dma_desc *first = NULL, *desc = NULL, *prev = @@ -255,7 +255,7 @@ Should I add something like "dma_sg_desc_invalid" function to dmaengine.h ? > > +static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, -> > + ???struct axi_dma_desc *desc_head) +> > + struct axi_dma_desc *desc_head) > > +{ > > + struct axi_dma_desc *desc; > > + @@ -302,7 +302,7 @@ overwritten by next transfer. > > + > > + val = axi_dma_ioread32(chan->chip, DMAC_CHEN); > > + val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | -> > + ???????BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; +> > + BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; > > + axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); > > You have helpers which you don't use. Why? @@ -339,7 +339,7 @@ Good idea. Will change to do {} while () here. > > + > > + val = axi_dma_ioread32(chan->chip, DMAC_CHEN); > > + val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); -> > + val |=??(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); +> > + val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); > > + axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); > > + > > + chan->is_paused = false; @@ -572,4 +572,4 @@ APB DMAC and AXI DMAC have completely different regmap. So there is no much sense to do that. -- -?Eugeniy Paltsev + Eugeniy Paltsev diff --git a/a/content_digest b/N2/content_digest index ad87eb9..a20269a 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,18 +1,27 @@ "ref\01491573855-1039-1-git-send-email-Eugeniy.Paltsev@synopsys.com\0" "ref\01491573855-1039-3-git-send-email-Eugeniy.Paltsev@synopsys.com\0" "ref\01492518695.24567.56.camel@linux.intel.com\0" - "From\0Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev)\0" - "Subject\0[PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver\0" + "From\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\0" + "Subject\0Re: [PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver\0" "Date\0Fri, 21 Apr 2017 14:29:38 +0000\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0andriy.shevchenko@linux.intel.com <andriy.shevchenko@linux.intel.com>\0" + "Cc\0vinod.koul@intel.com <vinod.koul@intel.com>" + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + robh+dt@kernel.org <robh+dt@kernel.org> + Alexey.Brodkin@synopsys.com <Alexey.Brodkin@synopsys.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + Eugeniy.Paltsev@synopsys.com <Eugeniy.Paltsev@synopsys.com> + linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org> + dan.j.williams@intel.com <dan.j.williams@intel.com> + " dmaengine@vger.kernel.org <dmaengine@vger.kernel.org>\0" "\00:1\0" "b\0" "Hi Andy,\n" "thanks for respond.\n" "My comments are inlined below.\n" "\n" - "On Tue, 2017-04-18@15:31 +0300, Andy Shevchenko wrote:\n" - "> On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote:\n" + "On Tue, 2017-04-18 at 15:31 +0300, Andy Shevchenko wrote:\n" + "> On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote:\n" "> > This patch adds support for the DW AXI DMAC controller.\n" "> >\n" "> > DW AXI DMAC is a part of upcoming development board from Synopsys.\n" @@ -50,7 +59,7 @@ "\n" "> > +#include \"dmaengine.h\"\n" "> > +#include \"virt-dma.h\"\n" - "> > +#define AXI_DMA_BUSWIDTHS\t\t??\\\n" + "> > +#define AXI_DMA_BUSWIDTHS\t\t\302\240\302\240\\\n" "> > +\t(DMA_SLAVE_BUSWIDTH_1_BYTE\t| \\\n" "> > +\tDMA_SLAVE_BUSWIDTH_2_BYTES\t| \\\n" "> > +\tDMA_SLAVE_BUSWIDTH_4_BYTES\t| \\\n" @@ -127,7 +136,7 @@ "> > +}\n" "> > +static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan,\n" "> > dma_addr_t src,\n" - "> > +\t\t\t\t???dma_addr_t dst, size_t len)\n" + "> > +\t\t\t\t\302\240\302\240\302\240dma_addr_t dst, size_t len)\n" "> > +{\n" "> > +\tu32 max_width = chan->chip->dw->hdata->m_data_width;\n" "> > +\tsize_t sdl = (src | dst | len);\n" @@ -167,7 +176,7 @@ "> > +}\n" "> > +/* Called in chan locked context */\n" "> > +static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,\n" - "> > +\t\t\t\t??????struct axi_dma_desc *first)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240struct axi_dma_desc *first)\n" "> > +{\n" "> > +\tu32 reg, irq_mask;\n" "> > +\tu8 lms = 0;\n" @@ -222,11 +231,11 @@ "> > +}\n" "> > +static struct dma_async_tx_descriptor *\n" "> > +dma_chan_prep_dma_sg(struct dma_chan *dchan,\n" - "> > +\t\t?????struct scatterlist *dst_sg, unsigned int\n" + "> > +\t\t\302\240\302\240\302\240\302\240\302\240struct scatterlist *dst_sg, unsigned int\n" "> > dst_nents,\n" - "> > +\t\t?????struct scatterlist *src_sg, unsigned int\n" + "> > +\t\t\302\240\302\240\302\240\302\240\302\240struct scatterlist *src_sg, unsigned int\n" "> > src_nents,\n" - "> > +\t\t?????unsigned long flags)\n" + "> > +\t\t\302\240\302\240\302\240\302\240\302\240unsigned long flags)\n" "> > +{\n" "> > +\tstruct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);\n" "> > +\tstruct axi_dma_desc *first = NULL, *desc = NULL, *prev =\n" @@ -264,7 +273,7 @@ "dmaengine.h ?\n" "\n" "> > +static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,\n" - "> > +\t\t\t\t???struct axi_dma_desc *desc_head)\n" + "> > +\t\t\t\t\302\240\302\240\302\240struct axi_dma_desc *desc_head)\n" "> > +{\n" "> > +\tstruct axi_dma_desc *desc;\n" "> > +\n" @@ -311,7 +320,7 @@ "> > +\n" "> > +\tval = axi_dma_ioread32(chan->chip, DMAC_CHEN);\n" "> > +\tval |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |\n" - "> > +\t???????BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;\n" + "> > +\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;\n" "> > +\taxi_dma_iowrite32(chan->chip, DMAC_CHEN, val);\n" ">\n" "> You have helpers which you don't use. Why?\n" @@ -348,7 +357,7 @@ "> > +\n" "> > +\tval = axi_dma_ioread32(chan->chip, DMAC_CHEN);\n" "> > +\tval &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);\n" - "> > +\tval |=??(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);\n" + "> > +\tval |=\302\240\302\240(BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);\n" "> > +\taxi_dma_iowrite32(chan->chip, DMAC_CHEN, val);\n" "> > +\n" "> > +\tchan->is_paused = false;\n" @@ -581,6 +590,6 @@ "much sense to do that.\n" "\n" "--\n" - ?Eugeniy Paltsev + "\302\240Eugeniy Paltsev" -7b19815e7324c389b5f830058ca255dbfac6db2488b68d7cc1bc8a05ba1bf827 +e0f069867f496d9b4d6a2dd565f4fa93a2b290f5fb86aa4684594c72ec7dc18a
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