From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev) Date: Mon, 24 Apr 2017 15:55:06 +0000 Subject: [PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver In-Reply-To: <1492787583.24567.120.camel@linux.intel.com> References: <1491573855-1039-1-git-send-email-Eugeniy.Paltsev@synopsys.com> <1491573855-1039-3-git-send-email-Eugeniy.Paltsev@synopsys.com> <1492518695.24567.56.camel@linux.intel.com> <1492784977.16657.6.camel@synopsys.com> <1492787583.24567.120.camel@linux.intel.com> List-ID: Message-ID: <1493049305.25985.4.camel@synopsys.com> To: linux-snps-arc@lists.infradead.org Hi, On Fri, 2017-04-21@18:13 +0300, Andy Shevchenko wrote: > On Fri, 2017-04-21@14:29 +0000, Eugeniy Paltsev wrote: > > On Tue, 2017-04-18@15:31 +0300, Andy Shevchenko wrote: > > > On Fri, 2017-04-07@17:04 +0300, Eugeniy Paltsev wrote: > > > > This patch adds support for the DW AXI DMAC controller. > > > > +#define AXI_DMA_BUSWIDTHS ??\ > > > > + (DMA_SLAVE_BUSWIDTH_1_BYTE | \ > > > > + DMA_SLAVE_BUSWIDTH_2_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_4_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_8_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_16_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_32_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_64_BYTES) > > > > +/* TODO: check: do we need to use BIT() macro here? */ > > > > > > Still TODO? I remember I answered to this on the first round. > > > > Yes, I remember it. > > I left this TODO as a reminder because src_addr_widths and > > dst_addr_widths are > > not used anywhere and they are set differently in different drivers > > (with or without BIT macro). > > Strange. AFAIK they are representing bits (which is not the best > idea) in the resulting u64 field. So, anything bigger than 63 doesn't >?make sense. They are u32 fields! From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeniy Paltsev Subject: Re: [PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver Date: Mon, 24 Apr 2017 15:55:06 +0000 Message-ID: <1493049305.25985.4.camel@synopsys.com> References: <1491573855-1039-1-git-send-email-Eugeniy.Paltsev@synopsys.com> <1491573855-1039-3-git-send-email-Eugeniy.Paltsev@synopsys.com> <1492518695.24567.56.camel@linux.intel.com> <1492784977.16657.6.camel@synopsys.com> <1492787583.24567.120.camel@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1492787583.24567.120.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Content-Language: en-US Content-ID: <6BC3FFA14AF9404ABEA95E7A878AF78F-z7JfP6tgrtVBCHUSTMH8dZqQE7yCjDx5@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: "andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org" Cc: "vinod.koul-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "Alexey.Brodkin-HKixBCOQz3hWk0Htik3J/w@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org" , "linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "dan.j.williams-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org" , "dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org SGksDQpPbiBGcmksIDIwMTctMDQtMjEgYXQgMTg6MTMgKzAzMDAsIEFuZHkgU2hldmNoZW5rbyB3 cm90ZToNCj4gT24gRnJpLCAyMDE3LTA0LTIxIGF0IDE0OjI5ICswMDAwLCBFdWdlbml5IFBhbHRz ZXYgd3JvdGU6DQo+ID4gT24gVHVlLCAyMDE3LTA0LTE4IGF0IDE1OjMxICswMzAwLCBBbmR5IFNo ZXZjaGVua28gd3JvdGU6DQo+ID4gPiBPbiBGcmksIDIwMTctMDQtMDcgYXQgMTc6MDQgKzAzMDAs IEV1Z2VuaXkgUGFsdHNldiB3cm90ZToNCj4gPiA+ID4gVGhpcyBwYXRjaCBhZGRzIHN1cHBvcnQg Zm9yIHRoZSBEVyBBWEkgRE1BQyBjb250cm9sbGVyLg0KPiA+ID4gPiArI2RlZmluZSBBWElfRE1B X0JVU1dJRFRIUwkJwqDCoFwNCj4gPiA+ID4gKwkoRE1BX1NMQVZFX0JVU1dJRFRIXzFfQllURQl8 IFwNCj4gPiA+ID4gKwlETUFfU0xBVkVfQlVTV0lEVEhfMl9CWVRFUwl8IFwNCj4gPiA+ID4gKwlE TUFfU0xBVkVfQlVTV0lEVEhfNF9CWVRFUwl8IFwNCj4gPiA+ID4gKwlETUFfU0xBVkVfQlVTV0lE VEhfOF9CWVRFUwl8IFwNCj4gPiA+ID4gKwlETUFfU0xBVkVfQlVTV0lEVEhfMTZfQllURVMJfCBc DQo+ID4gPiA+ICsJRE1BX1NMQVZFX0JVU1dJRFRIXzMyX0JZVEVTCXwgXA0KPiA+ID4gPiArCURN QV9TTEFWRV9CVVNXSURUSF82NF9CWVRFUykNCj4gPiA+ID4gKy8qIFRPRE86IGNoZWNrOiBkbyB3 ZSBuZWVkIHRvIHVzZSBCSVQoKSBtYWNybyBoZXJlPyAqLw0KPiA+ID4NCj4gPiA+IFN0aWxsIFRP RE8/IEkgcmVtZW1iZXIgSSBhbnN3ZXJlZCB0byB0aGlzIG9uIHRoZSBmaXJzdCByb3VuZC4NCj4g Pg0KPiA+IFllcywgSSByZW1lbWJlciBpdC4NCj4gPiBJIGxlZnQgdGhpcyBUT0RPIGFzIGEgcmVt aW5kZXIgYmVjYXVzZSBzcmNfYWRkcl93aWR0aHMgYW5kDQo+ID4gZHN0X2FkZHJfd2lkdGhzIGFy ZQ0KPiA+IG5vdCB1c2VkIGFueXdoZXJlIGFuZCB0aGV5IGFyZSBzZXQgZGlmZmVyZW50bHkgaW4g ZGlmZmVyZW50IGRyaXZlcnMNCj4gPiAod2l0aCBvciB3aXRob3V0IEJJVCBtYWNybykuDQo+DQo+ IFN0cmFuZ2UuIEFGQUlLIHRoZXkgYXJlIHJlcHJlc2VudGluZyBiaXRzICh3aGljaCBpcyBub3Qg dGhlIGJlc3QNCj4gaWRlYSkgaW4gdGhlIHJlc3VsdGluZyB1NjQgZmllbGQuIFNvLCBhbnl0aGlu ZyBiaWdnZXIgdGhhbiA2MyBkb2Vzbid0DQo+wqBtYWtlIHNlbnNlLg0KVGhleSBhcmUgdTMyIGZp ZWxkcyENCkZyb20gZG1hZW5naW5lLmggOg0Kc3RydWN0IGRtYV9kZXZpY2Ugew0KLi4uDQrCoMKg wqDCoHUzMiBzcmNfYWRkcl93aWR0aHM7DQrCoMKgwqDCoHUzMiBkc3RfYWRkcl93aWR0aHM7DQp9 Ow0KDQo+IEluIGRyaXZlcnMgd2hlcmUgdGhleSBhcmUgbm90IGJpdHMgcXVpdGUgbGlrZWx5IGEg YnVnIGlzIGhpZGRlbi4NCkZvciBleGFtcGxlIChmcm9tIHB4YV9kbWEuYyk6DQpjb25zdCBlbnVt IGRtYV9zbGF2ZV9idXN3aWR0aCB3aWR0aHMgPSBETUFfU0xBVkVfQlVTV0lEVEhfMV9CWVRFIHwN CkRNQV9TTEFWRV9CVVNXSURUSF8yX0JZVEVTIHwgRE1BX1NMQVZFX0JVU1dJRFRIXzRfQllURVM7 DQoNCkFuZCB0aGVyZSBhcmUgYSBsb3Qgb2YgZHJpdmVycywgd2hpY2ggZG9uJ3QgdXNlIEJJVCBm b3IgdGhpcyBmaWVsZHMuDQpzaC9zaGRtYWMuYw0Kc2gvcmNhci1kbWFjLmMNCnFjb20vYmFtX2Rt YS5jDQptbXBfcGRtYS5jDQpzdGVfZG1hNDAuYw0KQW5kIG1hbnkgb3RoZXJzLi4uDQoNCj4gPg0K PiA+ID4gPiArDQo+ID4gPiA+ICtzdGF0aWMgaW5saW5lIHZvaWQNCj4gPiA+ID4gK2F4aV9kbWFf aW93cml0ZTMyKHN0cnVjdCBheGlfZG1hX2NoaXAgKmNoaXAsIHUzMiByZWcsIHUzMiB2YWwpDQo+ ID4gPiA+ICt7DQo+ID4gPiA+ICsJaW93cml0ZTMyKHZhbCwgY2hpcC0+cmVncyArIHJlZyk7DQo+ ID4gPg0KPiA+ID4gQXJlIHlvdSBnb2luZyB0byB1c2UgSU8gcG9ydHMgZm9yIHRoaXMgSVA/IEkg ZG9uJ3QgdGhpbmsgc28uDQo+ID4gPiBXb3VsZG4ndCBiZSBiZXR0ZXIgdG8gY2FsbCByZWFkbCgp L3dyaXRlbCgpIGluc3RlYWQ/DQo+ID4NCj4gPiBBcyBJIHVuZGVyc3RhbmQsIGl0J3MgYmV0dGVy IHRvIHVzZSBpb3JlYWQvaW93cml0ZSBhcyBtb3JlDQo+ID4gdW5pdmVyc2FsDQo+ID4gSU8NCj4g PiBhY2Nlc3Mgd2F5LiBBbSBJIHdyb25nPw0KPg0KPiBBcyBJIHNhaWQgYWJvdmUgdGhlIGlvcmVh ZFgvaW93cml0ZVggbWFrZXMgb25seSBzZW5zZSB3aGVuIHlvdXIgSVANCj4gd291bGQgYmUgYWNj ZXNzZWQgdmlhIElPIHJlZ2lvbiBvciBNTUlPLiBJJ20gcHJldHR5IHN1cmUgSU8gaXMgbm90DQo+ IHRoZSBjYXNlIGF0IGFsbCBmb3IgdGhpcyBJUC4NCk1NSU8/IFRoaXMgSVAgd29ya3MgZXhhY3Rs eSB2aWEgbWVtb3J5LW1hcHBlZCBJL08uDQoNCj4gPiA+ID4gK3N0YXRpYyBpbmxpbmUgdm9pZCBh eGlfY2hhbl9pcnFfZGlzYWJsZShzdHJ1Y3QgYXhpX2RtYV9jaGFuDQo+ID4gPiA+ICpjaGFuLA0K PiA+ID4gPiB1MzIgaXJxX21hc2spDQo+ID4gPiA+ICt7DQo+ID4gPiA+ICsJdTMyIHZhbDsNCj4g PiA+ID4gKw0KPiA+ID4gPiArCWlmIChsaWtlbHkoaXJxX21hc2sgPT0gRFdBWElETUFDX0lSUV9B TEwpKSB7DQo+ID4gPiA+ICsJCWF4aV9jaGFuX2lvd3JpdGUzMihjaGFuLCBDSF9JTlRTVEFUVVNf RU5BLA0KPiA+ID4gPiBEV0FYSURNQUNfSVJRX05PTkUpOw0KPiA+ID4gPiArCX0gZWxzZSB7DQo+ ID4gPg0KPiA+ID4gSSBkb24ndCBzZWUgdGhlIGJlbmVmaXQuIChZZXMsIEkgc2VlIG9uZSByZWFk LWxlc3MgcGF0aCwgSSB0aGluaw0KPiA+ID4gaXQNCj4gPiA+IG1ha2VzIHBlcnBsZXhpdHkgZm9y IG5vdGhpbmcgaGVyZSkNCj4gPg0KPiA+IFRoaXMgZnVuY3Rpb24gaXMgY2FsbGVkIG1vc3RseSB3 aXRoIGlycV9tYXNrID0gRFdBWElETUFDX0lSUV9BTEwuDQo+ID4gQWN0dWFsbHkgaXQgaXMgY2Fs bGVkIG9ubHkgd2l0aCBpcnFfbWFzayA9IERXQVhJRE1BQ19JUlFfQUxMIHVudGlsDQo+ID4gSSBh ZGQgRE1BX1NMQVZFIHN1cHBvcnQuDQo+ID4gQnV0IEkgY2FuIGN1dCBvZmYgdGhpcyAnaWYnIHN0 YXRtZW50LCBpZiBpdCBpcyBuZWNlc3NlcnkuDQo+DQo+IEl0J3Mgbm90IG5lY2Vzc2FyeSwgYnV0 IGZyb20gbXkgcG9pbnQgb2YgdmlldyBpbmNyZWFzZXMgcmVhZGFiaWxpdHkNCj4gb2YgdGhlIGNv ZGUgYSBsb3QgZm9yIHRoZSBwcmljZSBvZiBhbiBhZGRpdGlvbmFsIHJlYWRsKCkuDQpPay4NCg0K PiA+DQo+ID4gPiA+ICsJCXZhbCA9IGF4aV9jaGFuX2lvcmVhZDMyKGNoYW4sDQo+ID4gPiA+IENI X0lOVFNUQVRVU19FTkEpOw0KPiA+ID4gPiArCQl2YWwgJj0gfmlycV9tYXNrOw0KPiA+ID4gPiAr CQlheGlfY2hhbl9pb3dyaXRlMzIoY2hhbiwgQ0hfSU5UU1RBVFVTX0VOQSwNCj4gPiA+ID4gdmFs KTsNCj4gPiA+ID4gKwl9DQo+ID4gPiA+ICsNCj4gPiA+ID4gKwlyZXR1cm4gbWluX3Qoc2l6ZV90 LCBfX2ZmcyhzZGwpLCBtYXhfd2lkdGgpOw0KPiA+ID4gPiArfQ0KPiA+ID4gPiArc3RhdGljIHZv aWQgYXhpX2Rlc2NfcHV0KHN0cnVjdCBheGlfZG1hX2Rlc2MgKmRlc2MpDQo+ID4gPiA+ICt7DQo+ ID4gPiA+ICsJc3RydWN0IGF4aV9kbWFfY2hhbiAqY2hhbiA9IGRlc2MtPmNoYW47DQo+ID4gPiA+ ICsJc3RydWN0IGR3X2F4aV9kbWEgKmR3ID0gY2hhbi0+Y2hpcC0+ZHc7DQo+ID4gPiA+ICsJc3Ry dWN0IGF4aV9kbWFfZGVzYyAqY2hpbGQsICpfbmV4dDsNCj4gPiA+ID4gKwl1bnNpZ25lZCBpbnQg ZGVzY3NfcHV0ID0gMDsNCj4gPiA+ID4gKwlsaXN0X2Zvcl9lYWNoX2VudHJ5X3NhZmUoY2hpbGQs IF9uZXh0LCAmZGVzYy0NCj4gPiA+ID4gPnhmZXJfbGlzdCwNCj4gPiA+ID4geGZlcl9saXN0KSB7 DQo+ID4gPg0KPiA+ID4geGZlcl9saXN0IGxvb2tzIHJlZHVuZGFudC4NCj4gPiA+IENhbiB5b3Ug ZWxhYm9yYXRlIHdoeSB2aXJ0dWFsIGNoYW5uZWwgbWFuYWdlbWVudCBpcyBub3Qgd29ya2luZw0K PiA+ID4gZm9yDQo+ID4gPiB5b3U/DQo+ID4NCj4gPiBFYWNoIHZpcnR1YWwgZGVzY3JpcHRvciBl bmNhcHN1bGF0ZXMgc2V2ZXJhbCBoYXJkd2FyZSBkZXNjcmlwdG9ycywNCj4gPiB3aGljaCBiZWxv bmcgdG8gc2FtZSB0cmFuc2Zlci4NCj4gPiBUaGlzIGxpc3QgKHhmZXJfbGlzdCkgaXMgdXNlZCBv bmx5IGZvciBhbGxvY2F0aW5nL2ZyZWVpbmcgdGhlc2UNCj4gPiBkZXNjcmlwdG9ycyBhbmQgaXQg ZG9lc24ndCBhZmZlY3Qgb24gdmlydHVhbCBkbWEgd29yayBsb2dpYy4NCj4gPiBJIGNhbiBzZWUg dGhpcyBhcHByb2FjaCBpbiBzZXZlcmFsIGRyaXZlcnMgd2l0aCBWaXJ0RE1BIChidXQgdGhleQ0K PiA+IG1vc3RseSB1c2UgYXJyYXkgaW5zdGVhZCBvZiBsaXN0KQ0KPg0KPiBZb3UgZGVzY3JpYmVk IGhvdyBtb3N0IG9mIHRoZSBETUEgZHJpdmVycyBhcmUgaW1wbGVtZW50ZWQsIHRob3VnaA0KPiB0 aGV5DQo+IGFyZSB1c2luZyBqdXN0IHNnX2xpc3QgZGlyZWN0bHkuIEkgd291bGQgcmVjb21tZW5k IHRvIGRvIHRoZSBzYW1lIGFuZA0KPiBnZXQgcmlkIG9mIHRoaXMgbGlzdC4NClRoaXMgSVAgY2Fu IGJlIChhbnMgaXMpIGNvbmZpZ3VyZWQgd2l0aCBzbWFsbCBibG9jayBzaXplLg0KKG5vdGUsIHRo YXQgSSBhbSBub3Qgc2F5aW5nIGFib3V0IHJ1bnRpbWUgSFcgY29uZmlndXJhdGlvbikNCg0KQW5k IHRoZXJlIGlzIG9wcG9ydHVuaXR5IHdoYXQgd2UgY2FuJ3QgdXNlIHNnX2xpc3QgZGlyZWN0bHkg YW5kIG5lZWQgdG8NCnNwbGl0IHNnX2xpc3QgdG8gYSBzbWFsbGVyIGNodW5rcy4NCg0KPiA+ID4g QnR3LCBhcmUgeW91IHBsYW5uaW5nIHRvIHVzZSBwcmlvcml0eSBhdCBhbGw/IEZvciBub3cgb24g SSBkaWRuJ3QNCj4gPiA+IHNlZQ0KPiA+ID4gYSBzaW5nbGUgZHJpdmVyIChmcm9tIHRoZSBzZXQg SSBoYXZlIGNoZWNrZWQsIGxpa2UgNC01IG9mIHRoZW0pDQo+ID4gPiB0aGF0DQo+ID4gPiB1c2Vz IHByaW9yaXR5IGFueWhvdy4gSXQgbWFrZXMgZHJpdmVyIG1vcmUgY29tcGxleCBmb3Igbm90aGlu Zy4NCj4gPg0KPiA+IE9ubHkgZm9yIGRtYSBzbGF2ZSBvcGVyYXRpb25zLg0KPg0KPiBTbywgaW4g b3RoZXIgd29yZHMgeW91ICpoYXZlKiBhbiBhY3R1YWwgdHdvIG9yIG1vcmUgdXNlcnMgdGhhdCAq bmVlZCoNCj4gcHJpb3JpdGl6YXRpb24/DQpBcyBJIHJlbWVtYmVyIHRoZXJlIHdhcyBhbiBpZGVh IHRvIGdpdmUgaGlnaGVyIHByaW9yaXR5IHRvIGF1ZGlvIGRtYQ0KY2hhbmVscy4NCg0KPiA+ID4g PiArCWlmICh1bmxpa2VseShkc3RfbmVudHMgPT0gMCB8fCBzcmNfbmVudHMgPT0gMCkpDQo+ID4g PiA+ICsJCXJldHVybiBOVUxMOw0KPiA+ID4gPiArDQo+ID4gPiA+ICsJaWYgKHVubGlrZWx5KGRz dF9zZyA9PSBOVUxMIHx8IHNyY19zZyA9PSBOVUxMKSkNCj4gPiA+ID4gKwkJcmV0dXJuIE5VTEw7 DQo+ID4gPg0KPiA+ID4gSWYgd2UgbmVlZCB0aG9zZSBjaGVja3MgdGhleSBzaG91bGQgZ28gdG8N Cj4gPiA+IGRtYWVuZ2luZS5oL2RtYWVuZ2luZS5jLg0KPiA+DQo+ID4gSSBjaGVja2VkIHNldmVy YWwgZHJpdmVycywgd2hpY2ggaW1wbGVtZW50cyBkZXZpY2VfcHJlcF9kbWFfc2cgYW5kDQo+ID4g dGhleQ0KPiA+IGltcGxlbWVudHMgdGhpcyBjaGVja2Vycy4NCj4gPiBTaG91bGQgSSBhZGQgc29t ZXRoaW5nIGxpa2UgImRtYV9zZ19kZXNjX2ludmFsaWQiIGZ1bmN0aW9uIHRvDQo+ID4gZG1hZW5n aW5lLmggPw0KPg0KPiBJIHN1cHBvc2UgaXQncyBiZXR0ZXIgdG8gaW1wbGVtZW50IHRoZW0gaW4g dGhlIGNvcnJlc3BvbmRpbmcgaGVscGVycw0KPiBpbiBkbWFlbmdpbmUuaC4NCk9rLg0KDQo+ID4g PiA+ICtzdGF0aWMgdm9pZCBheGlfY2hhbl9saXN0X2R1bXBfbGxpKHN0cnVjdCBheGlfZG1hX2No YW4gKmNoYW4sDQo+ID4gPiA+ICsJCQkJwqDCoMKgc3RydWN0IGF4aV9kbWFfZGVzYw0KPiA+ID4g PiAqZGVzY19oZWFkKQ0KPiA+ID4gPiArew0KPiA+ID4gPiArCXN0cnVjdCBheGlfZG1hX2Rlc2Mg KmRlc2M7DQo+ID4gPiA+ICsNCj4gPiA+ID4gKwlheGlfY2hhbl9kdW1wX2xsaShjaGFuLCBkZXNj X2hlYWQpOw0KPiA+ID4gPiArCWxpc3RfZm9yX2VhY2hfZW50cnkoZGVzYywgJmRlc2NfaGVhZC0+ eGZlcl9saXN0LA0KPiA+ID4gPiB4ZmVyX2xpc3QpDQo+ID4gPiA+ICsJCWF4aV9jaGFuX2R1bXBf bGxpKGNoYW4sIGRlc2MpOw0KPiA+ID4gPiArfQ0KPiA+ID4gPiArDQo+ID4gPiA+ICtzdGF0aWMg dm9pZCBheGlfY2hhbl9oYW5kbGVfZXJyKHN0cnVjdCBheGlfZG1hX2NoYW4gKmNoYW4sIHUzMg0K PiA+ID4gPiBzdGF0dXMpDQo+ID4gPiA+ICt7DQo+ID4gPiA+ICsJLyogV0FSTiBhYm91dCBiYWQg ZGVzY3JpcHRvciAqLw0KPiA+ID4gPg0KPiA+ID4gPiArCWRldl9lcnIoY2hhbjJkZXYoY2hhbiks DQo+ID4gPiA+ICsJCSJCYWQgZGVzY3JpcHRvciBzdWJtaXR0ZWQgZm9yICVzLCBjb29raWU6ICVk LA0KPiA+ID4gPiBpcnE6DQo+ID4gPiA+IDB4JTA4eFxuIiwNCj4gPiA+ID4gKwkJYXhpX2NoYW5f bmFtZShjaGFuKSwgdmQtPnR4LmNvb2tpZSwgc3RhdHVzKTsNCj4gPiA+ID4gKwlheGlfY2hhbl9s aXN0X2R1bXBfbGxpKGNoYW4sIHZkX3RvX2F4aV9kZXNjKHZkKSk7DQo+ID4gPg0KPiA+ID4gQXMg SSBzYWlkIGVhcmxpZXIgZHdfZG1hYyBpcyAqYmFkKiBleGFtcGxlIG9mIHRoZSAodmlydHVhbA0K PiA+ID4gY2hhbm5lbA0KPiA+ID4gYmFzZWQpIERNQSBkcml2ZXIuDQo+ID4gPg0KPiA+ID4gSSBn dWVzcyB5b3UgbWF5IGp1c3QgZmFpbCB0aGUgZGVzY3JpcHRvciBhbmQgZG9uJ3QgcHJldGVuZCBp dCBoYXMNCj4gPiA+IGJlZW4gcHJvY2Vzc2VkIHN1Y2Nlc3NmdWxseS4NCj4gPg0KPiA+IFdoYXQg ZG8geW91IG1lYW4gYnkgc2F5aW5nICJmYWlsIHRoZSBkZXNjcmlwdG9yIj8NCj4gPiBBZnRlciBJ IGdldCBlcnJvciBJIGNhbmNlbCBjdXJyZW50IHRyYW5zZmVyIGFuZCBmcmVlIGFsbA0KPiA+IGRl c2NyaXB0b3JzDQo+ID4gZnJvbSBpdCAoYnkgY2FsbGluZyB2Y2hhbl9jb29raWVfY29tcGxldGUp Lg0KPiA+IEkgY2FuJ3Qgc3RvcmUgZXJyb3Igc3RhdHVzIGluIGRlc2NyaXB0b3Igc3RydWN0dXJl IGJlY2F1c2UgaXQgd2lsbA0KPiA+IGJlDQo+ID4gZnJlZWQgYnkgdmNoYW5fY29va2llX2NvbXBs ZXRlLg0KPiA+IEkgY2FuJ3Qgc3RvcmUgZXJyb3Igc3RhdHVzIGluIGNoYW5uZWwgc3RydWN0dXJl IGJlY2F1c2UgaXQgd2lsbCBiZQ0KPiA+IG92ZXJ3cml0dGVuIGJ5IG5leHQgdHJhbnNmZXIuDQo+ DQo+IEJldHRlciBub3QgdG8gcHJldGVuZCB0aGF0IGl0IGhhcyBiZWVuIHByb2Nlc3NlZCBzdWNj ZXNzZnVsbHkuIERvbid0DQo+IGNhbGwgY2FsbGJhY2sgb24gaXQgYW5kIHNldCBpdHMgc3RhdHVz IHRvIERNQV9FUlJPUiAodGhhdCdzIHdoeQ0KPiBkZXNjcmlwdG9ycyBpbiBtYW55IGRyaXZlcnMg aGF2ZSBkbWFfc3RhdHVzIGZpZWxkKS4gV2hlbiB1c2VyIGFza3MNCj4gZm9yDQo+IHN0YXR1cyAo dXNpbmcgY29va2llKSB0aGUgc2F2ZWQgdmFsdWUgd291bGQgYmUgcmV0dXJuZWQgdW50aWwNCj4g ZGVzY3JpcHRvcg0KPiBpcyBhY3RpdmUuDQo+DQo+IERvIHlvdSBoYXZlIHNvbWUgb3RoZXIgd29y a2Zsb3cgaW4gbWluZD8NCg0KSG1tLi4uDQpEbyB5b3UgbWVhbiBJIHNob3VsZCBsZWZ0IGVycm9y IGRlc2NyaXB0b3JzIGluIGRlc2NfaXNzdWVkIGxpc3QNCm9yIEkgc2hvdWxkIGNyZWF0ZSBhbm90 aGVyIGxpc3QgKGxpa2UgZGVzY19lcnJvcikgaW4gbXkgZHJpdmVyIGFuZCBtb3ZlDQplcnJvciBk ZXNjcmlwdG9ycyB0byBkZXNjX2Vycm9yIGxpc3Q/DQoNCkFuZCB3aGVuIGV4YWN0bHkgc2hvdWxk IEkgZnJlZSBlcnJvciBkZXNjcmlwdG9ycz8NCg0KSSBjaGVja2VkIGhzdS9oc3UuYyBkbWEgZHJp dmVyIGltcGxlbWVudGF0aW9uOg0KwqAgdmRtYSBkZXNjcmlwdG9yIGlzIGRlbGV0ZWQgZnJvbSBk ZXNjX2lzc3VlZCBsaXN0IHdoZW4gdHJhbnNmZXINCsKgIHN0YXJ0cy4gV2hlbiBkZXNjcmlwdG9y IG1hcmtlZCBhcyBlcnJvciBkZXNjcmlwdG9yDQrCoCB2Y2hhbl9jb29raWVfY29tcGxldGUgaXNu J3QgY2FsbGVkIGZvciB0aGlzIGRlc2NyaXB0b3IuIEFuZCB0aGlzDQrCoCBkZXNjcmlwdG9yIGlz bid0IHBsYWNlZCBpbiBhbnkgbGlzdC4gU28gZXJyb3IgZGVzY3JpcHRvcnMgKm5ldmVyKg0KwqAg d2lsbCBiZSBmcmVlZC4NCsKgIEkgZG9uJ3QgYWN0dWFsbHkgbGlrZSB0aGlzIGFwcHJvYWNoLg0K DQo+ID4gPiA+ICsNCj4gPiA+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZGV2X3BtX29wcyBkd19h eGlfZG1hX3BtX29wcyA9IHsNCj4gPiA+ID4gKwlTRVRfUlVOVElNRV9QTV9PUFMoYXhpX2RtYV9y dW50aW1lX3N1c3BlbmQsDQo+ID4gPiA+IGF4aV9kbWFfcnVudGltZV9yZXN1bWUsIE5VTEwpDQo+ ID4gPiA+ICt9Ow0KPiA+ID4NCj4gPiA+IEhhdmUgeW91IHRyaWVkIHRvIGJ1aWxkIHdpdGggQ09O RklHX1BNIGRpc2FibGVkPw0KPiA+DQo+ID4gWWVzLg0KPiA+DQo+ID4gPiBJJ20gcHJldHR5IHN1 cmUgeW91IG5lZWQgX19tYXliZV91bnVzZWQgYXBwbGllZCB0byB5b3VyIFBNIG9wcy4NCj4gPg0K PiA+IEkgY2FsbCBheGlfZG1hX3J1bnRpbWVfc3VzcGVuZCAvIGF4aV9kbWFfcnVudGltZV9yZXN1 bWUgZXZlbiBJDQo+ID4gZG9udCd0DQo+ID4gdXNlIFBNLg0KPiA+IChJIGNhbGwgdGhlbSBpbiBw cm9iZSAvIHJlbW92ZSBmdW5jdGlvbi4pDQo+DQo+IEhtbS4uLiBJIGRpZG4ndCBjaGVjayB5b3Vy IC0+cHJvYmUoKSBhbmQgLT5yZW1vdmUoKS4gRG8geW91IG1lYW4geW91DQo+IGNhbGwgdGhlbSBl eHBsaWNpdGx5IGJ5IHRob3NlIG5hbWVzPw0KPg0KPiBJZiBzbywgcGxlYXNlIGRvbid0IGRvIHRo YXQuIFVzZSBwbV9ydW50aW1lXyooKSBpbnN0ZWFkLiBBbmQuLi4NCj4NCj4gPiBTbyBJIGRvbid0 IG5lZWQgdG8gZGVjbGFyZSB0aGVtIHdpdGggX19tYXliZV91bnVzZWQuDQo+DQo+IC4uLmluIHRo YXQgY2FzZSBpdCdzIHBvc3NpYmxlIHlvdSBoYXZlIHRoZW0gZGVmaW5lZCBidXQgbm90IHVzZWQu DQo+DQpGcm9tIG15IC0+cHJvYmUoKSBmdW5jdGlvbjoNCg0KcG1fcnVudGltZV9nZXRfbm9yZXN1 bWUoY2hpcC0+ZGV2KTsNCnJldCA9IGF4aV9kbWFfcnVudGltZV9yZXN1bWUoY2hpcC0+ZGV2KTsN Cg0KRmlyc3RseSBJIG9ubHkgaW5jcmVtZW10IGNvdW50ZXIuDQpTZWNvbmRseSBleHBsaWNpdGx5 IGNhbGwgbXkgcmVzdW1lIGZ1bmN0aW9uLg0KDQpJIGNhbGwgdGhlbSBleHBsaWNpdGx5IGJlY2F1 c2UgSSBuZWVkIGRyaXZlciB0byB3b3JrIGFsc28gd2l0aG91dA0KUnVudGltZSBQTS4gU28gSSBj YW4ndCBqdXN0IGNhbGwgcG1fcnVudGltZV9nZXQgaGVyZSBpbnN0ZWFkIG9mDQpwbV9ydW50aW1l X2dldF9ub3Jlc3VtZSArIGF4aV9kbWFfcnVudGltZV9yZXN1bWUuDQoNCk9mIGNvdXJzZSBJIGNh biBjb3B5ICphbGwqIGNvZGUgZnJvbSBheGlfZG1hX3J1bnRpbWVfcmVzdW1lDQp0byAtPnByb2Jl KCkgZnVuY3Rpb24sIGJ1dCBJIGRvbid0IHJlYWxseSBsaWtlIHRoaXMgaWRlYS4NCg0KPiA+ID4g PiArc3RydWN0IGF4aV9kbWFfY2hhbiB7DQo+ID4gPiA+ICsJc3RydWN0IGF4aV9kbWFfY2hpcAkJ KmNoaXA7DQo+ID4gPiA+ICsJdm9pZCBfX2lvbWVtCQkJKmNoYW5fcmVnczsNCj4gPiA+ID4gKwl1 OAkJCQlpZDsNCj4gPiA+ID4gKwlhdG9taWNfdAkJCWRlc2NzX2FsbG9jYXRlZDsNCj4gPiA+ID4g Kw0KPiA+ID4gPiArCXN0cnVjdCB2aXJ0X2RtYV9jaGFuCQl2YzsNCj4gPiA+ID4gKw0KPiA+ID4g PiArCS8qIHRoZXNlIG90aGVyIGVsZW1lbnRzIGFyZSBhbGwgcHJvdGVjdGVkIGJ5IHZjLmxvY2sN Cj4gPiA+ID4gKi8NCj4gPiA+ID4gKwlib29sCQkJCWlzX3BhdXNlZDsNCj4gPiA+DQo+ID4gPiBJ IHN0aWxsIGRpZG4ndCBnZXQgKGFscmVhZHkgZm9yZ290KSB3aHkgeW91IGNhbid0IHVzZSBkbWFf c3RhdHVzDQo+ID4gPiBpbnN0ZWFkIGZvciB0aGUgYWN0aXZlIGRlc2NyaXB0b3I/DQo+ID4NCj4g PiBBcyBJIHNhaWQgYmVmb3JlLCBJIGNoZWNrZWQgc2V2ZXJhbCBkcml2ZXIsIHdoaWNoIGhhdmUg c3RhdHVzDQo+ID4gdmFyaWFibGUNCj4gPiBpbiB0aGVpciBjaGFubmVsIHN0cnVjdHVyZSAtIGl0 IGlzIHVzZWQgKm9ubHkqIGZvciBkZXRlcm1pbmF0aW5nIGlzDQo+ID4gY2hhbm5lbCBwYXVzZWQg b3Igbm90LiBTbyB0aGVyZSBpcyBubyBtdWNoIHNlbnNlIGluIHJlcGxhY2luZw0KPiA+ICJpc19w YXVzZWQiIHRvICJzdGF0dXMiIGFuZCBJIGxlZnQgImlzX3BhdXNlZCIgdmFyaWFibGUgdW50b3Vj aGVkLg0KPg0KPiBOb3Qgb25seSAoc2VlIGFib3ZlKSwgdGhlIGVycm9yZWQgZGVzY3JpcHRvciBr ZWVwcyB0aGF0IHN0YXR1cy4NCj4NCj4gPiAoSSBkZXNjcmliZWQgYWJvdmUgd2h5IHdlIGNhbid0 IHVzZSBzdGF0dXMgaW4gY2hhbm5lbCBzdHJ1Y3R1cmUgZm9yDQo+ID4gZXJyb3IgaGFuZGxpbmcp DQo+DQo+IEFoLCBJJ20gdGFsa2luZyBhYm91dCBkZXNjcmlwdG9yLg0KDQpBZ2FpbiAtIFBBVVNF RCBpcyBwZXItY2hhbm5lbCBmbGFnLiBTbywgZXZlbiBpZiB3ZSBoYXZlIHN0YXR1cyBmaWVsZCBp bg0KZWFjaCBkZXNjcmlwdG9yLCBpdCBpcyBzaW1wbGVyIHRvIHVzZSBvbmUgcGVyLWNoYW5uZWwg ZmxhZyBpbnN0ZWFkIG9mDQpwbGVudHkgcGVyLWRlc2NyaXB0b3IgZmxhZ3MuDQpXaGVuIHdlIHBh dXNpbmcvcmVzdW1pbmcgZG1hIGNoYW5uZWwgaXQgaXMgc2ltcGxlciB0byBzZXQgb25seSBvbmUg ZmxhZw0KaW5zdGVhZCBvZiB3cml0aW5nIERNQV9QQVVTRUQgdG8gKmVhY2gqIGRlc2NyaXB0b3Ig c3RhdHVzIGZpZWxkLg0KDQo+ID4gPiA+IFN0YXR1cyBGZXRjaCBBZGRyICovDQo+ID4gPiA+ICsj ZGVmaW5lIENIX0lOVFNUQVRVU19FTkEJMHgwODAgLyogUi9XIENoYW4gSW50ZXJydXB0DQo+ID4g PiA+IFN0YXR1cw0KPiA+ID4gPiBFbmFibGUgKi8NCj4gPiA+ID4gKyNkZWZpbmUgQ0hfSU5UU1RB VFVTCQkweDA4OCAvKiBSL1cgQ2hhbg0KPiA+ID4gPiBJbnRlcnJ1cHQNCj4gPiA+ID4gU3RhdHVz ICovDQo+ID4gPiA+ICsjZGVmaW5lIENIX0lOVFNJR05BTF9FTkEJMHgwOTAgLyogUi9XIENoYW4g SW50ZXJydXB0DQo+ID4gPiA+IFNpZ25hbA0KPiA+ID4gPiBFbmFibGUgKi8NCj4gPiA+ID4gKyNk ZWZpbmUgQ0hfSU5UQ0xFQVIJCTB4MDk4IC8qIFcgQ2hhbiBJbnRlcnJ1cHQNCj4gPiA+ID4gQ2xl YXINCj4gPiA+ID4gKi8NCj4gPiA+DQo+ID4gPiBJJ20gd29uZGVyaW5nIGlmIHlvdSBjYW4gdXNl IHJlZ21hcCBBUEkgaW5zdGVhZC4NCj4gPg0KPiA+IElzIGl0IHJlYWxseSBuZWNlc3Nhcnk/IEl0 J2xsIG1ha2UgZHJpdmVyIG1vcmUgY29tcGxleCBmb3Igbm90aGluZy4NCj4NCj4gVGhhdCdzIHdo eSBJJ20gbm90IHN1Z2dlc3RpbmcgYnV0IHdvbmRlcmluZy4NCj4gPg0KPiA+ID4gPiArfTsNCj4g PiA+DQo+ID4gPiBIbW0uLi4gZG8geW91IG5lZWQgdGhlbSBpbiB0aGUgaGVhZGVyPw0KPiA+DQo+ ID4gSSB1c2Ugc29tZSBvZiB0aGVzZSBkZWZpbml0aW9ucyBpbiBteSBjb2RlIHNvIEkgZ3Vlc3Mg eWVzLg0KPiA+IC8qIE1heWJlIEkgbWlzdW5kZXJzdG9vZCB5b3VyIHF1ZXN0aW9uLi4uICovDQo+ DQo+IEkgbWVhbiwgd2hvIGFyZSB0aGUgdXNlcnMgb2YgdGhlbT8gSWYgaXQncyBvbmx5IG9uZSBt b2R1bGUsIHRoZXJlIGlzDQo+IG5vIG5lZWQgdG8gcHV0IHRoZW0gaW4gaGVhZGVyLg0KWWVzLCBv bmx5IG9uZSBtb2R1bGUuDQpTaG91bGQgSSBtb3ZlIGFsbCB0aGlzIGRlZmluaXRpb25zIHRvIGF4 aV9kbWFfcGxhdGZvcm0uYyBmaWxlIGFuZCByaWQNCm9mIGJvdGggYXhpX2RtYV9wbGF0Zm9ybV9y ZWcuaCBhbmQgYXhpX2RtYV9wbGF0Zm9ybS5oIGhlYWRlcnM/DQoNCj4gPg0KPiA+ID4gPiArI2Rl ZmluZSBDSF9DRkdfSF9UVF9GQ19QT1MJMA0KPiA+ID4gPiArZW51bSB7DQo+ID4gPiA+ICsJRFdB WElETUFDX1RUX0ZDX01FTV9UT19NRU1fRE1BQwk9IDB4MCwNCj4gPiA+ID4gKwlEV0FYSURNQUNf VFRfRkNfTUVNX1RPX1BFUl9ETUFDLA0KPiA+ID4gPiArCURXQVhJRE1BQ19UVF9GQ19QRVJfVE9f TUVNX0RNQUMsDQo+ID4gPiA+ICsJRFdBWElETUFDX1RUX0ZDX1BFUl9UT19QRVJfRE1BQywNCj4g PiA+ID4gKwlEV0FYSURNQUNfVFRfRkNfUEVSX1RPX01FTV9TUkMsDQo+ID4gPiA+ICsJRFdBWElE TUFDX1RUX0ZDX1BFUl9UT19QRVJfU1JDLA0KPiA+ID4gPiArCURXQVhJRE1BQ19UVF9GQ19NRU1f VE9fUEVSX0RTVCwNCj4gPiA+ID4gKwlEV0FYSURNQUNfVFRfRkNfUEVSX1RPX1BFUl9EU1QNCj4g PiA+ID4gK307DQo+ID4gPg0KPiA+ID4gU29tZSBvZiBkZWZpbml0aW9ucyBhcmUgdGhlIHNhbWUg YXMgZm9yIGR3X2RtYWMsIHJpZ2h0PyBXZSBtaWdodA0KPiA+ID4gc3BsaXQgdGhlbSB0byBhIGNv bW1vbiBoZWFkZXIsIHRob3VnaCBJIGhhdmUgbm8gc3Ryb25nIG9waW5pb24NCj4gPiA+IGFib3V0 DQo+ID4NCj4gPiBpdC4NCj4gPiA+IFZpbm9kPw0KPiA+DQo+ID4gQVBCIERNQUMgYW5kIEFYSSBE TUFDIGhhdmUgY29tcGxldGVseSBkaWZmZXJlbnQgcmVnbWFwLiBTbyB0aGVyZSBpcw0KPiA+IG5v DQo+ID4gbXVjaCBzZW5zZSB0byBkbyB0aGF0Lg0KPg0KPiBJJ20gbm90IHRhbGtpbmcgYWJvdXQg cmVnaXN0ZXJzLCBJJ20gdGFsa2luZyBhYm91dCBkZWZpbml0aW9ucyBsaWtlDQo+IGFib3ZlLiBU aG91Z2ggaXQgd291bGQgYmUgaW5kZWVkIGxpdHRsZSBzZW5zZSB0byBzcGxpdCBzb21lIGNvbW1v bg0KPiBjb2RlIGJldHdlZW4gdGhvc2UgdHdvLg0KVGhpcyBkZWZpbml0aW9ucyBhcmUgdGhlIGZp ZWxkcyBvZiBzb21lIHJlZ2lzdGVycy4gU28gdGhleSBhcmUgYWxzbw0KZGlmZmVyZW50Lg0KDQot LQ0KwqBFdWdlbml5IFBhbHRzZXY= -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S972426AbdDXPz7 (ORCPT ); Mon, 24 Apr 2017 11:55:59 -0400 Received: from smtprelay4.synopsys.com ([198.182.47.9]:54405 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S972391AbdDXPzV (ORCPT ); Mon, 24 Apr 2017 11:55:21 -0400 From: Eugeniy Paltsev To: "andriy.shevchenko@linux.intel.com" CC: "vinod.koul@intel.com" , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "Alexey.Brodkin@synopsys.com" , "devicetree@vger.kernel.org" , "Eugeniy.Paltsev@synopsys.com" , "linux-snps-arc@lists.infradead.org" , "dan.j.williams@intel.com" , "dmaengine@vger.kernel.org" Subject: Re: [PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver Thread-Topic: [PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver Thread-Index: AQHSr6fifaPEtWYJzkyOcLiQLbUIqKHK/piAgATX+YCAAAwigIAEwr2A Date: Mon, 24 Apr 2017 15:55:06 +0000 Message-ID: <1493049305.25985.4.camel@synopsys.com> References: <1491573855-1039-1-git-send-email-Eugeniy.Paltsev@synopsys.com> <1491573855-1039-3-git-send-email-Eugeniy.Paltsev@synopsys.com> <1492518695.24567.56.camel@linux.intel.com> <1492784977.16657.6.camel@synopsys.com> <1492787583.24567.120.camel@linux.intel.com> In-Reply-To: <1492787583.24567.120.camel@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.121.8.113] Content-Type: text/plain; charset="utf-8" Content-ID: <6BC3FFA14AF9404ABEA95E7A878AF78F@internal.synopsys.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v3OFuBab020497 Hi, On Fri, 2017-04-21 at 18:13 +0300, Andy Shevchenko wrote: > On Fri, 2017-04-21 at 14:29 +0000, Eugeniy Paltsev wrote: > > On Tue, 2017-04-18 at 15:31 +0300, Andy Shevchenko wrote: > > > On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote: > > > > This patch adds support for the DW AXI DMAC controller. > > > > +#define AXI_DMA_BUSWIDTHS   \ > > > > + (DMA_SLAVE_BUSWIDTH_1_BYTE | \ > > > > + DMA_SLAVE_BUSWIDTH_2_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_4_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_8_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_16_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_32_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_64_BYTES) > > > > +/* TODO: check: do we need to use BIT() macro here? */ > > > > > > Still TODO? I remember I answered to this on the first round. > > > > Yes, I remember it. > > I left this TODO as a reminder because src_addr_widths and > > dst_addr_widths are > > not used anywhere and they are set differently in different drivers > > (with or without BIT macro). > > Strange. AFAIK they are representing bits (which is not the best > idea) in the resulting u64 field. So, anything bigger than 63 doesn't > make sense. They are u32 fields! >>From dmaengine.h : struct dma_device { ...     u32 src_addr_widths;     u32 dst_addr_widths; }; > In drivers where they are not bits quite likely a bug is hidden. For example (from pxa_dma.c): const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES; And there are a lot of drivers, which don't use BIT for this fields. sh/shdmac.c sh/rcar-dmac.c qcom/bam_dma.c mmp_pdma.c ste_dma40.c And many others... > > > > > > + > > > > +static inline void > > > > +axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) > > > > +{ > > > > + iowrite32(val, chip->regs + reg); > > > > > > Are you going to use IO ports for this IP? I don't think so. > > > Wouldn't be better to call readl()/writel() instead? > > > > As I understand, it's better to use ioread/iowrite as more > > universal > > IO > > access way. Am I wrong? > > As I said above the ioreadX/iowriteX makes only sense when your IP > would be accessed via IO region or MMIO. I'm pretty sure IO is not > the case at all for this IP. MMIO? This IP works exactly via memory-mapped I/O. > > > > +static inline void axi_chan_irq_disable(struct axi_dma_chan > > > > *chan, > > > > u32 irq_mask) > > > > +{ > > > > + u32 val; > > > > + > > > > + if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) { > > > > + axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, > > > > DWAXIDMAC_IRQ_NONE); > > > > + } else { > > > > > > I don't see the benefit. (Yes, I see one read-less path, I think > > > it > > > makes perplexity for nothing here) > > > > This function is called mostly with irq_mask = DWAXIDMAC_IRQ_ALL. > > Actually it is called only with irq_mask = DWAXIDMAC_IRQ_ALL until > > I add DMA_SLAVE support. > > But I can cut off this 'if' statment, if it is necessery. > > It's not necessary, but from my point of view increases readability > of the code a lot for the price of an additional readl(). Ok. > > > > > > + val = axi_chan_ioread32(chan, > > > > CH_INTSTATUS_ENA); > > > > + val &= ~irq_mask; > > > > + axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, > > > > val); > > > > + } > > > > + > > > > + return min_t(size_t, __ffs(sdl), max_width); > > > > +} > > > > +static void axi_desc_put(struct axi_dma_desc *desc) > > > > +{ > > > > + struct axi_dma_chan *chan = desc->chan; > > > > + struct dw_axi_dma *dw = chan->chip->dw; > > > > + struct axi_dma_desc *child, *_next; > > > > + unsigned int descs_put = 0; > > > > + list_for_each_entry_safe(child, _next, &desc- > > > > >xfer_list, > > > > xfer_list) { > > > > > > xfer_list looks redundant. > > > Can you elaborate why virtual channel management is not working > > > for > > > you? > > > > Each virtual descriptor encapsulates several hardware descriptors, > > which belong to same transfer. > > This list (xfer_list) is used only for allocating/freeing these > > descriptors and it doesn't affect on virtual dma work logic. > > I can see this approach in several drivers with VirtDMA (but they > > mostly use array instead of list) > > You described how most of the DMA drivers are implemented, though > they > are using just sg_list directly. I would recommend to do the same and > get rid of this list. This IP can be (ans is) configured with small block size. (note, that I am not saying about runtime HW configuration) And there is opportunity what we can't use sg_list directly and need to split sg_list to a smaller chunks. > > > Btw, are you planning to use priority at all? For now on I didn't > > > see > > > a single driver (from the set I have checked, like 4-5 of them) > > > that > > > uses priority anyhow. It makes driver more complex for nothing. > > > > Only for dma slave operations. > > So, in other words you *have* an actual two or more users that *need* > prioritization? As I remember there was an idea to give higher priority to audio dma chanels. > > > > + if (unlikely(dst_nents == 0 || src_nents == 0)) > > > > + return NULL; > > > > + > > > > + if (unlikely(dst_sg == NULL || src_sg == NULL)) > > > > + return NULL; > > > > > > If we need those checks they should go to > > > dmaengine.h/dmaengine.c. > > > > I checked several drivers, which implements device_prep_dma_sg and > > they > > implements this checkers. > > Should I add something like "dma_sg_desc_invalid" function to > > dmaengine.h ? > > I suppose it's better to implement them in the corresponding helpers > in dmaengine.h. Ok. > > > > +static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, > > > > +    struct axi_dma_desc > > > > *desc_head) > > > > +{ > > > > + struct axi_dma_desc *desc; > > > > + > > > > + axi_chan_dump_lli(chan, desc_head); > > > > + list_for_each_entry(desc, &desc_head->xfer_list, > > > > xfer_list) > > > > + axi_chan_dump_lli(chan, desc); > > > > +} > > > > + > > > > +static void axi_chan_handle_err(struct axi_dma_chan *chan, u32 > > > > status) > > > > +{ > > > > + /* WARN about bad descriptor */ > > > > > > > > + dev_err(chan2dev(chan), > > > > + "Bad descriptor submitted for %s, cookie: %d, > > > > irq: > > > > 0x%08x\n", > > > > + axi_chan_name(chan), vd->tx.cookie, status); > > > > + axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd)); > > > > > > As I said earlier dw_dmac is *bad* example of the (virtual > > > channel > > > based) DMA driver. > > > > > > I guess you may just fail the descriptor and don't pretend it has > > > been processed successfully. > > > > What do you mean by saying "fail the descriptor"? > > After I get error I cancel current transfer and free all > > descriptors > > from it (by calling vchan_cookie_complete). > > I can't store error status in descriptor structure because it will > > be > > freed by vchan_cookie_complete. > > I can't store error status in channel structure because it will be > > overwritten by next transfer. > > Better not to pretend that it has been processed successfully. Don't > call callback on it and set its status to DMA_ERROR (that's why > descriptors in many drivers have dma_status field). When user asks > for > status (using cookie) the saved value would be returned until > descriptor > is active. > > Do you have some other workflow in mind? Hmm... Do you mean I should left error descriptors in desc_issued list or I should create another list (like desc_error) in my driver and move error descriptors to desc_error list? And when exactly should I free error descriptors? I checked hsu/hsu.c dma driver implementation:   vdma descriptor is deleted from desc_issued list when transfer   starts. When descriptor marked as error descriptor   vchan_cookie_complete isn't called for this descriptor. And this   descriptor isn't placed in any list. So error descriptors *never*   will be freed.   I don't actually like this approach. > > > > + > > > > +static const struct dev_pm_ops dw_axi_dma_pm_ops = { > > > > + SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, > > > > axi_dma_runtime_resume, NULL) > > > > +}; > > > > > > Have you tried to build with CONFIG_PM disabled? > > > > Yes. > > > > > I'm pretty sure you need __maybe_unused applied to your PM ops. > > > > I call axi_dma_runtime_suspend / axi_dma_runtime_resume even I > > dont't > > use PM. > > (I call them in probe / remove function.) > > Hmm... I didn't check your ->probe() and ->remove(). Do you mean you > call them explicitly by those names? > > If so, please don't do that. Use pm_runtime_*() instead. And... > > > So I don't need to declare them with __maybe_unused. > > ...in that case it's possible you have them defined but not used. > >>From my ->probe() function: pm_runtime_get_noresume(chip->dev); ret = axi_dma_runtime_resume(chip->dev); Firstly I only incrememt counter. Secondly explicitly call my resume function. I call them explicitly because I need driver to work also without Runtime PM. So I can't just call pm_runtime_get here instead of pm_runtime_get_noresume + axi_dma_runtime_resume. Of course I can copy *all* code from axi_dma_runtime_resume to ->probe() function, but I don't really like this idea. > > > > +struct axi_dma_chan { > > > > + struct axi_dma_chip *chip; > > > > + void __iomem *chan_regs; > > > > + u8 id; > > > > + atomic_t descs_allocated; > > > > + > > > > + struct virt_dma_chan vc; > > > > + > > > > + /* these other elements are all protected by vc.lock > > > > */ > > > > + bool is_paused; > > > > > > I still didn't get (already forgot) why you can't use dma_status > > > instead for the active descriptor? > > > > As I said before, I checked several driver, which have status > > variable > > in their channel structure - it is used *only* for determinating is > > channel paused or not. So there is no much sense in replacing > > "is_paused" to "status" and I left "is_paused" variable untouched. > > Not only (see above), the errored descriptor keeps that status. > > > (I described above why we can't use status in channel structure for > > error handling) > > Ah, I'm talking about descriptor. Again - PAUSED is per-channel flag. So, even if we have status field in each descriptor, it is simpler to use one per-channel flag instead of plenty per-descriptor flags. When we pausing/resuming dma channel it is simpler to set only one flag instead of writing DMA_PAUSED to *each* descriptor status field. > > > > Status Fetch Addr */ > > > > +#define CH_INTSTATUS_ENA 0x080 /* R/W Chan Interrupt > > > > Status > > > > Enable */ > > > > +#define CH_INTSTATUS 0x088 /* R/W Chan > > > > Interrupt > > > > Status */ > > > > +#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt > > > > Signal > > > > Enable */ > > > > +#define CH_INTCLEAR 0x098 /* W Chan Interrupt > > > > Clear > > > > */ > > > > > > I'm wondering if you can use regmap API instead. > > > > Is it really necessary? It'll make driver more complex for nothing. > > That's why I'm not suggesting but wondering. > > > > > > +}; > > > > > > Hmm... do you need them in the header? > > > > I use some of these definitions in my code so I guess yes. > > /* Maybe I misunderstood your question... */ > > I mean, who are the users of them? If it's only one module, there is > no need to put them in header. Yes, only one module. Should I move all this definitions to axi_dma_platform.c file and rid of both axi_dma_platform_reg.h and axi_dma_platform.h headers? > > > > > > +#define CH_CFG_H_TT_FC_POS 0 > > > > +enum { > > > > + DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC = 0x0, > > > > + DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC, > > > > + DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC, > > > > + DWAXIDMAC_TT_FC_PER_TO_PER_DMAC, > > > > + DWAXIDMAC_TT_FC_PER_TO_MEM_SRC, > > > > + DWAXIDMAC_TT_FC_PER_TO_PER_SRC, > > > > + DWAXIDMAC_TT_FC_MEM_TO_PER_DST, > > > > + DWAXIDMAC_TT_FC_PER_TO_PER_DST > > > > +}; > > > > > > Some of definitions are the same as for dw_dmac, right? We might > > > split them to a common header, though I have no strong opinion > > > about > > > > it. > > > Vinod? > > > > APB DMAC and AXI DMAC have completely different regmap. So there is > > no > > much sense to do that. > > I'm not talking about registers, I'm talking about definitions like > above. Though it would be indeed little sense to split some common > code between those two. This definitions are the fields of some registers. So they are also different. --  Eugeniy Paltsev