diff for duplicates of <1493373403-23462-5-git-send-email-varada@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 0f7af51..991baf2 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -61,7 +61,7 @@ index 0000000..c150bea + }; + + soc: soc { -+ pinctrl@1000000 { ++ pinctrl at 1000000 { + serial_4_pins: serial4_pinmux { + mux { + pins = "gpio23", "gpio24"; @@ -71,7 +71,7 @@ index 0000000..c150bea + }; + }; + -+ serial@78b3000 { ++ serial at 78b3000 { + pinctrl-0 = <&serial_4_pins>; + pinctrl-names = "default"; + status = "ok"; @@ -110,7 +110,7 @@ index 0000000..f910cc0 + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + -+ pinctrl@1000000 { ++ pinctrl at 1000000 { + compatible = "qcom,ipq8074-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; @@ -120,7 +120,7 @@ index 0000000..f910cc0 + #interrupt-cells = <0x2>; + }; + -+ intc: interrupt-controller@b000000 { ++ intc: interrupt-controller at b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <0x3>; @@ -136,14 +136,14 @@ index 0000000..f910cc0 + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + -+ gcc: gcc@1800000 { ++ gcc: gcc at 1800000 { + compatible = "qcom,gcc-ipq8074"; + reg = <0x1800000 0x80000>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + }; + -+ serial@78b3000 { ++ serial at 78b3000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b3000 0x200>; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; @@ -180,7 +180,7 @@ index 0000000..f910cc0 + }; + }; + -+ CPU0: cpu@0 { ++ CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; @@ -188,7 +188,7 @@ index 0000000..f910cc0 + enable-method = "psci"; + }; + -+ CPU1: cpu@1 { ++ CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; @@ -196,7 +196,7 @@ index 0000000..f910cc0 + next-level-cache = <&L2_0>; + }; + -+ CPU2: cpu@2 { ++ CPU2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; @@ -204,7 +204,7 @@ index 0000000..f910cc0 + next-level-cache = <&L2_0>; + }; + -+ CPU3: cpu@3 { ++ CPU3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; diff --git a/a/content_digest b/N1/content_digest index cd0fdf6..7615a96 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,28 +1,8 @@ "ref\01493373403-23462-1-git-send-email-varada@codeaurora.org\0" - "From\0Varadarajan Narayanan <varada@codeaurora.org>\0" + "From\0varada@codeaurora.org (Varadarajan Narayanan)\0" "Subject\0[PATCH 4/5] arm64: dts: Add ipq8074 SoC and MTP board support\0" "Date\0Fri, 28 Apr 2017 15:26:42 +0530\0" - "To\0robh+dt@kernel.org" - mark.rutland@arm.com - mturquette@baylibre.com - sboyd@codeaurora.org - linus.walleij@linaro.org - andy.gross@linaro.org - david.brown@linaro.org - catalin.marinas@arm.com - will.deacon@arm.com - devicetree@vger.kernel.org - linux-kernel@vger.kernel.org - linux-clk@vger.kernel.org - linux-gpio@vger.kernel.org - linux-arm-msm@vger.kernel.org - linux-soc@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" - "Cc\0sricharan@codeaurora.org" - absahu@codeaurora.org - sjaganat@codeaurora.org - Varadarajan Narayanan <varada@codeaurora.org> - " Manoharan Vijaya Raghavan <mraghava@codeaurora.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Add initial device tree support for the Qualcomm IPQ8074 SoC and\n" @@ -88,7 +68,7 @@ "+\t};\n" "+\n" "+\tsoc: soc {\n" - "+\t\tpinctrl@1000000 {\n" + "+\t\tpinctrl at 1000000 {\n" "+\t\t\tserial_4_pins: serial4_pinmux {\n" "+\t\t\t\tmux {\n" "+\t\t\t\t\tpins = \"gpio23\", \"gpio24\";\n" @@ -98,7 +78,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tserial@78b3000 {\n" + "+\t\tserial at 78b3000 {\n" "+\t\t\tpinctrl-0 = <&serial_4_pins>;\n" "+\t\t\tpinctrl-names = \"default\";\n" "+\t\t\tstatus = \"ok\";\n" @@ -137,7 +117,7 @@ "+\t\tranges = <0 0 0 0xffffffff>;\n" "+\t\tcompatible = \"simple-bus\";\n" "+\n" - "+\t\tpinctrl@1000000 {\n" + "+\t\tpinctrl at 1000000 {\n" "+\t\t\tcompatible = \"qcom,ipq8074-pinctrl\";\n" "+\t\t\treg = <0x1000000 0x300000>;\n" "+\t\t\tinterrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -147,7 +127,7 @@ "+\t\t\t#interrupt-cells = <0x2>;\n" "+\t\t};\n" "+\n" - "+\t\tintc: interrupt-controller@b000000 {\n" + "+\t\tintc: interrupt-controller at b000000 {\n" "+\t\t\tcompatible = \"qcom,msm-qgic2\";\n" "+\t\t\tinterrupt-controller;\n" "+\t\t\t#interrupt-cells = <0x3>;\n" @@ -163,14 +143,14 @@ "+\t\t\t\t <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n" "+\t\t};\n" "+\n" - "+\t\tgcc: gcc@1800000 {\n" + "+\t\tgcc: gcc at 1800000 {\n" "+\t\t\tcompatible = \"qcom,gcc-ipq8074\";\n" "+\t\t\treg = <0x1800000 0x80000>;\n" "+\t\t\t#clock-cells = <0x1>;\n" "+\t\t\t#reset-cells = <0x1>;\n" "+\t\t};\n" "+\n" - "+\t\tserial@78b3000 {\n" + "+\t\tserial at 78b3000 {\n" "+\t\t\tcompatible = \"qcom,msm-uartdm-v1.4\", \"qcom,msm-uartdm\";\n" "+\t\t\treg = <0x78b3000 0x200>;\n" "+\t\t\tinterrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -207,7 +187,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU0: cpu@0 {\n" + "+\t\tCPU0: cpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0>;\n" @@ -215,7 +195,7 @@ "+\t\t\tenable-method = \"psci\";\n" "+\t\t};\n" "+\n" - "+\t\tCPU1: cpu@1 {\n" + "+\t\tCPU1: cpu at 1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tenable-method = \"psci\";\n" @@ -223,7 +203,7 @@ "+\t\t\tnext-level-cache = <&L2_0>;\n" "+\t\t};\n" "+\n" - "+\t\tCPU2: cpu@2 {\n" + "+\t\tCPU2: cpu at 2 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tenable-method = \"psci\";\n" @@ -231,7 +211,7 @@ "+\t\t\tnext-level-cache = <&L2_0>;\n" "+\t\t};\n" "+\n" - "+\t\tCPU3: cpu@3 {\n" + "+\t\tCPU3: cpu at 3 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tenable-method = \"psci\";\n" @@ -267,4 +247,4 @@ "-- \n" QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -0f84e569a73abf91bccddf86354bac8a62bb1fffce346d88b87137983746e5ea +10088310259625c5033de6c04601131e4e5e745c25b681aa5c9ed2c773ca159e
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