From: <gregkh@linuxfoundation.org>
To: heiko@sntech.de, gregkh@linuxfoundation.org, sboyd@codeaurora.org
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036" has been added to the 4.10-stable tree
Date: Tue, 09 May 2017 11:19:38 +0200 [thread overview]
Message-ID: <1494321578201133@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036
to the 4.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-rockchip-add-to-mux_pll_src_apll_dpll_gpll_usb480m_p-on-rk3036.patch
and it can be found in the queue-4.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From 9b1b23f03abdd25ffde8bbfe5824b89bc0448c28 Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Wed, 1 Mar 2017 22:00:41 +0100
Subject: clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036
From: Heiko Stuebner <heiko@sntech.de>
commit 9b1b23f03abdd25ffde8bbfe5824b89bc0448c28 upstream.
The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.
Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/clk/rockchip/clk-rk3036.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -127,7 +127,7 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gp
PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
-PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll" "usb480m" };
+PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
Patches currently in stable-queue which might be from heiko@sntech.de are
queue-4.10/clk-rockchip-add-to-mux_pll_src_apll_dpll_gpll_usb480m_p-on-rk3036.patch
reply other threads:[~2017-05-09 9:20 UTC|newest]
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