[U-Boot] [PATCH v2 2/5] arm: socfpga: Restructure FPGA driver in the preparation to support A10.

[Chee, Tien Fong <tien.fong.chee@intel.com>]

On Kha, 2017-05-11 at 14:03 +0200, Marek Vasut wrote:
> On 05/11/2017 11:25 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Move FPGA driver which is Gen5 specific code into Gen5 driver file
> > and keeping common FPGA driver intact. All the changes are still
> > keeping
> > in driver/fpga/ and no functional change. Subsequent patch would
> > move
> > header files into include/intel_socfpga and FPGA manager driver
> > from
> > arch/arm into driver/fpga/ .
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  arch/arm/mach-socfpga/Makefile                     |   2 +-
> >  arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  70 ++----
> >  .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 +++---
> >  drivers/Makefile                                   |   1 +
> >  drivers/fpga/Makefile                              |   1 +
> >  drivers/fpga/socfpga.c                             | 243 +------
> > --------------
> >  drivers/fpga/{socfpga.c => socfpga_gen5.c}         |  57 +----
> >  7 files changed, 53 insertions(+), 390 deletions(-)
> >  copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h =>
> > fpga_manager_gen5.h} (57%)
> >  copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (82%)
> > 
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index 41b779c..286bfef 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -9,7 +9,6 @@
> >  
> >  obj-y	+= board.o
> >  obj-y	+= clock_manager.o
> > -obj-y	+= fpga_manager.o
> >  obj-y	+= misc.o
> >  obj-y	+= reset_manager.o
> >  obj-y	+= timer.o
> > @@ -21,6 +20,7 @@ obj-y	+= reset_manager_gen5.o
> >  obj-y	+= scan_manager.o
> >  obj-y	+= system_manager_gen5.o
> >  obj-y	+= wrap_pll_config.o
> > +obj-y	+= fpga_manager.o
> >  endif
> >  
> >  ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
> > diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > index a077e22..f259854 100644
> > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> >   * All rights reserved.
> >   *
> >   * SPDX-License-Identifier:    BSD-3-Clause
> > @@ -10,58 +10,9 @@
> >  
> >  #include <altera.h>
> >  
> > -struct socfpga_fpga_manager {
> > -	/* FPGA Manager Module */
> > -	u32	stat;			/* 0x00 */
> > -	u32	ctrl;
> > -	u32	dclkcnt;
> > -	u32	dclkstat;
> > -	u32	gpo;			/* 0x10 */
> > -	u32	gpi;
> > -	u32	misci;			/* 0x18 */
> > -	u32	_pad_0x1c_0x82c[517];
> > -
> > -	/* Configuration Monitor (MON) Registers */
> > -	u32	gpio_inten;		/* 0x830 */
> > -	u32	gpio_intmask;
> > -	u32	gpio_inttype_level;
> > -	u32	gpio_int_polarity;
> > -	u32	gpio_intstatus;		/* 0x840 */
> > -	u32	gpio_raw_intstatus;
> > -	u32	_pad_0x848;
> > -	u32	gpio_porta_eoi;
> > -	u32	gpio_ext_porta;		/* 0x850 */
> > -	u32	_pad_0x854_0x85c[3];
> > -	u32	gpio_1s_sync;		/* 0x860 */
> > -	u32	_pad_0x864_0x868[2];
> > -	u32	gpio_ver_id_code;
> > -	u32	gpio_config_reg2;	/* 0x870 */
> > -	u32	gpio_config_reg1;
> > -};
> > -
> > -#define FPGAMGRREGS_STAT_MODE_MASK		0x7
> > -#define FPGAMGRREGS_STAT_MSEL_MASK		0xf8
> > -#define FPGAMGRREGS_STAT_MSEL_LSB		3
> > -
> > -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK		0x200
> > -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK		0x100
> > -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK	0x4
> > -#define FPGAMGRREGS_CTRL_NCE_MASK		0x2
> > -#define FPGAMGRREGS_CTRL_EN_MASK		0x1
> > -#define FPGAMGRREGS_CTRL_CDRATIO_LSB		6
> > -
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK	0x8
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK	0x4
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK	0x2
> > -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK	0x1
> > -
> > -/* FPGA Mode */
> > -#define FPGAMGRREGS_MODE_FPGAOFF		0x0
> > -#define FPGAMGRREGS_MODE_RESETPHASE		0x1
> > -#define FPGAMGRREGS_MODE_CFGPHASE		0x2
> > -#define FPGAMGRREGS_MODE_INITPHASE		0x3
> > -#define FPGAMGRREGS_MODE_USERMODE		0x4
> > -#define FPGAMGRREGS_MODE_UNKNOWN		0x5
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +#include <asm/arch/fpga_manager_gen5.h>
> > +#endif
> >  
> >  /* FPGA CD Ratio Value */
> >  #define CDRATIO_x1				0x0
> > @@ -70,8 +21,17 @@ struct socfpga_fpga_manager {
> >  #define CDRATIO_x8				0x3
> >  
> >  /* SoCFPGA support functions */
> > -int fpgamgr_test_fpga_ready(void);
> > -int fpgamgr_poll_fpga_ready(void);
> >  int fpgamgr_get_mode(void);
> > +int fpgamgr_poll_fpga_ready(void);
> > +void fpgamgr_program_write(const void *rbf_data, unsigned long
> > rbf_size);
> use size_t for size .
> 
Okay.
> > 
> > +int fpgamgr_test_fpga_ready(void);
> > +
> > +#define FPGA_TIMEOUT_CNT	0x1000000
> Does that need to be in header file ?
> 
Yeah, gen5 and Arria10 driver need this macro.
> > 
> > +#ifndef __ASSEMBLY__
> > +
> > +/* Common prototypes */
> > +int fpgamgr_dclkcnt_set(unsigned long cnt);
> >  
> > +#endif /* __ASSEMBLY__ */
> >  #endif /* _FPGA_MANAGER_H_ */
> [...]
> > 
> > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c
> > similarity index 82%
> > copy from drivers/fpga/socfpga.c
> > copy to drivers/fpga/socfpga_gen5.c
> > index f1b2f2c..269e81e 100644
> > --- a/drivers/fpga/socfpga.c
> > +++ b/drivers/fpga/socfpga_gen5.c
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> Removal of code doesn't extend copyright IMO.
> 
Oh....okay, understood. I will revert back.
> > 
> >   * All rights reserved.
> >   *
> >   * SPDX-License-Identifier:	BSD-3-Clause
> > @@ -14,9 +14,6 @@
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > -/* Timeout count */
> > -#define FPGA_TIMEOUT_CNT		0x1000000
> > -
> >  static struct socfpga_fpga_manager *fpgamgr_regs =
> >  	(struct socfpga_fpga_manager
> > *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> >  static struct socfpga_system_manager *sysmgr_regs =
> > @@ -30,29 +27,6 @@ static void fpgamgr_set_cd_ratio(unsigned long
> > ratio)
> >  			(ratio & 0x3) <<
> > FPGAMGRREGS_CTRL_CDRATIO_LSB);
> >  }
> >  
> > -static int fpgamgr_dclkcnt_set(unsigned long cnt)
> > -{
> > -	unsigned long i;
> > -
> > -	/* Clear any existing done status */
> > -	if (readl(&fpgamgr_regs->dclkstat))
> > -		writel(0x1, &fpgamgr_regs->dclkstat);
> > -
> > -	/* Write the dclkcnt */
> > -	writel(cnt, &fpgamgr_regs->dclkcnt);
> > -
> > -	/* Wait till the dclkcnt done */
> > -	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
> > -		if (!readl(&fpgamgr_regs->dclkstat))
> > -			continue;
> > -
> > -		writel(0x1, &fpgamgr_regs->dclkstat);
> > -		return 0;
> > -	}
> > -
> > -	return -ETIMEDOUT;
> > -}
> > -
> >  /* Start the FPGA programming by initialize the FPGA Manager */
> >  static int fpgamgr_program_init(void)
> >  {
> > @@ -143,34 +117,6 @@ static int fpgamgr_program_init(void)
> >  	return 0;
> >  }
> >  
> > -/* Write the RBF data to FPGA Manager */
> > -static void fpgamgr_program_write(const void *rbf_data, unsigned
> > long rbf_size)
> > -{
> > -	uint32_t src = (uint32_t)rbf_data;
> > -	uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
> > -
> > -	/* Number of loops for 32-byte long copying. */
> > -	uint32_t loops32 = rbf_size / 32;
> > -	/* Number of loops for 4-byte long copying + trailing
> > bytes */
> > -	uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
> > -
> > -	asm volatile(
> > -		"1:	ldmia	%0!,	{r0-r7}\n"
> > -		"	stmia	%1!,	{r0-r7}\n"
> > -		"	sub	%1,	#32\n"
> > -		"	subs	%2,	#1\n"
> > -		"	bne	1b\n"
> > -		"	cmp	%3,	#0\n"
> > -		"	beq	3f\n"
> > -		"2:	ldr	%2,	[%0],	#4\n
> > "
> > -		"	str	%2,	[%1]\n"
> > -		"	subs	%3,	#1\n"
> > -		"	bne	2b\n"
> > -		"3:	nop\n"
> > -		: "+r"(src), "+r"(dst), "+r"(loops32),
> > "+r"(loops4) :
> > -		: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> > "cc");
> > -}
> > -
> >  /* Ensure the FPGA entering config done */
> >  static int fpgamgr_program_poll_cd(void)
> >  {
> > @@ -267,7 +213,6 @@ int socfpga_load(Altera_desc *desc, const void
> > *rbf_data, size_t rbf_size)
> >  	}
> >  
> >  	/* Prior programming the FPGA, all bridges need to be shut
> > off */
> > -
> Drop this bit
> 
Are you means dropping "-"? Ermm... how to drop this as this is
generated from git.
> > 
> >  	/* Disable all signals from hps peripheral controller to
> > fpga */
> >  	writel(0, &sysmgr_regs->fpgaintfgrp_module);
> >  
> > 
>