diff for duplicates of <1495711858.5393.37.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index 1692f9c..c80bdb4 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,29 +1,29 @@ Hi Noam, -On Thu, 2017-05-25@11:26 +0000, Noam Camus wrote: +On Thu, 2017-05-25 at 11:26 +0000, Noam Camus wrote: > > -> > From: Alexey Brodkin [mailto:Alexey.Brodkin at synopsys.com]? +> > From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com] > > Sent: Thursday, May 25, 2017 14:15 PM > > > > > > > > > -> > > diff --git a/arch/arc/kernel/entry-compact.S? +> > > diff --git a/arch/arc/kernel/entry-compact.S > > > b/arch/arc/kernel/entry-compact.S index f285dbb..d152d36 100644 > > > --- a/arch/arc/kernel/entry-compact.S > > > +++ b/arch/arc/kernel/entry-compact.S > > > @@ -203,6 +203,17 @@ END(handle_interrupt_level2) -> > > ?; --------------------------------------------- -> > > ?ENTRY(mem_service) -> > > ? +> > > ; --------------------------------------------- +> > > ENTRY(mem_service) +> > > > > > +#if defined(CONFIG_EZNPS_MEM_ERROR) -> > > +????????; SW workaround to cover up on a difference between -> > > +????????; NPS real chip and simulator behaviors. -> > > +????????; NPS real chip will activate a machine check exception -> > > +????????; in case of memory error, while the simulator will -> > > +????????; trigger a level 2 interrupt. Therefor this code section -> > > +????????; should be reached only in simulation mode. -> > > +????????; DEAD END: display Regs and HALT +> > > + ; SW workaround to cover up on a difference between +> > > + ; NPS real chip and simulator behaviors. +> > > + ; NPS real chip will activate a machine check exception +> > > + ; in case of memory error, while the simulator will +> > > + ; trigger a level 2 interrupt. Therefor this code section +> > > + ; should be reached only in simulation mode. +> > > + ; DEAD END: display Regs and HALT > > > > > I'm not really buying that. diff --git a/a/content_digest b/N1/content_digest index 8fa0ca0..4eb2ed0 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,38 +2,41 @@ "ref\01495679660-9598-11-git-send-email-noamca@mellanox.com\0" "ref\01495710896.5393.32.camel@synopsys.com\0" "ref\0DB5PR05MB1638C447032283FC639A30E8AAFF0@DB5PR05MB1638.eurprd05.prod.outlook.com\0" - "From\0Alexey.Brodkin@synopsys.com (Alexey Brodkin)\0" - "Subject\0[PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception\0" + "From\0Alexey Brodkin <Alexey.Brodkin@synopsys.com>\0" + "Subject\0Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception\0" "Date\0Thu, 25 May 2017 11:30:59 +0000\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0noamca@mellanox.com <noamca@mellanox.com>\0" + "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" + eladkan@mellanox.com <eladkan@mellanox.com> + " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" "\00:1\0" "b\0" "Hi Noam,\n" "\n" - "On Thu, 2017-05-25@11:26 +0000, Noam Camus wrote:\n" + "On Thu, 2017-05-25 at 11:26 +0000, Noam Camus wrote:\n" "> > \n" - "> > From: Alexey Brodkin [mailto:Alexey.Brodkin at synopsys.com]?\n" + "> > From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com]\302\240\n" "> > Sent: Thursday, May 25, 2017 14:15 PM\n" "> \n" "> > \n" "> > > \n" "> > > \n" - "> > > diff --git a/arch/arc/kernel/entry-compact.S?\n" + "> > > diff --git a/arch/arc/kernel/entry-compact.S\302\240\n" "> > > b/arch/arc/kernel/entry-compact.S index f285dbb..d152d36 100644\n" "> > > --- a/arch/arc/kernel/entry-compact.S\n" "> > > +++ b/arch/arc/kernel/entry-compact.S\n" "> > > @@ -203,6 +203,17 @@ END(handle_interrupt_level2)\n" - "> > > ?; ---------------------------------------------\n" - "> > > ?ENTRY(mem_service)\n" - "> > > ?\n" + "> > > \302\240; ---------------------------------------------\n" + "> > > \302\240ENTRY(mem_service)\n" + "> > > \302\240\n" "> > > +#if defined(CONFIG_EZNPS_MEM_ERROR)\n" - "> > > +????????; SW workaround to cover up on a difference between\n" - "> > > +????????; NPS real chip and simulator behaviors.\n" - "> > > +????????; NPS real chip will activate a machine check exception\n" - "> > > +????????; in case of memory error, while the simulator will\n" - "> > > +????????; trigger a level 2 interrupt. Therefor this code section\n" - "> > > +????????; should be reached only in simulation mode.\n" - "> > > +????????; DEAD END: display Regs and HALT\n" + "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240; SW workaround to cover up on a difference between\n" + "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240; NPS real chip and simulator behaviors.\n" + "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240; NPS real chip will activate a machine check exception\n" + "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240; in case of memory error, while the simulator will\n" + "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240; trigger a level 2 interrupt. Therefor this code section\n" + "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240; should be reached only in simulation mode.\n" + "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240; DEAD END: display Regs and HALT\n" "> \n" "> > \n" "> > I'm not really buying that.\n" @@ -47,4 +50,4 @@ "\n" -Alexey -79a0a6f842873b6fe5aaefb05208e9bdc7bf5591a34d7bf6dabf3dcc80dedcd6 +d2c23c297bdec97ef38b93b3d2ab88c3cc577fed50c9762f3b6feba0b6ae46a7
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