diff for duplicates of <1496064471.2741.0.camel@baylibre.com> diff --git a/a/1.txt b/N1/1.txt index ef8a919..3dc5c7d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -21,19 +21,19 @@ Thx Jerome > --- -> ?drivers/clk/meson/gxbb.c | 54 +> drivers/clk/meson/gxbb.c | 54 > ++++++++++++++++++++++++++++++++++++++++++++++++ -> ?drivers/clk/meson/gxbb.h |??5 ++++- -> ?2 files changed, 58 insertions(+), 1 deletion(-) +> drivers/clk/meson/gxbb.h | 5 ++++- +> 2 files changed, 58 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c > index ad5f027..4b7d85a 100644 > --- a/drivers/clk/meson/gxbb.c > +++ b/drivers/clk/meson/gxbb.c > @@ -951,6 +951,51 @@ struct pll_params_table gxl_gp0_params_table[] = { -> ? }, -> ?}; -> ? +> }, +> }; +> > +static struct clk_divider gxbb_32k_clk_div = { > + .reg = (void *)HHI_32K_CLK_CNTL, > + .shift = 0, @@ -79,67 +79,67 @@ Jerome > + }, > +}; > + -> ?/* Everything Else (EE) domain gates */ -> ?static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); -> ?static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); +> /* Everything Else (EE) domain gates */ +> static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); +> static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); > @@ -1158,6 +1203,9 @@ struct pll_params_table gxl_gp0_params_table[] = { -> ? [CLKID_CTS_MCLK_I958_SEL]???= &gxbb_cts_mclk_i958_sel.hw, -> ? [CLKID_CTS_MCLK_I958_DIV]???= &gxbb_cts_mclk_i958_div.hw, -> ? [CLKID_CTS_I958] ????= &gxbb_cts_i958.hw, -> + [CLKID_32K_CLK] ????= &gxbb_32k_clk.hw, -> + [CLKID_32K_CLK_SEL] ????= &gxbb_32k_clk_sel.hw, -> + [CLKID_32K_CLK_DIV] ????= &gxbb_32k_clk_div.hw, -> ? }, -> ? .num = NR_CLKS, -> ?}; +> [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, +> [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, +> [CLKID_CTS_I958] = &gxbb_cts_i958.hw, +> + [CLKID_32K_CLK] = &gxbb_32k_clk.hw, +> + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, +> + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, +> }, +> .num = NR_CLKS, +> }; > @@ -1278,6 +1326,9 @@ struct pll_params_table gxl_gp0_params_table[] = { -> ? [CLKID_CTS_MCLK_I958_SEL]???= &gxbb_cts_mclk_i958_sel.hw, -> ? [CLKID_CTS_MCLK_I958_DIV]???= &gxbb_cts_mclk_i958_div.hw, -> ? [CLKID_CTS_I958] ????= &gxbb_cts_i958.hw, -> + [CLKID_32K_CLK] ????= &gxbb_32k_clk.hw, -> + [CLKID_32K_CLK_SEL] ????= &gxbb_32k_clk_sel.hw, -> + [CLKID_32K_CLK_DIV] ????= &gxbb_32k_clk_div.hw, -> ? }, -> ? .num = NR_CLKS, -> ?}; +> [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, +> [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, +> [CLKID_CTS_I958] = &gxbb_cts_i958.hw, +> + [CLKID_32K_CLK] = &gxbb_32k_clk.hw, +> + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, +> + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, +> }, +> .num = NR_CLKS, +> }; > @@ -1392,6 +1443,7 @@ struct pll_params_table gxl_gp0_params_table[] = { -> ? &gxbb_mali_1, -> ? &gxbb_cts_amclk, -> ? &gxbb_cts_mclk_i958, +> &gxbb_mali_1, +> &gxbb_cts_amclk, +> &gxbb_cts_mclk_i958, > + &gxbb_32k_clk, -> ?}; -> ? -> ?static struct clk_mux *const gxbb_clk_muxes[] = { +> }; +> +> static struct clk_mux *const gxbb_clk_muxes[] = { > @@ -1403,6 +1455,7 @@ struct pll_params_table gxl_gp0_params_table[] = { -> ? &gxbb_cts_amclk_sel, -> ? &gxbb_cts_mclk_i958_sel, -> ? &gxbb_cts_i958, +> &gxbb_cts_amclk_sel, +> &gxbb_cts_mclk_i958_sel, +> &gxbb_cts_i958, > + &gxbb_32k_clk_sel, -> ?}; -> ? -> ?static struct clk_divider *const gxbb_clk_dividers[] = { +> }; +> +> static struct clk_divider *const gxbb_clk_dividers[] = { > @@ -1411,6 +1464,7 @@ struct pll_params_table gxl_gp0_params_table[] = { -> ? &gxbb_mali_0_div, -> ? &gxbb_mali_1_div, -> ? &gxbb_cts_mclk_i958_div, +> &gxbb_mali_0_div, +> &gxbb_mali_1_div, +> &gxbb_cts_mclk_i958_div, > + &gxbb_32k_clk_div, -> ?}; -> ? -> ?static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { +> }; +> +> static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { > diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h > index 93b8f07..de5fad0 100644 > --- a/drivers/clk/meson/gxbb.h > +++ b/drivers/clk/meson/gxbb.h > @@ -284,8 +284,11 @@ -> ?#define CLKID_CTS_MCLK_I958_SEL ??111 -> ?#define CLKID_CTS_MCLK_I958_DIV ??112 -> ?#define CLKID_CTS_I958 ??113 -> +#define CLKID_32K_CLK ??114 -> +#define CLKID_32K_CLK_SEL ??115 -> +#define CLKID_32K_CLK_DIV ??116 -> ? -> -#define NR_CLKS ??114 -> +#define NR_CLKS ??117 -> ? -> ?/* include the CLKIDs that have been made part of the stable DT binding */ -> ?#include <dt-bindings/clock/gxbb-clkc.h> +> #define CLKID_CTS_MCLK_I958_SEL 111 +> #define CLKID_CTS_MCLK_I958_DIV 112 +> #define CLKID_CTS_I958 113 +> +#define CLKID_32K_CLK 114 +> +#define CLKID_32K_CLK_SEL 115 +> +#define CLKID_32K_CLK_DIV 116 +> +> -#define NR_CLKS 114 +> +#define NR_CLKS 117 +> +> /* include the CLKIDs that have been made part of the stable DT binding */ +> #include <dt-bindings/clock/gxbb-clkc.h> diff --git a/a/content_digest b/N1/content_digest index add8d02..94067fe 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,12 @@ "ref\01495619025-1958-1-git-send-email-narmstrong@baylibre.com\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH] clk: meson-gxbb: Add EE 32K Clock for CEC\0" + "From\0Jerome Brunet <jbrunet@baylibre.com>\0" + "Subject\0Re: [PATCH] clk: meson-gxbb: Add EE 32K Clock for CEC\0" "Date\0Mon, 29 May 2017 15:27:51 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Neil Armstrong <narmstrong@baylibre.com>\0" + "Cc\0linux-amlogic@lists.infradead.org" + linux-clk@vger.kernel.org + linux-arm-kernel@lists.infradead.org + " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" "On Wed, 2017-05-24 at 11:43 +0200, Neil Armstrong wrote:\n" @@ -28,19 +32,19 @@ "Jerome\n" "\n" "> ---\n" - "> ?drivers/clk/meson/gxbb.c | 54\n" + "> \302\240drivers/clk/meson/gxbb.c | 54\n" "> ++++++++++++++++++++++++++++++++++++++++++++++++\n" - "> ?drivers/clk/meson/gxbb.h |??5 ++++-\n" - "> ?2 files changed, 58 insertions(+), 1 deletion(-)\n" + "> \302\240drivers/clk/meson/gxbb.h |\302\240\302\2405 ++++-\n" + "> \302\2402 files changed, 58 insertions(+), 1 deletion(-)\n" "> \n" "> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c\n" "> index ad5f027..4b7d85a 100644\n" "> --- a/drivers/clk/meson/gxbb.c\n" "> +++ b/drivers/clk/meson/gxbb.c\n" "> @@ -951,6 +951,51 @@ struct pll_params_table gxl_gp0_params_table[] = {\n" - "> ?\t},\n" - "> ?};\n" - "> ?\n" + "> \302\240\t},\n" + "> \302\240};\n" + "> \302\240\n" "> +static struct clk_divider gxbb_32k_clk_div = {\n" "> +\t.reg = (void *)HHI_32K_CLK_CNTL,\n" "> +\t.shift = 0,\n" @@ -86,69 +90,69 @@ "> +\t},\n" "> +};\n" "> +\n" - "> ?/* Everything Else (EE) domain gates */\n" - "> ?static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);\n" - "> ?static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);\n" + "> \302\240/* Everything Else (EE) domain gates */\n" + "> \302\240static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);\n" + "> \302\240static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);\n" "> @@ -1158,6 +1203,9 @@ struct pll_params_table gxl_gp0_params_table[] = {\n" - "> ?\t\t[CLKID_CTS_MCLK_I958_SEL]???= &gxbb_cts_mclk_i958_sel.hw,\n" - "> ?\t\t[CLKID_CTS_MCLK_I958_DIV]???= &gxbb_cts_mclk_i958_div.hw,\n" - "> ?\t\t[CLKID_CTS_I958]\t????= &gxbb_cts_i958.hw,\n" - "> +\t\t[CLKID_32K_CLK]\t\t????= &gxbb_32k_clk.hw,\n" - "> +\t\t[CLKID_32K_CLK_SEL]\t????= &gxbb_32k_clk_sel.hw,\n" - "> +\t\t[CLKID_32K_CLK_DIV]\t????= &gxbb_32k_clk_div.hw,\n" - "> ?\t},\n" - "> ?\t.num = NR_CLKS,\n" - "> ?};\n" + "> \302\240\t\t[CLKID_CTS_MCLK_I958_SEL]\302\240\302\240\302\240= &gxbb_cts_mclk_i958_sel.hw,\n" + "> \302\240\t\t[CLKID_CTS_MCLK_I958_DIV]\302\240\302\240\302\240= &gxbb_cts_mclk_i958_div.hw,\n" + "> \302\240\t\t[CLKID_CTS_I958]\t\302\240\302\240\302\240\302\240= &gxbb_cts_i958.hw,\n" + "> +\t\t[CLKID_32K_CLK]\t\t\302\240\302\240\302\240\302\240= &gxbb_32k_clk.hw,\n" + "> +\t\t[CLKID_32K_CLK_SEL]\t\302\240\302\240\302\240\302\240= &gxbb_32k_clk_sel.hw,\n" + "> +\t\t[CLKID_32K_CLK_DIV]\t\302\240\302\240\302\240\302\240= &gxbb_32k_clk_div.hw,\n" + "> \302\240\t},\n" + "> \302\240\t.num = NR_CLKS,\n" + "> \302\240};\n" "> @@ -1278,6 +1326,9 @@ struct pll_params_table gxl_gp0_params_table[] = {\n" - "> ?\t\t[CLKID_CTS_MCLK_I958_SEL]???= &gxbb_cts_mclk_i958_sel.hw,\n" - "> ?\t\t[CLKID_CTS_MCLK_I958_DIV]???= &gxbb_cts_mclk_i958_div.hw,\n" - "> ?\t\t[CLKID_CTS_I958]\t????= &gxbb_cts_i958.hw,\n" - "> +\t\t[CLKID_32K_CLK]\t\t????= &gxbb_32k_clk.hw,\n" - "> +\t\t[CLKID_32K_CLK_SEL]\t????= &gxbb_32k_clk_sel.hw,\n" - "> +\t\t[CLKID_32K_CLK_DIV]\t????= &gxbb_32k_clk_div.hw,\n" - "> ?\t},\n" - "> ?\t.num = NR_CLKS,\n" - "> ?};\n" + "> \302\240\t\t[CLKID_CTS_MCLK_I958_SEL]\302\240\302\240\302\240= &gxbb_cts_mclk_i958_sel.hw,\n" + "> \302\240\t\t[CLKID_CTS_MCLK_I958_DIV]\302\240\302\240\302\240= &gxbb_cts_mclk_i958_div.hw,\n" + "> \302\240\t\t[CLKID_CTS_I958]\t\302\240\302\240\302\240\302\240= &gxbb_cts_i958.hw,\n" + "> +\t\t[CLKID_32K_CLK]\t\t\302\240\302\240\302\240\302\240= &gxbb_32k_clk.hw,\n" + "> +\t\t[CLKID_32K_CLK_SEL]\t\302\240\302\240\302\240\302\240= &gxbb_32k_clk_sel.hw,\n" + "> +\t\t[CLKID_32K_CLK_DIV]\t\302\240\302\240\302\240\302\240= &gxbb_32k_clk_div.hw,\n" + "> \302\240\t},\n" + "> \302\240\t.num = NR_CLKS,\n" + "> \302\240};\n" "> @@ -1392,6 +1443,7 @@ struct pll_params_table gxl_gp0_params_table[] = {\n" - "> ?\t&gxbb_mali_1,\n" - "> ?\t&gxbb_cts_amclk,\n" - "> ?\t&gxbb_cts_mclk_i958,\n" + "> \302\240\t&gxbb_mali_1,\n" + "> \302\240\t&gxbb_cts_amclk,\n" + "> \302\240\t&gxbb_cts_mclk_i958,\n" "> +\t&gxbb_32k_clk,\n" - "> ?};\n" - "> ?\n" - "> ?static struct clk_mux *const gxbb_clk_muxes[] = {\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240static struct clk_mux *const gxbb_clk_muxes[] = {\n" "> @@ -1403,6 +1455,7 @@ struct pll_params_table gxl_gp0_params_table[] = {\n" - "> ?\t&gxbb_cts_amclk_sel,\n" - "> ?\t&gxbb_cts_mclk_i958_sel,\n" - "> ?\t&gxbb_cts_i958,\n" + "> \302\240\t&gxbb_cts_amclk_sel,\n" + "> \302\240\t&gxbb_cts_mclk_i958_sel,\n" + "> \302\240\t&gxbb_cts_i958,\n" "> +\t&gxbb_32k_clk_sel,\n" - "> ?};\n" - "> ?\n" - "> ?static struct clk_divider *const gxbb_clk_dividers[] = {\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240static struct clk_divider *const gxbb_clk_dividers[] = {\n" "> @@ -1411,6 +1464,7 @@ struct pll_params_table gxl_gp0_params_table[] = {\n" - "> ?\t&gxbb_mali_0_div,\n" - "> ?\t&gxbb_mali_1_div,\n" - "> ?\t&gxbb_cts_mclk_i958_div,\n" + "> \302\240\t&gxbb_mali_0_div,\n" + "> \302\240\t&gxbb_mali_1_div,\n" + "> \302\240\t&gxbb_cts_mclk_i958_div,\n" "> +\t&gxbb_32k_clk_div,\n" - "> ?};\n" - "> ?\n" - "> ?static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {\n" + "> \302\240};\n" + "> \302\240\n" + "> \302\240static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {\n" "> diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h\n" "> index 93b8f07..de5fad0 100644\n" "> --- a/drivers/clk/meson/gxbb.h\n" "> +++ b/drivers/clk/meson/gxbb.h\n" "> @@ -284,8 +284,11 @@\n" - "> ?#define CLKID_CTS_MCLK_I958_SEL\t??111\n" - "> ?#define CLKID_CTS_MCLK_I958_DIV\t??112\n" - "> ?#define CLKID_CTS_I958\t\t??113\n" - "> +#define CLKID_32K_CLK\t\t??114\n" - "> +#define CLKID_32K_CLK_SEL\t??115\n" - "> +#define CLKID_32K_CLK_DIV\t??116\n" - "> ?\n" - "> -#define NR_CLKS\t\t\t??114\n" - "> +#define NR_CLKS\t\t\t??117\n" - "> ?\n" - "> ?/* include the CLKIDs that have been made part of the stable DT binding */\n" - > ?#include <dt-bindings/clock/gxbb-clkc.h> + "> \302\240#define CLKID_CTS_MCLK_I958_SEL\t\302\240\302\240111\n" + "> \302\240#define CLKID_CTS_MCLK_I958_DIV\t\302\240\302\240112\n" + "> \302\240#define CLKID_CTS_I958\t\t\302\240\302\240113\n" + "> +#define CLKID_32K_CLK\t\t\302\240\302\240114\n" + "> +#define CLKID_32K_CLK_SEL\t\302\240\302\240115\n" + "> +#define CLKID_32K_CLK_DIV\t\302\240\302\240116\n" + "> \302\240\n" + "> -#define NR_CLKS\t\t\t\302\240\302\240114\n" + "> +#define NR_CLKS\t\t\t\302\240\302\240117\n" + "> \302\240\n" + "> \302\240/* include the CLKIDs that have been made part of the stable DT binding */\n" + "> \302\240#include <dt-bindings/clock/gxbb-clkc.h>" -8552f454dbbe148067399b8bafb219bf9dbdc07041f8b6eb61e0e39f3ab2a98a +9a3e991067c4a3f6c6a8da76f33a93bcbc7bb1320fa2a86acc529d91a0bfef65
diff --git a/a/content_digest b/N2/content_digest index add8d02..1d1e995 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,7 +2,7 @@ "From\0jbrunet@baylibre.com (Jerome Brunet)\0" "Subject\0[PATCH] clk: meson-gxbb: Add EE 32K Clock for CEC\0" "Date\0Mon, 29 May 2017 15:27:51 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Wed, 2017-05-24 at 11:43 +0200, Neil Armstrong wrote:\n" @@ -151,4 +151,4 @@ "> ?/* include the CLKIDs that have been made part of the stable DT binding */\n" > ?#include <dt-bindings/clock/gxbb-clkc.h> -8552f454dbbe148067399b8bafb219bf9dbdc07041f8b6eb61e0e39f3ab2a98a +c50a000bdef51f73270910c748e4961245062dcd868c07361e97fa4fda760d2e
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