diff for duplicates of <1496474875-7190-6-git-send-email-varada@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 47555e4..afd0e86 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -65,7 +65,7 @@ index 0000000..7d44be9 + }; + + soc { -+ pinctrl@1000000 { ++ pinctrl at 1000000 { + serial_4_pins: serial4_pinmux { + mux { + pins = "gpio23", "gpio24"; @@ -75,7 +75,7 @@ index 0000000..7d44be9 + }; + }; + -+ serial@78b3000 { ++ serial at 78b3000 { + pinctrl-0 = <&serial_4_pins>; + pinctrl-names = "default"; + status = "ok"; @@ -114,7 +114,7 @@ index 0000000..2bc5dec + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + -+ pinctrl@1000000 { ++ pinctrl at 1000000 { + compatible = "qcom,ipq8074-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; @@ -124,7 +124,7 @@ index 0000000..2bc5dec + #interrupt-cells = <0x2>; + }; + -+ intc: interrupt-controller@b000000 { ++ intc: interrupt-controller at b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <0x3>; @@ -139,7 +139,7 @@ index 0000000..2bc5dec + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + -+ timer@b120000 { ++ timer at b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; @@ -147,7 +147,7 @@ index 0000000..2bc5dec + reg = <0xb120000 0x1000>; + clock-frequency = <19200000>; + -+ frame@b120000 { ++ frame at b120000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -155,42 +155,42 @@ index 0000000..2bc5dec + <0xb122000 0x1000>; + }; + -+ frame@b123000 { ++ frame at b123000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + -+ frame@b124000 { ++ frame at b124000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + -+ frame@b125000 { ++ frame at b125000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + -+ frame@b126000 { ++ frame at b126000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + -+ frame@b127000 { ++ frame at b127000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + -+ frame@b128000 { ++ frame at b128000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb128000 0x1000>; @@ -198,14 +198,14 @@ index 0000000..2bc5dec + }; + }; + -+ gcc: gcc@1800000 { ++ gcc: gcc at 1800000 { + compatible = "qcom,gcc-ipq8074"; + reg = <0x1800000 0x80000>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + }; + -+ blsp1_uart5: serial@78b3000 { ++ blsp1_uart5: serial at 78b3000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b3000 0x200>; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; @@ -220,7 +220,7 @@ index 0000000..2bc5dec + #address-cells = <0x1>; + #size-cells = <0x0>; + -+ CPU0: cpu@0 { ++ CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; @@ -228,7 +228,7 @@ index 0000000..2bc5dec + enable-method = "psci"; + }; + -+ CPU1: cpu@1 { ++ CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; @@ -236,7 +236,7 @@ index 0000000..2bc5dec + next-level-cache = <&L2_0>; + }; + -+ CPU2: cpu@2 { ++ CPU2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; @@ -244,7 +244,7 @@ index 0000000..2bc5dec + next-level-cache = <&L2_0>; + }; + -+ CPU3: cpu@3 { ++ CPU3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; diff --git a/a/content_digest b/N1/content_digest index 4ee78cb..979e224 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,29 +1,8 @@ "ref\01496474875-7190-1-git-send-email-varada@codeaurora.org\0" - "From\0Varadarajan Narayanan <varada@codeaurora.org>\0" + "From\0varada@codeaurora.org (Varadarajan Narayanan)\0" "Subject\0[PATCH v4 5/6] arm64: dts: Add ipq8074 SoC and HK01 board support\0" "Date\0Sat, 3 Jun 2017 12:57:54 +0530\0" - "To\0robh+dt@kernel.org" - mark.rutland@arm.com - mturquette@baylibre.com - sboyd@codeaurora.org - linus.walleij@linaro.org - andy.gross@linaro.org - david.brown@linaro.org - catalin.marinas@arm.com - will.deacon@arm.com - devicetree@vger.kernel.org - linux-kernel@vger.kernel.org - linux-clk@vger.kernel.org - linux-gpio@vger.kernel.org - linux-arm-msm@vger.kernel.org - linux-soc@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " bjorn.andersson@linaro.org\0" - "Cc\0absahu@codeaurora.org" - sjaganat@codeaurora.org - sricharan@codeaurora.org - varada@codeaurora.org - " mraghava@codeaurora.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Add initial device tree support for the Qualcomm IPQ8074 SoC and\n" @@ -93,7 +72,7 @@ "+\t};\n" "+\n" "+\tsoc {\n" - "+\t\tpinctrl@1000000 {\n" + "+\t\tpinctrl at 1000000 {\n" "+\t\t\tserial_4_pins: serial4_pinmux {\n" "+\t\t\t\tmux {\n" "+\t\t\t\t\tpins = \"gpio23\", \"gpio24\";\n" @@ -103,7 +82,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tserial@78b3000 {\n" + "+\t\tserial at 78b3000 {\n" "+\t\t\tpinctrl-0 = <&serial_4_pins>;\n" "+\t\t\tpinctrl-names = \"default\";\n" "+\t\t\tstatus = \"ok\";\n" @@ -142,7 +121,7 @@ "+\t\tranges = <0 0 0 0xffffffff>;\n" "+\t\tcompatible = \"simple-bus\";\n" "+\n" - "+\t\tpinctrl@1000000 {\n" + "+\t\tpinctrl at 1000000 {\n" "+\t\t\tcompatible = \"qcom,ipq8074-pinctrl\";\n" "+\t\t\treg = <0x1000000 0x300000>;\n" "+\t\t\tinterrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -152,7 +131,7 @@ "+\t\t\t#interrupt-cells = <0x2>;\n" "+\t\t};\n" "+\n" - "+\t\tintc: interrupt-controller@b000000 {\n" + "+\t\tintc: interrupt-controller at b000000 {\n" "+\t\t\tcompatible = \"qcom,msm-qgic2\";\n" "+\t\t\tinterrupt-controller;\n" "+\t\t\t#interrupt-cells = <0x3>;\n" @@ -167,7 +146,7 @@ "+\t\t\t\t <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n" "+\t\t};\n" "+\n" - "+\t\ttimer@b120000 {\n" + "+\t\ttimer at b120000 {\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges;\n" @@ -175,7 +154,7 @@ "+\t\t\treg = <0xb120000 0x1000>;\n" "+\t\t\tclock-frequency = <19200000>;\n" "+\n" - "+\t\t\tframe@b120000 {\n" + "+\t\t\tframe at b120000 {\n" "+\t\t\t\tframe-number = <0>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,\n" "+\t\t\t\t\t <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -183,42 +162,42 @@ "+\t\t\t\t <0xb122000 0x1000>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@b123000 {\n" + "+\t\t\tframe at b123000 {\n" "+\t\t\t\tframe-number = <1>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0xb123000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@b124000 {\n" + "+\t\t\tframe at b124000 {\n" "+\t\t\t\tframe-number = <2>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0xb124000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@b125000 {\n" + "+\t\t\tframe at b125000 {\n" "+\t\t\t\tframe-number = <3>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0xb125000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@b126000 {\n" + "+\t\t\tframe at b126000 {\n" "+\t\t\t\tframe-number = <4>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0xb126000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@b127000 {\n" + "+\t\t\tframe at b127000 {\n" "+\t\t\t\tframe-number = <5>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0xb127000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@b128000 {\n" + "+\t\t\tframe at b128000 {\n" "+\t\t\t\tframe-number = <6>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0xb128000 0x1000>;\n" @@ -226,14 +205,14 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tgcc: gcc@1800000 {\n" + "+\t\tgcc: gcc at 1800000 {\n" "+\t\t\tcompatible = \"qcom,gcc-ipq8074\";\n" "+\t\t\treg = <0x1800000 0x80000>;\n" "+\t\t\t#clock-cells = <0x1>;\n" "+\t\t\t#reset-cells = <0x1>;\n" "+\t\t};\n" "+\n" - "+\t\tblsp1_uart5: serial@78b3000 {\n" + "+\t\tblsp1_uart5: serial at 78b3000 {\n" "+\t\t\tcompatible = \"qcom,msm-uartdm-v1.4\", \"qcom,msm-uartdm\";\n" "+\t\t\treg = <0x78b3000 0x200>;\n" "+\t\t\tinterrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -248,7 +227,7 @@ "+\t\t#address-cells = <0x1>;\n" "+\t\t#size-cells = <0x0>;\n" "+\n" - "+\t\tCPU0: cpu@0 {\n" + "+\t\tCPU0: cpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\treg = <0x0>;\n" @@ -256,7 +235,7 @@ "+\t\t\tenable-method = \"psci\";\n" "+\t\t};\n" "+\n" - "+\t\tCPU1: cpu@1 {\n" + "+\t\tCPU1: cpu at 1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tenable-method = \"psci\";\n" @@ -264,7 +243,7 @@ "+\t\t\tnext-level-cache = <&L2_0>;\n" "+\t\t};\n" "+\n" - "+\t\tCPU2: cpu@2 {\n" + "+\t\tCPU2: cpu at 2 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tenable-method = \"psci\";\n" @@ -272,7 +251,7 @@ "+\t\t\tnext-level-cache = <&L2_0>;\n" "+\t\t};\n" "+\n" - "+\t\tCPU3: cpu@3 {\n" + "+\t\tCPU3: cpu at 3 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tenable-method = \"psci\";\n" @@ -313,4 +292,4 @@ "-- \n" QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -66a4c4f81fdbf1bac2cf653b43459551bc7a41a21a86b1ad11e28b3ab4df9a7e +9fcc7c8ef2176165e25e0cf7c7fc0bb7a25f3dcb548d421aa57d598a75b00563
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