diff for duplicates of <1497022484.28352.105.camel@nxp.com> diff --git a/a/1.txt b/N1/1.txt index 36e9283..5ebdc23 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,13 +1,13 @@ -On Fri, 2017-06-09 at 15:46 +0200, Lothar Waßmann wrote: +On Fri, 2017-06-09 at 15:46 +0200, Lothar Wa?mann wrote: > On Fri, 9 Jun 2017 13:58:15 +0300 Leonard Crestez wrote: > > On Thu, 2017-06-08 at 13:45 -0300, Fabio Estevam wrote: -> > > On Thu, Jun 8, 2017 at 1:26 PM, Leonard Crestez wrote: -> > > > + tempmon: tempmon { -> > > > + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; -> > > > + interrupts = ; -> > > > + fsl,tempmon = <&anatop>; -> > > > + fsl,tempmon-data = <&ocotp>; -> > > > + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; +> > > On Thu, Jun 8, 2017 at 1:26 PM, Leonard Crestez??wrote: +> > > > +???????????????????????tempmon: tempmon { +> > > > +???????????????????????????????compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; +> > > > +???????????????????????????????interrupts = ; +> > > > +???????????????????????????????fsl,tempmon = <&anatop>; +> > > > +???????????????????????????????fsl,tempmon-data = <&ocotp>; +> > > > +???????????????????????????????clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; > > > Does the IMX6UL_CLK_PLL3_USB_OTG clock really control tempmon? Please > > > double check. > > Yes, as far as I can tell the tempmon block uses the 480 Mhz PLL3 clock @@ -16,7 +16,7 @@ On Fri, 2017-06-09 at 15:46 +0200, Lothar Waßmann wrote: > > suffix is descriptive, similar to PLL4_AUDIO and PLL6_ENET. Other non- > > usb components use PLL3 (like UART) but through other gates/dividers. > > -> > Setting this to IMX6UL_CLK_DUMMY will cause temperature reads to fail. +> > Setting this to?IMX6UL_CLK_DUMMY will cause temperature reads to fail. > > Even if PLL3 usually ends up being constantly enabled because of uarts > > this is not true at imx_thermal_probe time (or uarts can be disabled). > > @@ -25,7 +25,7 @@ On Fri, 2017-06-09 at 15:46 +0200, Lothar Waßmann wrote: > I don't think so. OCOTP reads fuse values into shadows registers on chip reset and values seem to be available even if it's specific OCOTP -clock is off. I think that clock is only required for writes or shadow +clock is off. I think that clock is only required for writes or?shadow updates. In theory perhaps tempmon could be made to read ocotp through the imx- diff --git a/a/content_digest b/N1/content_digest index f4a4bb2..8348445 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,32 +3,22 @@ "ref\0CAOMZO5BP4fPyzDmSg+DFLRYh3QMf-8T0gqvnZn6mEMt-QqSgfw@mail.gmail.com\0" "ref\01497005895.28352.88.camel@nxp.com\0" "ref\020170609154638.3b64e6d0@karo-electronics.de\0" - "From\0Leonard Crestez <leonard.crestez@nxp.com>\0" - "Subject\0Re: [PATCH 2/2] ARM: dts: imx6ul: Add imx6ul-tempmon\0" + "From\0leonard.crestez@nxp.com (Leonard Crestez)\0" + "Subject\0[PATCH 2/2] ARM: dts: imx6ul: Add imx6ul-tempmon\0" "Date\0Fri, 9 Jun 2017 18:34:44 +0300\0" - "To\0Lothar Wa\303\237mann <LW@karo-electronics.de>\0" - "Cc\0Fabio Estevam <festevam@gmail.com>" - Bai Ping <ping.bai@nxp.com> - linux-pm@vger.kernel.org <linux-pm@vger.kernel.org> - linux-kernel <linux-kernel@vger.kernel.org> - Eduardo Valentin <edubezval@gmail.com> - Sascha Hauer <kernel@pengutronix.de> - Fabio Estevam <fabio.estevam@nxp.com> - Zhang Rui <rui.zhang@intel.com> - Shawn Guo <shawnguo@kernel.org> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "On Fri, 2017-06-09 at 15:46 +0200, Lothar Wa\303\237mann wrote:\n" + "On Fri, 2017-06-09 at 15:46 +0200, Lothar Wa?mann wrote:\n" "> On Fri, 9 Jun 2017 13:58:15 +0300 Leonard Crestez wrote:\n" "> > On Thu, 2017-06-08 at 13:45 -0300, Fabio Estevam wrote:\n" - "> > > On Thu, Jun 8, 2017 at 1:26 PM, Leonard Crestez\302\240\302\240wrote:\n" - "> > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240tempmon: tempmon {\n" - "> > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240compatible = \"fsl,imx6ul-tempmon\", \"fsl,imx6sx-tempmon\";\n" - "> > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240interrupts = ;\n" - "> > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240fsl,tempmon = <&anatop>;\n" - "> > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240fsl,tempmon-data = <&ocotp>;\n" - "> > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;\n" + "> > > On Thu, Jun 8, 2017 at 1:26 PM, Leonard Crestez??wrote:\n" + "> > > > +???????????????????????tempmon: tempmon {\n" + "> > > > +???????????????????????????????compatible = \"fsl,imx6ul-tempmon\", \"fsl,imx6sx-tempmon\";\n" + "> > > > +???????????????????????????????interrupts = ;\n" + "> > > > +???????????????????????????????fsl,tempmon = <&anatop>;\n" + "> > > > +???????????????????????????????fsl,tempmon-data = <&ocotp>;\n" + "> > > > +???????????????????????????????clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;\n" "> > > Does the IMX6UL_CLK_PLL3_USB_OTG clock really control tempmon? Please\n" "> > > double check.\n" "> > Yes, as far as I can tell the tempmon block uses the 480 Mhz PLL3 clock\n" @@ -37,7 +27,7 @@ "> > suffix is descriptive, similar to PLL4_AUDIO and PLL6_ENET. Other non-\n" "> > usb components use PLL3 (like UART) but through other gates/dividers.\n" "> > \n" - "> > Setting this to\302\240IMX6UL_CLK_DUMMY will cause temperature reads to fail.\n" + "> > Setting this to?IMX6UL_CLK_DUMMY will cause temperature reads to fail.\n" "> > Even if PLL3 usually ends up being constantly enabled because of uarts\n" "> > this is not true at imx_thermal_probe time (or uarts can be disabled).\n" "> > \n" @@ -46,7 +36,7 @@ "> \n" "I don't think so. OCOTP reads fuse values into shadows registers on\n" "chip reset and values seem to be available even if it's specific OCOTP\n" - "clock is off. I think that clock is only required for writes or\302\240shadow\n" + "clock is off. I think that clock is only required for writes or?shadow\n" "updates.\n" "\n" "In theory perhaps tempmon could be made to read ocotp through the imx-\n" @@ -61,4 +51,4 @@ "Regards,\n" Leonard -92baf12ad7748700f4bd35431858dfb62a9a5f29942ae026cb72b0d3344cbfff +25508f5f8fbedc26e34b388dcbe9854d361d87cb6cdd65e3f055a3425f035105
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