diff for duplicates of <1497253225.3086.2.camel@baylibre.com> diff --git a/a/1.txt b/N1/1.txt index 052d5f9..e66c515 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -17,12 +17,12 @@ On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote: > > > all commented out code). > > > The difference between the Meson8 and Meson8b clock gates seem to be: > > > - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, -> > > ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b +> > > CSI_DIG_CLKIN gates which don't seem to be available on Meson8b > > > - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead -> > > ? of "PERIPHS_TOP" (on Meson8b) +> > > of "PERIPHS_TOP" (on Meson8b) > > > - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or -> > > ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL -> > > ? kernel sources) +> > > on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL +> > > kernel sources) > > > None of these gates is added for now, since it's unclear whether these > > > definitions are actually correct (the VCLK2_ENCT gate for example is > > > defined, but only used in some commented block). @@ -38,7 +38,7 @@ On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote: > > > > > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > > > --- -> > > ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +> > > .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 11 > > > +++++++--- > > > > I think you should split the binding documentation and clk changes into @@ -46,8 +46,8 @@ On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote: > > patches. > > > > > - -> > > ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++--- -> > > ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++- +> > > drivers/clk/meson/Kconfig | 6 +++--- +> > > drivers/clk/meson/meson8b.c | 5 ++++- > > > > The change being more platform than clock related, I'd prefer if Kevin or > > Carlo diff --git a/a/content_digest b/N1/content_digest index 0d87c98..ea11165 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,10 +2,22 @@ "ref\020170604183341.21417-2-martin.blumenstingl@googlemail.com\0" "ref\01496606325.3552.16.camel@baylibre.com\0" "ref\0m2lgp19ghu.fsf@baylibre.com\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" + "From\0Jerome Brunet <jbrunet@baylibre.com>\0" + "Subject\0Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" "Date\0Mon, 12 Jun 2017 09:40:25 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Kevin Hilman <khilman@baylibre.com>\0" + "Cc\0Martin Blumenstingl <martin.blumenstingl@googlemail.com>" + narmstrong@baylibre.com + linux-amlogic@lists.infradead.org + linux-clk@vger.kernel.org + mturquette@baylibre.com + sboyd@codeaurora.org + robh+dt@kernel.org + mark.rutland@arm.com + carlo@caione.org + linux@armlinux.org.uk + devicetree@vger.kernel.org + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote:\n" @@ -27,12 +39,12 @@ "> > > all commented out code).\n" "> > > The difference between the Meson8 and Meson8b clock gates seem to be:\n" "> > > - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,\n" - "> > > ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b\n" + "> > > \302\240 CSI_DIG_CLKIN gates which don't seem to be available on Meson8b\n" "> > > - the gate on Meson8 for bit 7 seems to be named \"_1200XXX\" instead\n" - "> > > ? of \"PERIPHS_TOP\" (on Meson8b)\n" + "> > > \302\240 of \"PERIPHS_TOP\" (on Meson8b)\n" "> > > - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or\n" - "> > > ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL\n" - "> > > ? kernel sources)\n" + "> > > \302\240 on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL\n" + "> > > \302\240 kernel sources)\n" "> > > None of these gates is added for now, since it's unclear whether these\n" "> > > definitions are actually correct (the VCLK2_ENCT gate for example is\n" "> > > defined, but only used in some commented block).\n" @@ -48,7 +60,7 @@ "> > > \n" "> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n" "> > > ---\n" - "> > > ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11\n" + "> > > \302\240.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 11\n" "> > > +++++++---\n" "> > \n" "> > I think you should split the binding documentation and clk changes into\n" @@ -56,8 +68,8 @@ "> > patches.\n" "> > \n" "> > > -\n" - "> > > ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---\n" - "> > > ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-\n" + "> > > \302\240drivers/clk/meson/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2406 +++---\n" + "> > > \302\240drivers/clk/meson/meson8b.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2405 ++++-\n" "> > \n" "> > The change being more platform than clock related, I'd prefer if Kevin or\n" "> > Carlo\n" @@ -67,4 +79,4 @@ "\n" Applied to next/drivers with Kevin and Rob's Acks. -5a041455eb54cd402d7dd5e5982790578768be3ed03fee5de9d6cd1aa01aaf02 +744be8c21159b098ef2a3d0746e8c27a7f82d0bb85035fd733d73819e02e820a
diff --git a/a/content_digest b/N2/content_digest index 0d87c98..78c9345 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -5,7 +5,7 @@ "From\0jbrunet@baylibre.com (Jerome Brunet)\0" "Subject\0[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" "Date\0Mon, 12 Jun 2017 09:40:25 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote:\n" @@ -67,4 +67,4 @@ "\n" Applied to next/drivers with Kevin and Rob's Acks. -5a041455eb54cd402d7dd5e5982790578768be3ed03fee5de9d6cd1aa01aaf02 +6f9bb8c23c44e1d2c73fc764799363e027fb402c74ce89bc4efe4f727c28e522
diff --git a/a/1.txt b/N3/1.txt index 052d5f9..23e8d7c 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -1,5 +1,5 @@ On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote: -> Jerome Brunet <jbrunet@baylibre.com> writes: +> Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes: > > > On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote: > > > The clock controller on Meson8, Meson8b and Meson8m2 is very similar @@ -17,12 +17,12 @@ On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote: > > > all commented out code). > > > The difference between the Meson8 and Meson8b clock gates seem to be: > > > - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, -> > > ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b +> > > CSI_DIG_CLKIN gates which don't seem to be available on Meson8b > > > - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead -> > > ? of "PERIPHS_TOP" (on Meson8b) +> > > of "PERIPHS_TOP" (on Meson8b) > > > - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or -> > > ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL -> > > ? kernel sources) +> > > on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL +> > > kernel sources) > > > None of these gates is added for now, since it's unclear whether these > > > definitions are actually correct (the VCLK2_ENCT gate for example is > > > defined, but only used in some commented block). @@ -36,9 +36,9 @@ On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote: > > > None of these VPU clocks are not supported by our mainline meson8b > > > clock driver yet though. > > > -> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> > > > --- -> > > ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +> > > .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 11 > > > +++++++--- > > > > I think you should split the binding documentation and clk changes into @@ -46,13 +46,18 @@ On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote: > > patches. > > > > > - -> > > ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++--- -> > > ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++- +> > > drivers/clk/meson/Kconfig | 6 +++--- +> > > drivers/clk/meson/meson8b.c | 5 ++++- > > > > The change being more platform than clock related, I'd prefer if Kevin or > > Carlo > > ack it before we apply it. > -> Acked-by: Kevin Hilman <khilman@baylibre.com> +> Acked-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> Applied to next/drivers with Kevin and Rob's Acks. + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N3/content_digest index 0d87c98..6913cc7 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -2,14 +2,27 @@ "ref\020170604183341.21417-2-martin.blumenstingl@googlemail.com\0" "ref\01496606325.3552.16.camel@baylibre.com\0" "ref\0m2lgp19ghu.fsf@baylibre.com\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" + "ref\0m2lgp19ghu.fsf-rdvid1DuHRBWk0Htik3J/w@public.gmane.org\0" + "From\0Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Subject\0Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" "Date\0Mon, 12 Jun 2017 09:40:25 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Cc\0Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>" + narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org + linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "On Fri, 2017-06-09 at 11:13 -0700, Kevin Hilman wrote:\n" - "> Jerome Brunet <jbrunet@baylibre.com> writes:\n" + "> Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes:\n" "> \n" "> > On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:\n" "> > > The clock controller on Meson8, Meson8b and Meson8m2 is very similar\n" @@ -27,12 +40,12 @@ "> > > all commented out code).\n" "> > > The difference between the Meson8 and Meson8b clock gates seem to be:\n" "> > > - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,\n" - "> > > ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b\n" + "> > > \302\240 CSI_DIG_CLKIN gates which don't seem to be available on Meson8b\n" "> > > - the gate on Meson8 for bit 7 seems to be named \"_1200XXX\" instead\n" - "> > > ? of \"PERIPHS_TOP\" (on Meson8b)\n" + "> > > \302\240 of \"PERIPHS_TOP\" (on Meson8b)\n" "> > > - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or\n" - "> > > ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL\n" - "> > > ? kernel sources)\n" + "> > > \302\240 on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL\n" + "> > > \302\240 kernel sources)\n" "> > > None of these gates is added for now, since it's unclear whether these\n" "> > > definitions are actually correct (the VCLK2_ENCT gate for example is\n" "> > > defined, but only used in some commented block).\n" @@ -46,9 +59,9 @@ "> > > None of these VPU clocks are not supported by our mainline meson8b\n" "> > > clock driver yet though.\n" "> > > \n" - "> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n" + "> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>\n" "> > > ---\n" - "> > > ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11\n" + "> > > \302\240.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 11\n" "> > > +++++++---\n" "> > \n" "> > I think you should split the binding documentation and clk changes into\n" @@ -56,15 +69,20 @@ "> > patches.\n" "> > \n" "> > > -\n" - "> > > ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---\n" - "> > > ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-\n" + "> > > \302\240drivers/clk/meson/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2406 +++---\n" + "> > > \302\240drivers/clk/meson/meson8b.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2405 ++++-\n" "> > \n" "> > The change being more platform than clock related, I'd prefer if Kevin or\n" "> > Carlo\n" "> > ack it before we apply it.\n" "> \n" - "> Acked-by: Kevin Hilman <khilman@baylibre.com>\n" + "> Acked-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\n" "\n" - Applied to next/drivers with Kevin and Rob's Acks. + "Applied to next/drivers with Kevin and Rob's Acks.\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -5a041455eb54cd402d7dd5e5982790578768be3ed03fee5de9d6cd1aa01aaf02 +a1a04298c80fa2cde645962475b982ff2b4e735456fcae5b756584e3dac44432
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.