diff for duplicates of <1497257685.3086.4.camel@baylibre.com> diff --git a/a/1.txt b/N1/1.txt index 87e155a..c218458 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,7 +2,7 @@ On Sat, 2017-06-10 at 23:57 +0200, Heiner Kallweit wrote: > Add a driver supporting the GPIO interrupt controller on certain > Amlogic meson SoC's. > -> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> +> Signed-off-by: Heiner Kallweit <hkallweit1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > v5: > - changed Kconfig entry based on Neil's suggestion @@ -13,21 +13,21 @@ On Sat, 2017-06-10 at 23:57 +0200, Heiner Kallweit wrote: > v7: > - no changes > --- -> ?drivers/irqchip/Kconfig??????????|???5 + -> ?drivers/irqchip/Makefile?????????|???1 + -> ?drivers/irqchip/irq-meson-gpio.c | 295 +> drivers/irqchip/Kconfig | 5 + +> drivers/irqchip/Makefile | 1 + +> drivers/irqchip/irq-meson-gpio.c | 295 > +++++++++++++++++++++++++++++++++++++++ -> ?3 files changed, 301 insertions(+) -> ?create mode 100644 drivers/irqchip/irq-meson-gpio.c +> 3 files changed, 301 insertions(+) +> create mode 100644 drivers/irqchip/irq-meson-gpio.c > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index 478f8ace..bdc86e14 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -301,3 +301,8 @@ config QCOM_IRQ_COMBINER -> ? help -> ? ??Say yes here to add support for the IRQ combiner devices embedded -> ? ??in Qualcomm Technologies chips. +> help +> Say yes here to add support for the IRQ combiner devices embedded +> in Qualcomm Technologies chips. > + > +config MESON_GPIO_INTC > + bool @@ -39,9 +39,9 @@ On Sat, 2017-06-10 at 23:57 +0200, Heiner Kallweit wrote: > +++ b/drivers/irqchip/Makefile > @@ -76,3 +76,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq- > eznps.o -> ?obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o -> ?obj-$(CONFIG_STM32_EXTI)? += irq-stm32-exti.o -> ?obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o +> obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o +> obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o +> obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o > +obj-$(CONFIG_MESON_GPIO_INTC) += irq-meson-gpio.o > diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson- > gpio.c @@ -54,10 +54,10 @@ On Sat, 2017-06-10 at 23:57 +0200, Heiner Kallweit wrote: > + * Amlogic Meson GPIO IRQ chip driver > + * > + * Copyright (c) 2015 Endless Mobile, Inc. -> + * Author: Carlo Caione <carlo@endlessm.com> +> + * Author: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org> > + * Copyright (c) 2016 BayLibre, SAS. -> + * Author: Jerome Brunet <jbrunet@baylibre.com> -> + * Copyright (c) 2017 Heiner Kallweit <hkallweit1@gmail.com> +> + * Author: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> +> + * Copyright (c) 2017 Heiner Kallweit <hkallweit1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as @@ -171,7 +171,7 @@ Review from october suggested to put this value in DT. > + int shift = 8 * (idx % 4); > + > + regmap_update_bits(md->regmap, reg, 0xff << shift, -> + ???hwirq << shift); +> + hwirq << shift); > +} > + > +static void meson_irq_set_hwirq(struct irq_data *data, unsigned int hwirq) @@ -203,7 +203,7 @@ Review from october suggested to put this value in DT. > + val |= REG_EDGE_POL_LOW(slot); > + > + regmap_update_bits(md->regmap, REG_EDGE_POL, -> + ???REG_EDGE_POL_MASK(slot), val); +> + REG_EDGE_POL_MASK(slot), val); > + > + if (type & IRQ_TYPE_EDGE_BOTH) > + val = IRQ_TYPE_EDGE_RISING; @@ -217,10 +217,10 @@ Review from october suggested to put this value in DT. > +{ > + irq_chip_unmask_parent(data); > + /* -> + ?* An extra bit was added to allow having the same gpio hwirq twice -> + ?* for handling IRQ_TYPE_EDGE_BOTH. Remove this bit to get the -> + ?* gpio hwirq. -> + ?*/ +> + * An extra bit was added to allow having the same gpio hwirq twice +> + * for handling IRQ_TYPE_EDGE_BOTH. Remove this bit to get the +> + * gpio hwirq. +> + */ > + meson_irq_set_hwirq(data, data->hwirq >> 1); Comments from v6 still applies here, and this has nothing to do with the so- @@ -265,7 +265,7 @@ to understand it and trust it, identified corner cases should be covered. > +}; > + > +static int meson_irq_alloc(struct irq_domain *d, unsigned int virq, -> + ???unsigned int nr_irqs, void *data) +> + unsigned int nr_irqs, void *data) > +{ > + struct irq_fwspec parent_fwspec, *fwspec = data; > + struct meson_data *md = d->host_data; @@ -293,7 +293,7 @@ to understand it and trust it, identified corner cases should be covered. > +} > + > +static void meson_irq_free(struct irq_domain *d, unsigned int virq, -> + ???unsigned int nr_irqs) +> + unsigned int nr_irqs) > +{ > + struct meson_data *md = d->host_data; > + @@ -326,14 +326,14 @@ to understand it and trust it, identified corner cases should be covered. > +} > + > +static const struct regmap_config meson_regmap_config = { -> + .reg_bits???????= 32, -> + .reg_stride?????= 4, -> + .val_bits???????= 32, +> + .reg_bits = 32, +> + .reg_stride = 4, +> + .val_bits = 32, > + .max_register = REG_FILTER_SEL, > +}; > + > +static int __init meson_gpio_irq_init(struct device_node *node, -> + ??????struct device_node *parent) +> + struct device_node *parent) > +{ > + struct irq_domain *meson_irq_domain, *parent_domain; > + struct meson_data *md; @@ -371,10 +371,15 @@ to understand it and trust it, identified corner cases should be covered. > + return -ENXIO; > + > + meson_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, -> + ????NUM_GPIO_HWIRQ, node, -> + ????&meson_irq_ops, md); +> + NUM_GPIO_HWIRQ, node, +> + &meson_irq_ops, md); > + return meson_irq_domain ? 0 : -EINVAL; > +} > + > +IRQCHIP_DECLARE(meson_gpio_irq, "amlogic,meson-gpio-intc", > meson_gpio_irq_init); + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 06888f3..fe24123 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,16 +1,29 @@ "ref\05b352c8d-a426-fa73-58b7-0c935979492b@gmail.com\0" "ref\0b33ccc5c-f383-97e7-44e6-d6e1f104e26c@gmail.com\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH v7 1/9] irqchip: add Amlogic Meson GPIO irqchip driver\0" + "ref\0b33ccc5c-f383-97e7-44e6-d6e1f104e26c-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Subject\0Re: [PATCH v7 1/9] irqchip: add Amlogic Meson GPIO irqchip driver\0" "Date\0Mon, 12 Jun 2017 10:54:45 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Heiner Kallweit <hkallweit1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>" + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> + Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org> + Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + " Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Cc\0devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" + linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + " Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" "\00:1\0" "b\0" "On Sat, 2017-06-10 at 23:57 +0200, Heiner Kallweit wrote:\n" "> Add a driver supporting the GPIO interrupt controller on certain\n" "> Amlogic meson SoC's.\n" "> \n" - "> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>\n" + "> Signed-off-by: Heiner Kallweit <hkallweit1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "> ---\n" "> v5:\n" "> - changed Kconfig entry based on Neil's suggestion\n" @@ -21,21 +34,21 @@ "> v7:\n" "> - no changes\n" "> ---\n" - "> ?drivers/irqchip/Kconfig??????????|???5 +\n" - "> ?drivers/irqchip/Makefile?????????|???1 +\n" - "> ?drivers/irqchip/irq-meson-gpio.c | 295\n" + "> \302\240drivers/irqchip/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\240\302\2405 +\n" + "> \302\240drivers/irqchip/Makefile\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\240\302\2401 +\n" + "> \302\240drivers/irqchip/irq-meson-gpio.c | 295\n" "> +++++++++++++++++++++++++++++++++++++++\n" - "> ?3 files changed, 301 insertions(+)\n" - "> ?create mode 100644 drivers/irqchip/irq-meson-gpio.c\n" + "> \302\2403 files changed, 301 insertions(+)\n" + "> \302\240create mode 100644 drivers/irqchip/irq-meson-gpio.c\n" "> \n" "> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig\n" "> index 478f8ace..bdc86e14 100644\n" "> --- a/drivers/irqchip/Kconfig\n" "> +++ b/drivers/irqchip/Kconfig\n" "> @@ -301,3 +301,8 @@ config QCOM_IRQ_COMBINER\n" - "> ?\thelp\n" - "> ?\t??Say yes here to add support for the IRQ combiner devices embedded\n" - "> ?\t??in Qualcomm Technologies chips.\n" + "> \302\240\thelp\n" + "> \302\240\t\302\240\302\240Say yes here to add support for the IRQ combiner devices embedded\n" + "> \302\240\t\302\240\302\240in Qualcomm Technologies chips.\n" "> +\n" "> +config MESON_GPIO_INTC\n" "> +\tbool\n" @@ -47,9 +60,9 @@ "> +++ b/drivers/irqchip/Makefile\n" "> @@ -76,3 +76,4 @@ obj-$(CONFIG_EZNPS_GIC)\t\t\t+= irq-\n" "> eznps.o\n" - "> ?obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-vic.o\n" - "> ?obj-$(CONFIG_STM32_EXTI)?\t\t+= irq-stm32-exti.o\n" - "> ?obj-$(CONFIG_QCOM_IRQ_COMBINER)\t\t+= qcom-irq-combiner.o\n" + "> \302\240obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-vic.o\n" + "> \302\240obj-$(CONFIG_STM32_EXTI)\302\240\t\t+= irq-stm32-exti.o\n" + "> \302\240obj-$(CONFIG_QCOM_IRQ_COMBINER)\t\t+= qcom-irq-combiner.o\n" "> +obj-$(CONFIG_MESON_GPIO_INTC)\t\t+= irq-meson-gpio.o\n" "> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-\n" "> gpio.c\n" @@ -62,10 +75,10 @@ "> + * Amlogic Meson GPIO IRQ chip driver\n" "> + *\n" "> + * Copyright (c) 2015 Endless Mobile, Inc.\n" - "> + * Author: Carlo Caione <carlo@endlessm.com>\n" + "> + * Author: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>\n" "> + * Copyright (c) 2016 BayLibre, SAS.\n" - "> + * Author: Jerome Brunet <jbrunet@baylibre.com>\n" - "> + * Copyright (c) 2017 Heiner Kallweit <hkallweit1@gmail.com>\n" + "> + * Author: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\n" + "> + * Copyright (c) 2017 Heiner Kallweit <hkallweit1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "> + *\n" "> + * This program is free software; you can redistribute it and/or\n" "> + * modify it under the terms of the GNU General Public License as\n" @@ -179,7 +192,7 @@ "> +\tint shift = 8 * (idx % 4);\n" "> +\n" "> +\tregmap_update_bits(md->regmap, reg, 0xff << shift,\n" - "> +\t\t\t???hwirq << shift);\n" + "> +\t\t\t\302\240\302\240\302\240hwirq << shift);\n" "> +}\n" "> +\n" "> +static void meson_irq_set_hwirq(struct irq_data *data, unsigned int hwirq)\n" @@ -211,7 +224,7 @@ "> +\t\tval |= REG_EDGE_POL_LOW(slot);\n" "> +\n" "> +\tregmap_update_bits(md->regmap, REG_EDGE_POL,\n" - "> +\t\t\t???REG_EDGE_POL_MASK(slot), val);\n" + "> +\t\t\t\302\240\302\240\302\240REG_EDGE_POL_MASK(slot), val);\n" "> +\n" "> +\tif (type & IRQ_TYPE_EDGE_BOTH)\n" "> +\t\tval = IRQ_TYPE_EDGE_RISING;\n" @@ -225,10 +238,10 @@ "> +{\n" "> +\tirq_chip_unmask_parent(data);\n" "> +\t/*\n" - "> +\t?* An extra bit was added to allow having the same gpio hwirq twice\n" - "> +\t?* for handling IRQ_TYPE_EDGE_BOTH. Remove this bit to get the\n" - "> +\t?* gpio hwirq.\n" - "> +\t?*/\n" + "> +\t\302\240* An extra bit was added to allow having the same gpio hwirq twice\n" + "> +\t\302\240* for handling IRQ_TYPE_EDGE_BOTH. Remove this bit to get the\n" + "> +\t\302\240* gpio hwirq.\n" + "> +\t\302\240*/\n" "> +\tmeson_irq_set_hwirq(data, data->hwirq >> 1);\n" "\n" "Comments from v6 still applies here, and this has nothing to do with the so-\n" @@ -273,7 +286,7 @@ "> +};\n" "> +\n" "> +static int meson_irq_alloc(struct irq_domain *d, unsigned int virq,\n" - "> +\t\t\t???unsigned int nr_irqs, void *data)\n" + "> +\t\t\t\302\240\302\240\302\240unsigned int nr_irqs, void *data)\n" "> +{\n" "> +\tstruct irq_fwspec parent_fwspec, *fwspec = data;\n" "> +\tstruct meson_data *md = d->host_data;\n" @@ -301,7 +314,7 @@ "> +}\n" "> +\n" "> +static void meson_irq_free(struct irq_domain *d, unsigned int virq,\n" - "> +\t\t\t???unsigned int nr_irqs)\n" + "> +\t\t\t\302\240\302\240\302\240unsigned int nr_irqs)\n" "> +{\n" "> +\tstruct meson_data *md = d->host_data;\n" "> +\n" @@ -334,14 +347,14 @@ "> +}\n" "> +\n" "> +static const struct regmap_config meson_regmap_config = {\n" - "> +\t.reg_bits???????= 32,\n" - "> +\t.reg_stride?????= 4,\n" - "> +\t.val_bits???????= 32,\n" + "> +\t.reg_bits\302\240\302\240\302\240\302\240\302\240\302\240\302\240= 32,\n" + "> +\t.reg_stride\302\240\302\240\302\240\302\240\302\240= 4,\n" + "> +\t.val_bits\302\240\302\240\302\240\302\240\302\240\302\240\302\240= 32,\n" "> +\t.max_register\t= REG_FILTER_SEL,\n" "> +};\n" "> +\n" "> +static int __init meson_gpio_irq_init(struct device_node *node,\n" - "> +\t\t\t\t??????struct device_node *parent)\n" + "> +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240struct device_node *parent)\n" "> +{\n" "> +\tstruct irq_domain *meson_irq_domain, *parent_domain;\n" "> +\tstruct meson_data *md;\n" @@ -379,12 +392,17 @@ "> +\t\treturn -ENXIO;\n" "> +\n" "> +\tmeson_irq_domain = irq_domain_add_hierarchy(parent_domain, 0,\n" - "> +\t\t\t\t\t\t????NUM_GPIO_HWIRQ, node,\n" - "> +\t\t\t\t\t\t????&meson_irq_ops, md);\n" + "> +\t\t\t\t\t\t\302\240\302\240\302\240\302\240NUM_GPIO_HWIRQ, node,\n" + "> +\t\t\t\t\t\t\302\240\302\240\302\240\302\240&meson_irq_ops, md);\n" "> +\treturn meson_irq_domain ? 0 : -EINVAL;\n" "> +}\n" "> +\n" "> +IRQCHIP_DECLARE(meson_gpio_irq, \"amlogic,meson-gpio-intc\",\n" - > meson_gpio_irq_init); + "> meson_gpio_irq_init);\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -0b107f5cfbe1474ef0182d8caa6306c6a848989e5cb7e5c689a73d72171f27af +b00b27adbb04f937c027635e31cee107e9b3a5a95f62fad0ee59d872fa0537e8
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.