diff for duplicates of <1497268028.32422.15.camel@nxp.com> diff --git a/a/1.txt b/N1/1.txt index a7418c4..b05e855 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,20 +1,20 @@ -On Mon, 2017-06-12 at 12:40 +0200, Lothar Waßmann wrote: +On Mon, 2017-06-12 at 12:40 +0200, Lothar Wa?mann wrote: > On Fri, 9 Jun 2017 18:34:44 +0300 Leonard Crestez wrote: > > -> > On Fri, 2017-06-09 at 15:46 +0200, Lothar Waßmann wrote: +> > On Fri, 2017-06-09 at 15:46 +0200, Lothar Wa?mann wrote: > > > > > > On Fri, 9 Jun 2017 13:58:15 +0300 Leonard Crestez wrote: > > > > > > > > On Thu, 2017-06-08 at 13:45 -0300, Fabio Estevam wrote: > > > > > -> > > > > On Thu, Jun 8, 2017 at 1:26 PM, Leonard Crestez wrote: +> > > > > On Thu, Jun 8, 2017 at 1:26 PM, Leonard Crestez??wrote: > > > > > > -> > > > > > + tempmon: tempmon { -> > > > > > + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; -> > > > > > + interrupts = ; -> > > > > > + fsl,tempmon = <&anatop>; -> > > > > > + fsl,tempmon-data = <&ocotp>; -> > > > > > + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; +> > > > > > +???????????????????????tempmon: tempmon { +> > > > > > +???????????????????????????????compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; +> > > > > > +???????????????????????????????interrupts = ; +> > > > > > +???????????????????????????????fsl,tempmon = <&anatop>; +> > > > > > +???????????????????????????????fsl,tempmon-data = <&ocotp>; +> > > > > > +???????????????????????????????clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; > > > > > Does the IMX6UL_CLK_PLL3_USB_OTG clock really control tempmon? Please > > > > > double check. > > > > Yes, as far as I can tell the tempmon block uses the 480 Mhz PLL3 clock @@ -23,7 +23,7 @@ On Mon, 2017-06-12 at 12:40 +0200, Lothar Waßmann wrote: > > > > suffix is descriptive, similar to PLL4_AUDIO and PLL6_ENET. Other non- > > > > usb components use PLL3 (like UART) but through other gates/dividers. > > > > -> > > > Setting this to IMX6UL_CLK_DUMMY will cause temperature reads to fail. +> > > > Setting this to?IMX6UL_CLK_DUMMY will cause temperature reads to fail. > > > > Even if PLL3 usually ends up being constantly enabled because of uarts > > > > this is not true at imx_thermal_probe time (or uarts can be disabled). > > > > @@ -37,24 +37,24 @@ On Mon, 2017-06-12 at 12:40 +0200, Lothar Waßmann wrote: > accessing them. > > > -> > clock is off. I think that clock is only required for writes or shadow +> > clock is off. I think that clock is only required for writes or?shadow > > updates. > > > Sometimes it helps to read the Reference Manual or take hardware and try > it out. The i.MX6(Q|UL) Reference Manual lists the required clocks as: -> Table 35-1. OCOTP Clocks -> Clock name Clock Root Description -> ipg_clk ipg_clk_root Peripheral clock -> ipg_clk_s ipg_clk_root Peripheral access clock +> ??????????????????????????????????Table 35-1. OCOTP Clocks +> Clock name???????Clock Root???????????Description +> ipg_clk??????????ipg_clk_root?????????Peripheral clock +> ipg_clk_s????????ipg_clk_root?????????Peripheral access clock > > and Table 18-3. "System Clocks, Gating, and Override (continued)" > for i.MX6UL shows: -> OCOTP IPG_CLK IPG_CLK_ROOT CCGR2[CG6] (IIM_CLK_ENABLE) -> IPG_CLK_S IPG_CLK_ROOT CCGR2[CG6] (IIM_CLK_ENABLE) +> OCOTP IPG_CLK???IPG_CLK_ROOT CCGR2[CG6] (IIM_CLK_ENABLE) +> ??????IPG_CLK_S IPG_CLK_ROOT CCGR2[CG6] (IIM_CLK_ENABLE) > > while the same table for i.MX6Q shows: -> OCOTP ipg_clk ipg_clk_root CCGR2[CG6] (iim_clk_enable) -> ipg_clk_s ipg_clk_root +> OCOTP ipg_clk???ipg_clk_root CCGR2[CG6] (iim_clk_enable) +> ??????ipg_clk_s ipg_clk_root > > with a blank entry in the "Clock Gating" column for the access clock. > So, for i.MX6Q there is no clock enable necessary for the access clock, @@ -64,7 +64,7 @@ On Mon, 2017-06-12 at 12:40 +0200, Lothar Waßmann wrote: > with the OCOTP clock disabled (which immediately hangs the processor). I did check this on real hardware and it seems to work. Printing the -values read from OCOTP inside imx_get_sensor_data displays what looks +values read from OCOTP inside?imx_get_sensor_data displays what looks like valid data. However it seems that this might be accidental, it just happens that diff --git a/a/content_digest b/N1/content_digest index 3c7c10b..916de71 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,39 +5,29 @@ "ref\020170609154638.3b64e6d0@karo-electronics.de\0" "ref\01497022484.28352.105.camel@nxp.com\0" "ref\020170612124029.1643469d@karo-electronics.de\0" - "From\0Leonard Crestez <leonard.crestez@nxp.com>\0" - "Subject\0Re: [PATCH 2/2] ARM: dts: imx6ul: Add imx6ul-tempmon\0" + "From\0leonard.crestez@nxp.com (Leonard Crestez)\0" + "Subject\0[PATCH 2/2] ARM: dts: imx6ul: Add imx6ul-tempmon\0" "Date\0Mon, 12 Jun 2017 14:47:08 +0300\0" - "To\0Lothar Wa\303\237mann <LW@karo-electronics.de>\0" - "Cc\0Bai Ping <ping.bai@nxp.com>" - linux-pm@vger.kernel.org <linux-pm@vger.kernel.org> - Shawn Guo <shawnguo@kernel.org> - linux-kernel <linux-kernel@vger.kernel.org> - Eduardo Valentin <edubezval@gmail.com> - Sascha Hauer <kernel@pengutronix.de> - Fabio Estevam <fabio.estevam@nxp.com> - Zhang Rui <rui.zhang@intel.com> - Fabio Estevam <festevam@gmail.com> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "On Mon, 2017-06-12 at 12:40 +0200, Lothar Wa\303\237mann wrote:\n" + "On Mon, 2017-06-12 at 12:40 +0200, Lothar Wa?mann wrote:\n" "> On Fri, 9 Jun 2017 18:34:44 +0300 Leonard Crestez wrote:\n" "> > \n" - "> > On Fri, 2017-06-09 at 15:46 +0200, Lothar Wa\303\237mann wrote:\n" + "> > On Fri, 2017-06-09 at 15:46 +0200, Lothar Wa?mann wrote:\n" "> > > \n" "> > > On Fri, 9 Jun 2017 13:58:15 +0300 Leonard Crestez wrote:\n" "> > > > \n" "> > > > On Thu, 2017-06-08 at 13:45 -0300, Fabio Estevam wrote:\n" "> > > > > \n" - "> > > > > On Thu, Jun 8, 2017 at 1:26 PM, Leonard Crestez\302\240\302\240wrote:\n" + "> > > > > On Thu, Jun 8, 2017 at 1:26 PM, Leonard Crestez??wrote:\n" "> > > > > > \n" - "> > > > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240tempmon: tempmon {\n" - "> > > > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240compatible = \"fsl,imx6ul-tempmon\", \"fsl,imx6sx-tempmon\";\n" - "> > > > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240interrupts = ;\n" - "> > > > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240fsl,tempmon = <&anatop>;\n" - "> > > > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240fsl,tempmon-data = <&ocotp>;\n" - "> > > > > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;\n" + "> > > > > > +???????????????????????tempmon: tempmon {\n" + "> > > > > > +???????????????????????????????compatible = \"fsl,imx6ul-tempmon\", \"fsl,imx6sx-tempmon\";\n" + "> > > > > > +???????????????????????????????interrupts = ;\n" + "> > > > > > +???????????????????????????????fsl,tempmon = <&anatop>;\n" + "> > > > > > +???????????????????????????????fsl,tempmon-data = <&ocotp>;\n" + "> > > > > > +???????????????????????????????clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;\n" "> > > > > Does the IMX6UL_CLK_PLL3_USB_OTG clock really control tempmon? Please\n" "> > > > > double check.\n" "> > > > Yes, as far as I can tell the tempmon block uses the 480 Mhz PLL3 clock\n" @@ -46,7 +36,7 @@ "> > > > suffix is descriptive, similar to PLL4_AUDIO and PLL6_ENET. Other non-\n" "> > > > usb components use PLL3 (like UART) but through other gates/dividers.\n" "> > > > \n" - "> > > > Setting this to\302\240IMX6UL_CLK_DUMMY will cause temperature reads to fail.\n" + "> > > > Setting this to?IMX6UL_CLK_DUMMY will cause temperature reads to fail.\n" "> > > > Even if PLL3 usually ends up being constantly enabled because of uarts\n" "> > > > this is not true at imx_thermal_probe time (or uarts can be disabled).\n" "> > > > \n" @@ -60,24 +50,24 @@ "> accessing them.\n" "> \n" "> > \n" - "> > clock is off. I think that clock is only required for writes or\302\240shadow\n" + "> > clock is off. I think that clock is only required for writes or?shadow\n" "> > updates.\n" "> > \n" "> Sometimes it helps to read the Reference Manual or take hardware and try\n" "> it out. The i.MX6(Q|UL) Reference Manual lists the required clocks as:\n" - "> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240Table 35-1. OCOTP Clocks\n" - "> Clock name\302\240\302\240\302\240\302\240\302\240\302\240\302\240Clock Root\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240Description\n" - "> ipg_clk\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240ipg_clk_root\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240Peripheral clock\n" - "> ipg_clk_s\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240ipg_clk_root\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240Peripheral access clock\n" + "> ??????????????????????????????????Table 35-1. OCOTP Clocks\n" + "> Clock name???????Clock Root???????????Description\n" + "> ipg_clk??????????ipg_clk_root?????????Peripheral clock\n" + "> ipg_clk_s????????ipg_clk_root?????????Peripheral access clock\n" "> \n" "> and Table 18-3. \"System Clocks, Gating, and Override (continued)\"\n" "> for i.MX6UL shows:\n" - "> OCOTP IPG_CLK\302\240\302\240\302\240IPG_CLK_ROOT CCGR2[CG6] (IIM_CLK_ENABLE)\n" - "> \302\240\302\240\302\240\302\240\302\240\302\240IPG_CLK_S IPG_CLK_ROOT CCGR2[CG6] (IIM_CLK_ENABLE)\n" + "> OCOTP IPG_CLK???IPG_CLK_ROOT CCGR2[CG6] (IIM_CLK_ENABLE)\n" + "> ??????IPG_CLK_S IPG_CLK_ROOT CCGR2[CG6] (IIM_CLK_ENABLE)\n" "> \n" "> while the same table for i.MX6Q shows:\n" - "> OCOTP ipg_clk\302\240\302\240\302\240ipg_clk_root CCGR2[CG6] (iim_clk_enable)\n" - "> \302\240\302\240\302\240\302\240\302\240\302\240ipg_clk_s ipg_clk_root\n" + "> OCOTP ipg_clk???ipg_clk_root CCGR2[CG6] (iim_clk_enable)\n" + "> ??????ipg_clk_s ipg_clk_root\n" "> \n" "> with a blank entry in the \"Clock Gating\" column for the access clock.\n" "> So, for i.MX6Q there is no clock enable necessary for the access clock,\n" @@ -87,7 +77,7 @@ "> with the OCOTP clock disabled (which immediately hangs the processor).\n" "\n" "I did check this on real hardware and it seems to work. Printing the\n" - "values read from OCOTP inside\302\240imx_get_sensor_data displays what looks\n" + "values read from OCOTP inside?imx_get_sensor_data displays what looks\n" "like valid data.\n" "\n" "However it seems that this might be accidental, it just happens that\n" @@ -100,4 +90,4 @@ "Regards,\n" Leonard -f8f2aeb670230b73b540f6dde3bfbda4e55f05df554d3f1a2ae04bd1654fad5f +84306f28cf6931400119a8d57a707fe601dce54bd732a2b4e38e0f62d069352e
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