From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Lankhorst, Maarten" Subject: Re: [PATCH 6/6] drm/i915/gen10: Calculate and enable transition WM Date: Tue, 13 Jun 2017 09:29:51 +0000 Message-ID: <1497346189.4965.1.camel@intel.com> References: <20170613060450.16094-1-mahesh1.kumar@intel.com> <20170613060450.16094-7-mahesh1.kumar@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0502381135==" Return-path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94A386E27D for ; Tue, 13 Jun 2017 09:29:53 +0000 (UTC) In-Reply-To: <20170613060450.16094-7-mahesh1.kumar@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "intel-gfx@lists.freedesktop.org" , "Kumar, Mahesh1" Cc: "Zanoni, Paulo R" List-Id: intel-gfx@lists.freedesktop.org --===============0502381135== Content-Language: en-US Content-Type: multipart/signed; micalg=sha-1; protocol="application/x-pkcs7-signature"; boundary="=-4O/9rKtG9p8ygeHKCKc1" --=-4O/9rKtG9p8ygeHKCKc1 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hey, Mahesh Kumar schreef op di 13-06-2017 om 11:34 [+0530]: > GEN > 9 require transition WM to be programmed if IPC is enabled. > This patch calculates & enable transition WM for supported platforms. > If transition WM is enabled, Plane read requests are sent at high > priority until filling above the transition watermark, then the > requests are sent at lower priority until dropping below the level-0 > WM. > The lower priority requests allow other memory clients to have better > memory access. >=20 > transition minimum is the minimum amount needed for trans_wm to work > to > ensure=C2=A0=C2=A0the demote does not happen before enough data has been = read > to > meet the level 0 watermark requirements. >=20 > transition amount is configurable value. Higher values will > tend to cause longer periods of high priority reads followed by > longer > periods of lower priority reads. Tuning to lower values will tend to > cause shorter periods of high and lower priority reads. >=20 > Keeping transition amount to 0 in this patch. > Signed-off-by: Mahesh Kumar > --- > =C2=A0drivers/gpu/drm/i915/intel_pm.c | 51 > ++++++++++++++++++++++++++++++++++++++--- > =C2=A01 file changed, 48 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index 10ec2660acd7..6b951aa14840 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4163,6 +4163,15 @@ skl_enable_plane_wm_levels(const struct > drm_i915_private *dev_priv, > =C2=A0 level_wm->plane_en =3D true; > =C2=A0 } > =C2=A0 } > + > + /* > + =C2=A0* Unsupported GEN will have plane_res_b =3D 0 & transition WM > for > + =C2=A0* them will get disabled here. > + =C2=A0*/ > + if (wm->trans_wm.plane_res_b && wm->trans_wm.plane_res_b < > plane_ddb) > + wm->trans_wm.plane_en =3D true; > + else > + wm->trans_wm.plane_en =3D false; > =C2=A0} > =C2=A0 > =C2=A0static int > @@ -4639,13 +4648,48 @@ skl_compute_linetime_wm(struct > intel_crtc_state *cstate) > =C2=A0} > =C2=A0 > =C2=A0static void skl_compute_transition_wm(struct intel_crtc_state > *cstate, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0struct skl_wm_params *wp, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0struct skl_wm_level *wm_l0, > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0struct skl_wm_level *trans_= wm > /* out */) > =C2=A0{ > + struct drm_device *dev =3D cstate->base.crtc->dev; > + const struct drm_i915_private *dev_priv =3D to_i915(dev); > + uint16_t trans_min, trans_y_tile_min; > + uint16_t trans_amount =3D 0; /* This is configurable amount */ > + uint16_t trans_offset_b, res_blocks; > + > =C2=A0 if (!cstate->base.active) > =C2=A0 return; > - /* Until we know more, just disable transition WMs */ > - trans_wm->plane_en =3D false; > + /* Transition WM are not recommended by HW team for GEN9 */ > + if (INTEL_GEN(dev_priv) <=3D 9) > + return; > + > + /* Transition WM don't have any impact if ipc is disabled */ > + if (!dev_priv->ipc_enabled) > + return; ipc_enabled is never set, so this patch on its own doesn't do much. :) Otherwise series looks good, I didn't check the math on this patch, but the series doesn't regress KBL. For patch 3 and 4: Reviewed-by: Maarten Lankhorst For patch 5 and 6: Acked-by: Maarten Lankhorst > + if (INTEL_GEN(dev_priv) >=3D 10) > + trans_min =3D 4; > + > + trans_offset_b =3D trans_min + trans_amount; > + trans_y_tile_min =3D (uint16_t) mul_round_up_u32_fixed16(2, > + wp- > >y_tile_minimum); > + > + if (wp->y_tiled) { > + res_blocks =3D max(wm_l0->plane_res_b, > trans_y_tile_min) + > + trans_offset_b; > + } else { > + res_blocks =3D wm_l0->plane_res_b + trans_offset_b; > + } > + > + res_blocks +=3D 1; > + > + /* WA BUG:1938466 add one block for non y-tile planes */ > + if (!wp->y_tiled && IS_CNL_REVID(dev_priv, CNL_REVID_A0, > CNL_REVID_A0)) > + res_blocks +=3D 1; > + > + trans_wm->plane_res_b =3D res_blocks; > =C2=A0} > =C2=A0 > =C2=A0static int skl_build_pipe_wm(struct intel_crtc_state *cstate, > @@ -4684,7 +4728,8 @@ static int skl_build_pipe_wm(struct > intel_crtc_state *cstate, > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0&wm_params, wm); > =C2=A0 if (ret) > =C2=A0 return ret; > - skl_compute_transition_wm(cstate, &wm->trans_wm); > + skl_compute_transition_wm(cstate, &wm_params, &wm- > >wm[0], > + =C2=A0=C2=A0&wm->trans_wm); > =C2=A0 } > =C2=A0 pipe_wm->linetime =3D skl_compute_linetime_wm(cstate); > =C2=A0 --=-4O/9rKtG9p8ygeHKCKc1 Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExCzAJBgUrDgMCGgUAMIAGCSqGSIb3DQEHAQAAoIIKfTCCBOsw ggPToAMCAQICEDabxALowUBS+21KC0JI8fcwDQYJKoZIhvcNAQEFBQAwbzELMAkGA1UEBhMCU0Ux FDASBgNVBAoTC0FkZFRydXN0IEFCMSYwJAYDVQQLEx1BZGRUcnVzdCBFeHRlcm5hbCBUVFAgTmV0 d29yazEiMCAGA1UEAxMZQWRkVHJ1c3QgRXh0ZXJuYWwgQ0EgUm9vdDAeFw0xMzEyMTEwMDAwMDBa Fw0yMDA1MzAxMDQ4MzhaMHkxCzAJBgNVBAYTAlVTMQswCQYDVQQIEwJDQTEUMBIGA1UEBxMLU2Fu dGEgQ2xhcmExGjAYBgNVBAoTEUludGVsIENvcnBvcmF0aW9uMSswKQYDVQQDEyJJbnRlbCBFeHRl cm5hbCBCYXNpYyBJc3N1aW5nIENBIDRCMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA yzuW/y/g0bznz8BD48M94luFzqHaqY9yGN9H/W0J7hOVBpl0rTQJ6kZ7z7hyDb9kf2UW4ZU25alC i+q5m6NwHg+z9pcN7bQ84SSBueaYF7cXlAg7z3XyZbzSEYP7raeuWRf5fYvYzq8/uI7VNR8o/43w PtDP10YDdO/0J5xrHxnC/9/aU+wTFSVsPqxsd7C58mnu7G4VRJ0n9PG4SfmYNC0h/5fLWuOWhxAv 6MuiK7MmvTPHLMclULgJqVSqG1MbBs0FbzoRHne4Cx0w6rtzPTrzo+bTRqhruaU18lQkzBk6OnyJ UthtaDQIlfyGy2IlZ5F6QEyjItbdKcHHdjBX8wIDAQABo4IBdzCCAXMwHwYDVR0jBBgwFoAUrb2Y ejS0Jvf6xCZU7wO94CTLVBowHQYDVR0OBBYEFNpBI5xaj3GvV4M+INPjZdsMywvbMA4GA1UdDwEB /wQEAwIBhjASBgNVHRMBAf8ECDAGAQH/AgEAMDYGA1UdJQQvMC0GCCsGAQUFBwMEBgorBgEEAYI3 CgMEBgorBgEEAYI3CgMMBgkrBgEEAYI3FQUwFwYDVR0gBBAwDjAMBgoqhkiG+E0BBQFpMEkGA1Ud HwRCMEAwPqA8oDqGOGh0dHA6Ly9jcmwudHJ1c3QtcHJvdmlkZXIuY29tL0FkZFRydXN0RXh0ZXJu YWxDQVJvb3QuY3JsMDoGCCsGAQUFBwEBBC4wLDAqBggrBgEFBQcwAYYeaHR0cDovL29jc3AudHJ1 c3QtcHJvdmlkZXIuY29tMDUGA1UdHgQuMCygKjALgQlpbnRlbC5jb20wG6AZBgorBgEEAYI3FAID oAsMCWludGVsLmNvbTANBgkqhkiG9w0BAQUFAAOCAQEAp9XGgH85hk/3IuN8F4nrFd24MAoau7Uq M/of09XtyYg2dV0TIPqtxPZw4813r78WwsGIbvtO8VQ18dNktIxaq6+ym2zebqDh0z6Bvo63jKE/ HMj8oNV3ovnuo+7rGpCppcda4iVBG2CetB3WXbUVr82EzECN+wxmC4H9Rup+gn+t+qeBTaXulQfV TYOvZ0eZPO+DyC2pVv5q5+xHljyUsVqpzsw89utuO8ZYaMsQGBRuFGOncRLEOhCtehy5B5aCI571 i4dDAv9LPODrEzm3PBfrNhlp8C0skak15VXWFzNuHd00AsxXxWSUT4TG8RiAH61Ua5GXsP1BIZwl 4WjK8DCCBYowggRyoAMCAQICEzMAADKN2wraLg2L7TkAAAAAMo0wDQYJKoZIhvcNAQEFBQAweTEL MAkGA1UEBhMCVVMxCzAJBgNVBAgTAkNBMRQwEgYDVQQHEwtTYW50YSBDbGFyYTEaMBgGA1UEChMR SW50ZWwgQ29ycG9yYXRpb24xKzApBgNVBAMTIkludGVsIEV4dGVybmFsIEJhc2ljIElzc3Vpbmcg Q0EgNEIwHhcNMTcwMTI0MTQyOTM1WhcNMTgwMTE5MTQyOTM1WjBJMRswGQYDVQQDExJMYW5raG9y c3QsIE1hYXJ0ZW4xKjAoBgkqhkiG9w0BCQEWG21hYXJ0ZW4ubGFua2hvcnN0QGludGVsLmNvbTCC ASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAONfR6BaGMj7h+KRpuIsoqZl3aDEI2hkJAhB osso6S9RNBCrzWi2I1LcpalFdHhDm/GXbFyX3lFkzp66aIv3vdzSktoo6Bze3A30l50hUzouAUdF JX0UiBAKsW8koT2flSRb78s3kYnJhVCSpaYxyKEB4PqNPGg1V5kA2Dar+jeoZtbl1jLbs/krLEW4 gc4OmzzkRo+jF2IJm5fL2S7fxCD1ZOYuaJSgXZjpWspJghtOw/ucsIe15Ub3rAyKA6WfyeZRTpKv 4QqKvoZ8s1FZkSjyNoItRMG8ry1ynpPH0uVQtrTqs59DSMQjTLRVAylj6AoVPSGdTFI404Gf7U/V RbsCAwEAAaOCAjkwggI1MB0GA1UdDgQWBBRgVzvXIeZkmvUcHidu2JGZ7lucnzAfBgNVHSMEGDAW gBTaQSOcWo9xr1eDPiDT42XbDMsL2zBlBgNVHR8EXjBcMFqgWKBWhlRodHRwOi8vd3d3LmludGVs LmNvbS9yZXBvc2l0b3J5L0NSTC9JbnRlbCUyMEV4dGVybmFsJTIwQmFzaWMlMjBJc3N1aW5nJTIw Q0ElMjA0Qi5jcmwwgZ8GCCsGAQUFBwEBBIGSMIGPMCIGCCsGAQUFBzABhhZodHRwOi8vb2NzcC5p bnRlbC5jb20vMGkGCCsGAQUFBzAChl1odHRwOi8vd3d3LmludGVsLmNvbS9yZXBvc2l0b3J5L2Nl cnRpZmljYXRlcy9JbnRlbCUyMEV4dGVybmFsJTIwQmFzaWMlMjBJc3N1aW5nJTIwQ0ElMjA0Qi5j cnQwCwYDVR0PBAQDAgeAMDwGCSsGAQQBgjcVBwQvMC0GJSsGAQQBgjcVCIbDjHWEmeVRg/2BKIWO n1OCkcAJZ4HevTmV8EMCAWQCAQkwHwYDVR0lBBgwFgYIKwYBBQUHAwQGCisGAQQBgjcKAwwwKQYJ KwYBBAGCNxUKBBwwGjAKBggrBgEFBQcDBDAMBgorBgEEAYI3CgMMMFMGA1UdEQRMMEqgKwYKKwYB BAGCNxQCA6AdDBttYWFydGVuLmxhbmtob3JzdEBpbnRlbC5jb22BG21hYXJ0ZW4ubGFua2hvcnN0 QGludGVsLmNvbTANBgkqhkiG9w0BAQUFAAOCAQEAOK0npk5+7PZnWtxZ3/GAl4/z22WrHQefYKUI +85U8BTTseVpsWjEg3DQgvTJ+a3q01iR4tEXfmrdQ9mD1d9AU41AIBVK0pXsEQc52hzBJ+xsT/en 5mixv04VAZHB6ZsHbAohXk16XiDW650AIdNPStJKWVQgkreWpIRQjZ0KJ9zJpiSeJjJYvjt3M5Q1 GCnYyh9VpKocvnsu+O+Rz9IJfd0VIVob6/nqd/nEvZZZhxuexzTZefxSs6+5rnkBFG9inVMMhsvP VHumop5vbakXSunxIdJLXGij3hhjk9NnYc5/yHI/qzl4U5CHOHrxcQN1eg4I7x5wpCFQgG7F2t2x rDGCAhcwggITAgEBMIGQMHkxCzAJBgNVBAYTAlVTMQswCQYDVQQIEwJDQTEUMBIGA1UEBxMLU2Fu dGEgQ2xhcmExGjAYBgNVBAoTEUludGVsIENvcnBvcmF0aW9uMSswKQYDVQQDEyJJbnRlbCBFeHRl cm5hbCBCYXNpYyBJc3N1aW5nIENBIDRCAhMzAAAyjdsK2i4Ni+05AAAAADKNMAkGBSsOAwIaBQCg XTAYBgkqhkiG9w0BCQMxCwYJKoZIhvcNAQcBMBwGCSqGSIb3DQEJBTEPFw0xNzA2MTMwOTI5NDla MCMGCSqGSIb3DQEJBDEWBBTj0HjM5KXpeKNsQI3FbvdzcsbQAjANBgkqhkiG9w0BAQEFAASCAQBq lUdjyrRIQqdBnIEGE2ZgzjjF2YFlEbbDgBLGfOhhEiD/v7hmknEDPQSuGvU0ZLFREXIjV7rfQst5 dTM5ZVZlR6Gd9zLCEwv268E/V49ubKp/L+EETKdOuCerhKf+d8zUMrtU5Mr5ioBHcPnFmzAAL1Ag qfLM2Ilv5p4ElSEZjkwksgbJ1yW7/oE4bn5eLEmXcCZEhBgQz1rQRTKpS2TU+pacYBh2zfcMsk99 1ZaFMjy6z3i2UxAgZ1DgEypIab96bMzov1CemojtRzhuyupg9OHiXk7sEhgRQ16fwIeoP7C0k909 0Fh6NGGNfv8isR2WZaTMNm27Jbgw23MBppBvAAAAAAAA --=-4O/9rKtG9p8ygeHKCKc1-- --===============0502381135== Content-Type: text/plain; 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