From: "Péter Bittner" <bittner@lesswire.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] U-boot Memory configure
Date: Thu, 15 Jun 2017 15:31:21 +0200 [thread overview]
Message-ID: <1497533481.16491.11.camel@lesswire.com> (raw)
Hi all,
I have a problem and i can't solve it.
I have a costume IMX6 board. I want to make new memory configure file.
I found this script: I.MX6DQSDL DDR3 Script Aid V0.10 and i set
everything which need. It generated init script for the calibration.
It's worked and didn't get any error.
Then i modified this script for uboot memory config file and changed
calibration data. But when i tried flash the board then Uboot don't
start.
this is the Uboot config file:
IMAGE_VERSION 2
BOOT_FROM sd
DATA 4 0x020c4068 0x00003fff
DATA 4 0x020c406c 0x00f0fc00
DATA 4 0x020c4070 0x00fff000
DATA 4 0x020c4074 0x3ff00000
DATA 4 0x020c4078 0xff00f300
DATA 4 0x020c407c 0x0f0000c3
DATA 4 0x020c4080 0x000003ff
DATA 4 0x020e0798 0x000C0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
DATA 4 0x020e0588 0x00000018 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
DATA 4 0x020e0594 0x00000018 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 -
DSE can be configured using Group Control Register:
IOMUXC_SW_PAD_CTL_GRP_CTLDS
DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4 0x020e05a8 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
DATA 4 0x020e05b0 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
DATA 4 0x020e0524 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
DATA 4 0x020e051c 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
DATA 4 0x020e0518 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
DATA 4 0x020e050c 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
DATA 4 0x020e05b8 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
DATA 4 0x020e05c0 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
DATA 4 0x020e0534 0x00018200 //
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10)
DATA 4 0x020e0538 0x00008000 //
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00)
DATA 4 0x020e053c 0x00018200 //
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10)
DATA 4 0x020e0540 0x00018200 //
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10)
DATA 4 0x020e0544 0x00018200 //
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10)
DATA 4 0x020e0548 0x00018200 //
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10)
DATA 4 0x020e054c 0x00018200 //
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10)
DATA 4 0x020e0550 0x00018200 //
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10)
DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4 0x020e0784 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4 0x020e0788 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4 0x020e0794 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B2DS
DATA 4 0x020e079c 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B3DS
DATA 4 0x020e07a0 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B4DS
DATA 4 0x020e07a4 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B5DS
DATA 4 0x020e07a8 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B6DS
DATA 4 0x020e0748 0x00000028 // IOMUXC_SW_PAD_CTL_GRP_B7DS
DATA 4 0x020e05ac 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4 0x020e05b4 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
DATA 4 0x020e0528 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
DATA 4 0x020e0520 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
DATA 4 0x020e0514 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
DATA 4 0x020e0510 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
DATA 4 0x020e05bc 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
DATA 4 0x020e05c4 0x00000028 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
DATA 4 0x021b001c 0x00008000 //MMDC0_MDSCR, set the Configuration
request bit during MMDC set up
DATA 4 0x021b0800 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both
one-time & periodic HW ZQ calibration.
DATA 4 0x021b080c 0x000D000D
DATA 4 0x021b0810 0x00150011
DATA 4 0x021b480c 0x00060015
DATA 4 0x021b4810 0x00000013
DATA 4 0x021b083c 0x0310031C // MPDGCTRL0 PHY0
DATA 4 0x021b0840 0x03080270 // MPDGCTRL1 PHY0
DATA 4 0x021b483c 0x03080320 // MPDGCTRL0 PHY1
DATA 4 0x021b4840 0x030C024C // MPDGCTRL1 PHY1
DATA 4 0x021b0848 0x42323A3A // MPRDDLCTL PHY0
DATA 4 0x021b4848 0x3C323044 // MPRDDLCTL PHY1
DATA 4 0x021b0850 0x30363832 // MPWRDLCTL PHY0
DATA 4 0x021b4850 0x3E2E4236 // MPWRDLCTL PHY1
DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
DATA 4 0x021b08c0 0x24912489 // fine tune SDCLK duty cyc to low -
seen to improve measured duty cycle of i.mx6
DATA 4 0x021b48c0 0x24914452
DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
DATA 4 0x021b0004 0x00020036 // MMDC0_MDPDC
DATA 4 0x021b0008 0x09444040 // MMDC0_MDOTC
DATA 4 0x021b000c 0x898E7955 // MMDC0_MDCFG0
DATA 4 0x021b0010 0xFF328F64 // MMDC0_MDCFG1
DATA 4 0x021b0014 0x01FF00DB // MMDC0_MDCFG2
DATA 4 0x021b0018 0x00011740 // MMDC0_MDMISC
DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration
request bit during MMDC set up
DATA 4 0x021b002c 0x000026D2 // MMDC0_MDRWD
DATA 4 0x021b0030 0x008E1023 // MMDC0_MDOR
DATA 4 0x021b0040 0x00000047 // Chan0 CS0_END
DATA 4 0x021b0400 0x14420000 // adopt bypass
DATA 4 0x021b0000 0x841A0000 // MMDC0_MDCTL
DATA 4 0x021b0890 0x00400c58 //ZQ Offset
DATA 4 0x00bb0008 0x00000000 // GPV0_S_A_0_DDRCONF
DATA 4 0x00bb000c 0x2891E41A // GPV0_S_A_0_DDRTIMING accorindt to
MMDC0_MDCFG0/1/2
DATA 4 0x00bb0038 0x00000564 // GPV0_S_A_0_Activate
DATA 4 0x00bb0014 0x00000040 // Read latency
DATA 4 0x00bb0028 0x00000020 // Aging control for
IPU1/PRE0/PRE3
DATA 4 0x00bb002c 0x00000020 // Aging control for
IPU2/PRE1/PRE2
DATA 4 0x021b001c 0x02088032 // MMDC0_MDSCR, MR2 write, CS0
DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR, MR3 write, CS0
DATA 4 0x021b001c 0x00408031 // MMDC0_MDSCR, MR1 write, CS0
DATA 4 0x021b001c 0x19408030 // MMDC0_MDSCR, MR0write, CS0
DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR, ZQ calibration
command sent to device on CS0
DATA 4 0x021b0020 0x00007800 // MMDC0_MDREF
DATA 4 0x021b0818 0x00011117 // DDR_PHY_P0_MPODTCTRL
DATA 4 0x021b4818 0x00011117 // DDR_PHY_P1_MPODTCTRL
DATA 4 0x021b0004 0x00025576 // MMDC0_MDPDC now SDCTL power down
enabled
DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down
enabled, MMDC will enter automatically to self-refresh while the number
of idle cycle reached.
DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register
(especially the configuration bit as initialization is complete)
This is the calibration script
//===================================================================
==========
//init script for i.Mx6Q DDR3
//=============================================================================
// Revision History
// v01
//=============================================================================
wait = on
//=============================================================================
// Disable
WDOG
//=============================================================================
setmem /16
0x020bc000 =
0x30
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
setmem /32
0x020c4068 =
0xffffffff
setmem /32
0x020c406c =
0xffffffff
setmem /32
0x020c4070 =
0xffffffff
setmem /32
0x020c4074 =
0xffffffff
setmem /32
0x020c4078 =
0xffffffff
setmem /32
0x020c407c =
0xffffffff
setmem /32
0x020c4080 =
0xffffffff
setmem /32
0x020c4084 =
0xffffffff
//=============================================================================
// IOMUX
//=============================================================================
//DDR IO TYPE:
setmem /32
0x020e0798 =
0x000C0000
// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
setmem /32
0x020e0758 =
0x00000000
// IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
setmem /32
0x020e0588 =
0x00000018
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
setmem /32
0x020e0594 =
0x00000018
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
//ADDRESS:
setmem /32
0x020e056c =
0x00000030
// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
setmem /32
0x020e0578 =
0x00000030
// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
setmem /32
0x020e074c =
0x00000030
// IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
setmem /32
0x020e057c =
0x00000030
// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
setmem /32
0x020e058c =
0x00000000
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
setmem /32
0x020e059c =
0x00000030
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
setmem /32
0x020e05a0 =
0x00000030
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
setmem /32
0x020e078c =
0x00000030
// IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
setmem /32
0x020e0750 =
0x00020000
// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
setmem /32
0x020e05a8 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
setmem /32
0x020e05b0 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
setmem /32
0x020e0524 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
setmem /32
0x020e051c =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
setmem /32
0x020e0518 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
setmem /32
0x020e050c =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
setmem /32
0x020e05b8 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
setmem /32
0x020e05c0 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
//Data:
setmem /32
0x020e0774 =
0x00020000
// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
setmem /32
0x020e0784 =
0x00000028
// IOMUXC_SW_PAD_CTL_GRP_B0DS
setmem /32
0x020e0788 =
0x00000028
// IOMUXC_SW_PAD_CTL_GRP_B1DS
setmem /32
0x020e0794 =
0x00000028
// IOMUXC_SW_PAD_CTL_GRP_B2DS
setmem /32
0x020e079c =
0x00000028
// IOMUXC_SW_PAD_CTL_GRP_B3DS
setmem /32
0x020e07a0 =
0x00000028
// IOMUXC_SW_PAD_CTL_GRP_B4DS
setmem /32
0x020e07a4 =
0x00000028
// IOMUXC_SW_PAD_CTL_GRP_B5DS
setmem /32
0x020e07a8 =
0x00000028
// IOMUXC_SW_PAD_CTL_GRP_B6DS
setmem /32
0x020e0748 =
0x00000028
// IOMUXC_SW_PAD_CTL_GRP_B7DS
setmem /32
0x020e05ac =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
setmem /32
0x020e05b4 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
setmem /32
0x020e0528 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
setmem /32
0x020e0520 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
setmem /32
0x020e0514 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
setmem /32
0x020e0510 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
setmem /32
0x020e05bc =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
setmem /32
0x020e05c4 =
0x00000028
// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer:
Micron
// Device Part Number:
MT41K128M16JT-125
// Clock Freq.:
528MHz
// Density per CS in Gb:
16
// Chip Selects used:
1
// Number of Banks:
8
// Row address:
15
// Column address:
10
// Data bus width
64
//=============================================================================
setmem /32
0x021b001c =
0x00008000
MMDC0_MDSCR, set the Configuration request bit during MMDC set up
//=============================================================================
// Calibration setup.
//=============================================================================
setmem /32
0x021b0800 =
0xA1390003
// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
// For target board, may need to run write leveling calibration to fine tune these settings.
setmem /32
0x021b080c =
0x00000000
setmem /32
0x021b0810 =
0x00000000
setmem /32
0x021b480c =
0x00000000
setmem /32
0x021b4810 =
0x00000000
////Read DQS Gating calibration
setmem /32
0x021b083c =
0x00000000
// MPDGCTRL0 PHY0
setmem /32
0x021b0840 =
0x00000000
// MPDGCTRL1 PHY0
setmem /32
0x021b483c =
0x00000000
// MPDGCTRL0 PHY1
setmem /32
0x021b4840 =
0x00000000
// MPDGCTRL1 PHY1
//Read calibration
setmem /32
0x021b0848 =
0x40404040
// MPRDDLCTL PHY0
setmem /32
0x021b4848 =
0x40404040
// MPRDDLCTL PHY1
//Write calibration
setmem /32
0x021b0850 =
0x40404040
// MPWRDLCTL PHY0
setmem /32
0x021b4850 =
0x40404040
// MPWRDLCTL PHY1
//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
setmem /32
0x021b081c =
0x33333333
// DDR_PHY_P0_MPREDQBY0DL3
setmem /32
0x021b0820 =
0x33333333
// DDR_PHY_P0_MPREDQBY1DL3
setmem /32
0x021b0824 =
0x33333333
// DDR_PHY_P0_MPREDQBY2DL3
setmem /32
0x021b0828 =
0x33333333
// DDR_PHY_P0_MPREDQBY3DL3
setmem /32
0x021b481c =
0x33333333
// DDR_PHY_P1_MPREDQBY0DL3
setmem /32
0x021b4820 =
0x33333333
// DDR_PHY_P1_MPREDQBY1DL3
setmem /32
0x021b4824 =
0x33333333
// DDR_PHY_P1_MPREDQBY2DL3
setmem /32
0x021b4828 =
0x33333333
// DDR_PHY_P1_MPREDQBY3DL3
//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
//setmem /32
0x021b08c0 =
0x24911492
// fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
//setmem /32
0x021b48c0 =
0x24911492
// Complete calibration by forced measurement:
setmem /32
0x021b08b8 =
0x00000800
// DDR_PHY_P0_MPMUR0, frc_msr
setmem /32
0x021b48b8 =
0x00000800
// DDR_PHY_P0_MPMUR0, frc_msr
//=============================================================================
// Calibration setup end
//=============================================================================
//MMDC init:
setmem /32
0x021b0004 =
0x00020036
// MMDC0_MDPDC
setmem /32
0x021b0008 =
0x09444040
// MMDC0_MDOTC
setmem /32
0x021b000c =
0x54597955
// MMDC0_MDCFG0
setmem /32
0x021b0010 =
0xFF328F64
// MMDC0_MDCFG1
setmem /32
0x021b0014 =
0x01FF00DB
// MMDC0_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
setmem /32
0x021b0018 =
0x00011740
// MMDC0_MDMISC
setmem /32
0x021b001c =
0x00008000
// MMDC0_MDSCR, set the Configuration request bit during MMDC set up
setmem /32
0x021b002c =
0x000026D2
// MMDC0_MDRWD
setmem /32
0x021b0030 =
0x00591023
// MMDC0_MDOR
setmem /32
0x021b0040 =
0x00000047
// Chan0 CS0_END
setmem /32
0x021b0000 =
0x841A0000
// MMDC0_MDCTL
//Mode register writes
setmem /32
0x021b001c =
0x02088032
// MMDC0_MDSCR, MR2 write, CS0
setmem /32
0x021b001c =
0x00008033
// MMDC0_MDSCR, MR3 write, CS0
setmem /32
0x021b001c =
0x00408031
// MMDC0_MDSCR, MR1 write, CS0
setmem /32
0x021b001c =
0x19408030
// MMDC0_MDSCR, MR0write, CS0
setmem /32
0x021b001c =
0x04008040
// MMDC0_MDSCR, ZQ calibration command sent to device on CS0
//setmem /32
0x021b001c =
0x0208803A
// MMDC0_MDSCR, MR2 write, CS1
//setmem /32
0x021b001c =
0x0000803B
// MMDC0_MDSCR, MR3 write, CS1
//setmem /32
0x021b001c =
0x00408039
// MMDC0_MDSCR, MR1 write, CS1
//setmem /32
0x021b001c =
0x19408038
// MMDC0_MDSCR, MR0write, CS1
//setmem /32
0x021b001c =
0x04008048
// MMDC0_MDSCR, ZQ calibration command sent to device on CS1
setmem /32
0x021b0020 =
0x00007800
// MMDC0_MDREF
setmem /32
0x021b0818 =
0x00011117
// DDR_PHY_P0_MPODTCTRL
setmem /32
0x021b4818 =
0x00011117
// DDR_PHY_P1_MPODTCTRL
setmem /32
0x021b0004 =
0x00025576
// MMDC0_MDPDC now SDCTL power down enabled
setmem /32
0x021b0404 =
0x00011006
// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
setmem /32
0x021b001c =
0x00000000
// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
PS.: sorry for my English
regards,
Péter
reply other threads:[~2017-06-15 13:31 UTC|newest]
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