diff for duplicates of <1497607375.3086.40.camel@baylibre.com> diff --git a/a/content_digest b/N1/content_digest index 5b4ee03..06c08ee 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,7 +4,7 @@ "From\0jbrunet@baylibre.com (Jerome Brunet)\0" "Subject\0[PATCH v3 2/6] irqchip: meson: add support for gpio interrupt controller\0" "Date\0Fri, 16 Jun 2017 12:02:55 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote:\n" @@ -560,4 +560,4 @@ "> \n" "> \tM." -31fa1c18ca35de05ce9bcb1a2e58051b2d1c8b5188cdf19a2b256239167197ba +47bf7e271b15021a378605b5800941da8b8e1bcfcc307e8235af84941bae25e1
diff --git a/a/1.txt b/N2/1.txt index 3e7548f..723398f 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -11,40 +11,40 @@ On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote: > > edge and polarity. The number of actual mappable inputs depends on the > > SoC. > > -> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> +> > Signed-off-by: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> > > --- -> > ?drivers/irqchip/Kconfig??????????|???8 + -> > ?drivers/irqchip/Makefile?????????|???1 + -> > ?drivers/irqchip/irq-meson-gpio.c | 407 +> > drivers/irqchip/Kconfig | 8 + +> > drivers/irqchip/Makefile | 1 + +> > drivers/irqchip/irq-meson-gpio.c | 407 > > +++++++++++++++++++++++++++++++++++++++ -> > ?3 files changed, 416 insertions(+) -> > ?create mode 100644 drivers/irqchip/irq-meson-gpio.c +> > 3 files changed, 416 insertions(+) +> > create mode 100644 drivers/irqchip/irq-meson-gpio.c > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > index 478f8ace2664..be577a7512cc 100644 > > --- a/drivers/irqchip/Kconfig > > +++ b/drivers/irqchip/Kconfig > > @@ -301,3 +301,11 @@ config QCOM_IRQ_COMBINER -> > ? help -> > ? ??Say yes here to add support for the IRQ combiner devices embedded -> > ? ??in Qualcomm Technologies chips. +> > help +> > Say yes here to add support for the IRQ combiner devices embedded +> > in Qualcomm Technologies chips. > > + > > +config MESON_IRQ_GPIO -> > +???????bool "Meson GPIO Interrupt Multiplexer" -> > +???????depends on ARCH_MESON || COMPILE_TEST -> > +???????select IRQ_DOMAIN -> > +???????select IRQ_DOMAIN_HIERARCHY -> > +???????help -> > +?????????Support Meson SoC Family GPIO Interrupt Multiplexer +> > + bool "Meson GPIO Interrupt Multiplexer" +> > + depends on ARCH_MESON || COMPILE_TEST +> > + select IRQ_DOMAIN +> > + select IRQ_DOMAIN_HIERARCHY +> > + help +> > + Support Meson SoC Family GPIO Interrupt Multiplexer > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > index b64c59b838a0..95bf2715850e 100644 > > --- a/drivers/irqchip/Makefile > > +++ b/drivers/irqchip/Makefile > > @@ -76,3 +76,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq- > > eznps.o -> > ?obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o -> > ?obj-$(CONFIG_STM32_EXTI)? += irq-stm32-exti.o -> > ?obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o +> > obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o +> > obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o +> > obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o > > +obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o > > diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson- > > gpio.c @@ -55,9 +55,9 @@ On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote: > > @@ -0,0 +1,407 @@ > > +/* > > + * Copyright (c) 2015 Endless Mobile, Inc. -> > + * Author: Carlo Caione <carlo@endlessm.com> +> > + * Author: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org> > > + * Copyright (c) 2016 BayLibre, SAS. -> > + * Author: Jerome Brunet <jbrunet@baylibre.com> +> > + * Author: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of version 2 of the GNU General Public License as @@ -65,7 +65,7 @@ On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote: > > + * > > + * This program is distributed in the hope that it will be useful, but > > + * WITHOUT ANY WARRANTY; without even the implied warranty of -> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the GNU +> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License @@ -144,8 +144,8 @@ some other change that would require some other adaptation. Also, there this comment in "include/linux/bitmap.h" : -?* Note that nbits should be always a compile time evaluable constant. -?* Otherwise many inlines will generate horrible code. + * Note that nbits should be always a compile time evaluable constant. + * Otherwise many inlines will generate horrible code. Finally there was your advice from the v2 to not make the driver unnecessarily complicated. @@ -162,7 +162,7 @@ Would you agree ? > > + > > +static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller > > *ctl, -> > + ???????unsigned int reg, u32 mask, u32 val) +> > + unsigned int reg, u32 mask, u32 val) > > +{ > > + u32 tmp; > > + @@ -174,8 +174,8 @@ Would you agree ? > > + > > +static int > > +meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, -> > + ???????unsigned long??hwirq, -> > + ???????u32 **parent_hwirq) +> > + unsigned long hwirq, +> > + u32 **parent_hwirq) > > +{ > > + unsigned int reg, channel; > > + unsigned long flags; @@ -206,9 +206,9 @@ Is this version the one I should use ? > > + set_bit(channel, ctl->map); > > + > > + /* -> > + ?* Setup the mux of the channel to route the signal of the pad -> > + ?* to the appropriate input of the GIC -> > + ?*/ +> > + * Setup the mux of the channel to route the signal of the pad +> > + * to the appropriate input of the GIC +> > + */ > > + reg = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; > > Make a helper for this (channel_to_reg?). @@ -217,8 +217,8 @@ Ok. why not. > > > + meson_gpio_irq_update_bits(ctl, reg, -> > + ???0xff << REG_PIN_SEL_SHIFT(channel), -> > + ???hwirq << REG_PIN_SEL_SHIFT(channel)); +> > + 0xff << REG_PIN_SEL_SHIFT(channel), +> > + hwirq << REG_PIN_SEL_SHIFT(channel)); > > + > > + /* Get the parent hwirq number assigned to this channel */ > > + *parent_hwirq = &(ctl->upstream_irq[channel]); @@ -234,21 +234,21 @@ To be fair, it was your idea initially :P > > + spin_unlock_irqrestore(&ctl->lock, flags); > > + > > + pr_debug("hwirq %lu assigned to channel %d - parent %u\n", -> > + ?hwirq, channel, **parent_hwirq); +> > + hwirq, channel, **parent_hwirq); > > + > > + return 0; > > +} > > + > > +static unsigned int > > +meson_gpio_irq_get_channel(struct meson_gpio_irq_controller *ctl, -> > + ???u32 *parent_hwirq) +> > + u32 *parent_hwirq) > > +{ > > + return parent_hwirq - ctl->upstream_irq; > > +} > > + > > +static void > > +meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl, -> > + ???????u32 *parent_hwirq) +> > + u32 *parent_hwirq) > > +{ > > + unsigned int channel; > > + @@ -257,8 +257,8 @@ To be fair, it was your idea initially :P > > +} > > + > > +static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, -> > + ?????unsigned int type, -> > + ?????u32 *parent_hwirq) +> > + unsigned int type, +> > + u32 *parent_hwirq) > > +{ > > + u32 val = 0; > > + unsigned int channel; @@ -267,14 +267,14 @@ To be fair, it was your idea initially :P > > + channel = meson_gpio_irq_get_channel(ctl, parent_hwirq); > > + > > + /* -> > + ?* The controller has a filter block to operate in either LEVEL or -> > + ?* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW +> > + * The controller has a filter block to operate in either LEVEL or +> > + * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW > > and -> > + ?* EDGE_FALLING support (which the GIC does not support), the +> > + * EDGE_FALLING support (which the GIC does not support), the > > filter -> > + ?* block is also able to invert the input signal it gets before -> > + ?* providing it to the GIC. -> > + ?*/ +> > + * block is also able to invert the input signal it gets before +> > + * providing it to the GIC. +> > + */ > > + type &= IRQ_TYPE_SENSE_MASK; > > + > > + if (type == IRQ_TYPE_EDGE_BOTH) @@ -289,7 +289,7 @@ To be fair, it was your idea initially :P > > + spin_lock_irqsave(&ctl->lock, flags); > > + > > + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, -> > + ???REG_EDGE_POL_MASK(channel), val); +> > + REG_EDGE_POL_MASK(channel), val); > > + > > + spin_unlock_irqrestore(&ctl->lock, flags); > > + @@ -303,9 +303,9 @@ To be fair, it was your idea initially :P > > + type &= ~IRQ_TYPE_SENSE_MASK; > > + > > + /* -> > + ?* The polarity of the signal provided to the GIC should always -> > + ?* be high. -> > + ?*/ +> > + * The polarity of the signal provided to the GIC should always +> > + * be high. +> > + */ > > + if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) > > + type |= IRQ_TYPE_LEVEL_HIGH; > > + else if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) @@ -343,9 +343,9 @@ To be fair, it was your idea initially :P > > +}; > > + > > +static int meson_gpio_irq_domain_translate(struct irq_domain *domain, -> > + ???struct irq_fwspec *fwspec, -> > + ???unsigned long *hwirq, -> > + ???unsigned int *type) +> > + struct irq_fwspec *fwspec, +> > + unsigned long *hwirq, +> > + unsigned int *type) > > +{ > > + if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) { > > + *hwirq = fwspec->param[0]; @@ -357,9 +357,9 @@ To be fair, it was your idea initially :P > > +} > > + > > +static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain, -> > + ???unsigned int virq, -> > + ???u32 hwirq, -> > + ???unsigned int type) +> > + unsigned int virq, +> > + u32 hwirq, +> > + unsigned int type) > > +{ > > + struct irq_fwspec fwspec; > > + @@ -373,9 +373,9 @@ To be fair, it was your idea initially :P > > +} > > + > > +static int meson_gpio_irq_domain_alloc(struct irq_domain *domain, -> > + ???????unsigned int virq, -> > + ???????unsigned int nr_irqs, -> > + ???????void *data) +> > + unsigned int virq, +> > + unsigned int nr_irqs, +> > + void *data) > > +{ > > + struct irq_fwspec *fwspec = data; > > + struct meson_gpio_irq_controller *ctl = domain->host_data; @@ -397,7 +397,7 @@ To be fair, it was your idea initially :P > > + return ret; > > + > > + ret = meson_gpio_irq_allocate_gic_irq(domain, virq, -> > + ??????*parent_hwirq, type); +> > + *parent_hwirq, type); > > + if (ret < 0) { > > + pr_err("failed to allocate gic irq %u\n", *parent_hwirq); > @@ -410,14 +410,14 @@ Oops ... > > + } > > + > > + irq_domain_set_hwirq_and_chip(domain, virq, hwirq, -> > + ??????&meson_gpio_irq_chip, parent_hwirq); +> > + &meson_gpio_irq_chip, parent_hwirq); > > + > > + return 0; > > +} > > + > > +static void meson_gpio_irq_domain_free(struct irq_domain *domain, -> > + ???????unsigned int virq, -> > + ???????unsigned int nr_irqs) +> > + unsigned int virq, +> > + unsigned int nr_irqs) > > +{ > > + struct meson_gpio_irq_controller *ctl = domain->host_data; > > + struct irq_data *irq_data; @@ -441,7 +441,7 @@ Oops ... > > +}; > > + > > +static int __init meson_gpio_irq_parse_dt(struct device_node *node, -> > + ??struct meson_gpio_irq_controller +> > + struct meson_gpio_irq_controller > > *ctl) > > +{ > > + const struct of_device_id *match; @@ -456,11 +456,11 @@ Oops ... > > + ctl->nr_hwirq = params->nr_hwirq; > > + > > + ret = of_property_read_variable_u32_array(node, -> > + ??"amlogic,upstream- +> > + "amlogic,upstream- > > interrupts", -> > + ??ctl->upstream_irq, -> > + ??NUM_UPSTREAM_IRQ, -> > + ??NUM_UPSTREAM_IRQ); +> > + ctl->upstream_irq, +> > + NUM_UPSTREAM_IRQ, +> > + NUM_UPSTREAM_IRQ); > > + if (ret < 0) { > > + pr_err("can't get %d upstream interrupts\n", > > NUM_UPSTREAM_IRQ); @@ -471,7 +471,7 @@ Oops ... > > +} > > + > > +static int __init meson_gpio_irq_of_init(struct device_node *node, -> > + ?struct device_node *parent) +> > + struct device_node *parent) > > +{ > > + struct irq_domain *domain, *parent_domain; > > + struct meson_gpio_irq_controller *ctl; @@ -514,9 +514,9 @@ indeed > > + > > + domain = irq_domain_create_hierarchy(parent_domain, 0, ctl- > > >nr_hwirq, -> > + ?????of_node_to_fwnode(node), -> > + ?????&meson_gpio_irq_domain_ops, -> > + ?????ctl); +> > + of_node_to_fwnode(node), +> > + &meson_gpio_irq_domain_ops, +> > + ctl); > > + if (!domain) { > > + pr_err("failed to add domain\n"); > > + ret = -ENODEV; @@ -550,3 +550,8 @@ Noted > Thanks, > > M. + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index 5b4ee03..ccc0644 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,10 +1,20 @@ "ref\020170615161804.32658-1-jbrunet@baylibre.com\0" "ref\020170615161804.32658-3-jbrunet@baylibre.com\0" "ref\0d37dae42-77df-72b7-0898-a4873ccbbcce@arm.com\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH v3 2/6] irqchip: meson: add support for gpio interrupt controller\0" + "ref\0d37dae42-77df-72b7-0898-a4873ccbbcce-5wv7dgnIgG8@public.gmane.org\0" + "From\0Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Subject\0Re: [PATCH v3 2/6] irqchip: meson: add support for gpio interrupt controller\0" "Date\0Fri, 16 Jun 2017 12:02:55 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>" + Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org> + Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org> + " Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Cc\0Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>" + linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " Heiner Kallweit <hkallweit1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" "\00:1\0" "b\0" "On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote:\n" @@ -20,40 +30,40 @@ "> > edge and polarity. The number of actual mappable inputs depends on the\n" "> > SoC.\n" "> > \n" - "> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>\n" + "> > Signed-off-by: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\n" "> > ---\n" - "> > ?drivers/irqchip/Kconfig??????????|???8 +\n" - "> > ?drivers/irqchip/Makefile?????????|???1 +\n" - "> > ?drivers/irqchip/irq-meson-gpio.c | 407\n" + "> > \302\240drivers/irqchip/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\240\302\2408 +\n" + "> > \302\240drivers/irqchip/Makefile\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\240\302\2401 +\n" + "> > \302\240drivers/irqchip/irq-meson-gpio.c | 407\n" "> > +++++++++++++++++++++++++++++++++++++++\n" - "> > ?3 files changed, 416 insertions(+)\n" - "> > ?create mode 100644 drivers/irqchip/irq-meson-gpio.c\n" + "> > \302\2403 files changed, 416 insertions(+)\n" + "> > \302\240create mode 100644 drivers/irqchip/irq-meson-gpio.c\n" "> > \n" "> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig\n" "> > index 478f8ace2664..be577a7512cc 100644\n" "> > --- a/drivers/irqchip/Kconfig\n" "> > +++ b/drivers/irqchip/Kconfig\n" "> > @@ -301,3 +301,11 @@ config QCOM_IRQ_COMBINER\n" - "> > ?\thelp\n" - "> > ?\t??Say yes here to add support for the IRQ combiner devices embedded\n" - "> > ?\t??in Qualcomm Technologies chips.\n" + "> > \302\240\thelp\n" + "> > \302\240\t\302\240\302\240Say yes here to add support for the IRQ combiner devices embedded\n" + "> > \302\240\t\302\240\302\240in Qualcomm Technologies chips.\n" "> > +\n" "> > +config MESON_IRQ_GPIO\n" - "> > +???????bool \"Meson GPIO Interrupt Multiplexer\"\n" - "> > +???????depends on ARCH_MESON || COMPILE_TEST\n" - "> > +???????select IRQ_DOMAIN\n" - "> > +???????select IRQ_DOMAIN_HIERARCHY\n" - "> > +???????help\n" - "> > +?????????Support Meson SoC Family GPIO Interrupt Multiplexer\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240bool \"Meson GPIO Interrupt Multiplexer\"\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on ARCH_MESON || COMPILE_TEST\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240select IRQ_DOMAIN\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240select IRQ_DOMAIN_HIERARCHY\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240help\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240Support Meson SoC Family GPIO Interrupt Multiplexer\n" "> > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile\n" "> > index b64c59b838a0..95bf2715850e 100644\n" "> > --- a/drivers/irqchip/Makefile\n" "> > +++ b/drivers/irqchip/Makefile\n" "> > @@ -76,3 +76,4 @@ obj-$(CONFIG_EZNPS_GIC)\t\t\t+= irq-\n" "> > eznps.o\n" - "> > ?obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-vic.o\n" - "> > ?obj-$(CONFIG_STM32_EXTI)?\t\t+= irq-stm32-exti.o\n" - "> > ?obj-$(CONFIG_QCOM_IRQ_COMBINER)\t\t+= qcom-irq-combiner.o\n" + "> > \302\240obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-vic.o\n" + "> > \302\240obj-$(CONFIG_STM32_EXTI)\302\240\t\t+= irq-stm32-exti.o\n" + "> > \302\240obj-$(CONFIG_QCOM_IRQ_COMBINER)\t\t+= qcom-irq-combiner.o\n" "> > +obj-$(CONFIG_MESON_IRQ_GPIO)\t\t+= irq-meson-gpio.o\n" "> > diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-\n" "> > gpio.c\n" @@ -64,9 +74,9 @@ "> > @@ -0,0 +1,407 @@\n" "> > +/*\n" "> > + * Copyright (c) 2015 Endless Mobile, Inc.\n" - "> > + * Author: Carlo Caione <carlo@endlessm.com>\n" + "> > + * Author: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>\n" "> > + * Copyright (c) 2016 BayLibre, SAS.\n" - "> > + * Author: Jerome Brunet <jbrunet@baylibre.com>\n" + "> > + * Author: Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\n" "> > + *\n" "> > + * This program is free software; you can redistribute it and/or modify\n" "> > + * it under the terms of version 2 of the GNU General Public License as\n" @@ -74,7 +84,7 @@ "> > + *\n" "> > + * This program is distributed in the hope that it will be useful, but\n" "> > + * WITHOUT ANY WARRANTY; without even the implied warranty of\n" - "> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the GNU\n" + "> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\302\240\302\240See the GNU\n" "> > + * General Public License for more details.\n" "> > + *\n" "> > + * You should have received a copy of the GNU General Public License\n" @@ -153,8 +163,8 @@ "\n" "Also, there this comment in \"include/linux/bitmap.h\" :\n" "\n" - "?* Note that nbits should be always a compile time evaluable constant.\n" - "?* Otherwise many inlines will generate horrible code.\n" + "\302\240* Note that nbits should be always a compile time evaluable constant.\n" + "\302\240* Otherwise many inlines will generate horrible code.\n" "\n" "Finally there was your advice from the v2 to not make the driver unnecessarily\n" "complicated.\n" @@ -171,7 +181,7 @@ "> > +\n" "> > +static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller\n" "> > *ctl,\n" - "> > +\t\t\t\t???????unsigned int reg, u32 mask, u32 val)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int reg, u32 mask, u32 val)\n" "> > +{\n" "> > +\tu32 tmp;\n" "> > +\n" @@ -183,8 +193,8 @@ "> > +\n" "> > +static int\n" "> > +meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,\n" - "> > +\t\t\t???????unsigned long??hwirq,\n" - "> > +\t\t\t???????u32 **parent_hwirq)\n" + "> > +\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned long\302\240\302\240hwirq,\n" + "> > +\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 **parent_hwirq)\n" "> > +{\n" "> > +\tunsigned int reg, channel;\n" "> > +\tunsigned long flags;\n" @@ -215,9 +225,9 @@ "> > +\tset_bit(channel, ctl->map);\n" "> > +\n" "> > +\t/*\n" - "> > +\t?* Setup the mux of the channel to route the signal of the pad\n" - "> > +\t?* to the appropriate input of the GIC\n" - "> > +\t?*/\n" + "> > +\t\302\240* Setup the mux of the channel to route the signal of the pad\n" + "> > +\t\302\240* to the appropriate input of the GIC\n" + "> > +\t\302\240*/\n" "> > +\treg = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;\n" "> \n" "> Make a helper for this (channel_to_reg?).\n" @@ -226,8 +236,8 @@ "\n" "> \n" "> > +\tmeson_gpio_irq_update_bits(ctl, reg,\n" - "> > +\t\t\t\t???0xff << REG_PIN_SEL_SHIFT(channel),\n" - "> > +\t\t\t\t???hwirq << REG_PIN_SEL_SHIFT(channel));\n" + "> > +\t\t\t\t\302\240\302\240\302\2400xff << REG_PIN_SEL_SHIFT(channel),\n" + "> > +\t\t\t\t\302\240\302\240\302\240hwirq << REG_PIN_SEL_SHIFT(channel));\n" "> > +\n" "> > +\t/* Get the parent hwirq number assigned to this channel */\n" "> > +\t*parent_hwirq = &(ctl->upstream_irq[channel]);\n" @@ -243,21 +253,21 @@ "> > +\tspin_unlock_irqrestore(&ctl->lock, flags);\n" "> > +\n" "> > +\tpr_debug(\"hwirq %lu assigned to channel %d - parent %u\\n\",\n" - "> > +\t\t?hwirq, channel, **parent_hwirq);\n" + "> > +\t\t\302\240hwirq, channel, **parent_hwirq);\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" "> > +static unsigned int\n" "> > +meson_gpio_irq_get_channel(struct meson_gpio_irq_controller *ctl,\n" - "> > +\t\t\t???u32 *parent_hwirq)\n" + "> > +\t\t\t\302\240\302\240\302\240u32 *parent_hwirq)\n" "> > +{\n" "> > +\treturn parent_hwirq - ctl->upstream_irq;\n" "> > +}\n" "> > +\n" "> > +static void\n" "> > +meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,\n" - "> > +\t\t\t???????u32 *parent_hwirq)\n" + "> > +\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 *parent_hwirq)\n" "> > +{\n" "> > +\tunsigned int channel;\n" "> > +\n" @@ -266,8 +276,8 @@ "> > +}\n" "> > +\n" "> > +static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,\n" - "> > +\t\t\t\t?????unsigned int type,\n" - "> > +\t\t\t\t?????u32 *parent_hwirq)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240unsigned int type,\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240u32 *parent_hwirq)\n" "> > +{\n" "> > +\tu32 val = 0;\n" "> > +\tunsigned int channel;\n" @@ -276,14 +286,14 @@ "> > +\tchannel = meson_gpio_irq_get_channel(ctl, parent_hwirq);\n" "> > +\n" "> > +\t/*\n" - "> > +\t?* The controller has a filter block to operate in either LEVEL or\n" - "> > +\t?* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW\n" + "> > +\t\302\240* The controller has a filter block to operate in either LEVEL or\n" + "> > +\t\302\240* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW\n" "> > and\n" - "> > +\t?* EDGE_FALLING support (which the GIC does not support), the\n" + "> > +\t\302\240* EDGE_FALLING support (which the GIC does not support), the\n" "> > filter\n" - "> > +\t?* block is also able to invert the input signal it gets before\n" - "> > +\t?* providing it to the GIC.\n" - "> > +\t?*/\n" + "> > +\t\302\240* block is also able to invert the input signal it gets before\n" + "> > +\t\302\240* providing it to the GIC.\n" + "> > +\t\302\240*/\n" "> > +\ttype &= IRQ_TYPE_SENSE_MASK;\n" "> > +\n" "> > +\tif (type == IRQ_TYPE_EDGE_BOTH)\n" @@ -298,7 +308,7 @@ "> > +\tspin_lock_irqsave(&ctl->lock, flags);\n" "> > +\n" "> > +\tmeson_gpio_irq_update_bits(ctl, REG_EDGE_POL,\n" - "> > +\t\t\t\t???REG_EDGE_POL_MASK(channel), val);\n" + "> > +\t\t\t\t\302\240\302\240\302\240REG_EDGE_POL_MASK(channel), val);\n" "> > +\n" "> > +\tspin_unlock_irqrestore(&ctl->lock, flags);\n" "> > +\n" @@ -312,9 +322,9 @@ "> > +\ttype &= ~IRQ_TYPE_SENSE_MASK;\n" "> > +\n" "> > +\t/*\n" - "> > +\t?* The polarity of the signal provided to the GIC should always\n" - "> > +\t?* be high.\n" - "> > +\t?*/\n" + "> > +\t\302\240* The polarity of the signal provided to the GIC should always\n" + "> > +\t\302\240* be high.\n" + "> > +\t\302\240*/\n" "> > +\tif (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))\n" "> > +\t\ttype |= IRQ_TYPE_LEVEL_HIGH;\n" "> > +\telse if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))\n" @@ -352,9 +362,9 @@ "> > +};\n" "> > +\n" "> > +static int meson_gpio_irq_domain_translate(struct irq_domain *domain,\n" - "> > +\t\t\t\t\t???struct irq_fwspec *fwspec,\n" - "> > +\t\t\t\t\t???unsigned long *hwirq,\n" - "> > +\t\t\t\t\t???unsigned int *type)\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240struct irq_fwspec *fwspec,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240unsigned long *hwirq,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240unsigned int *type)\n" "> > +{\n" "> > +\tif (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {\n" "> > +\t\t*hwirq\t= fwspec->param[0];\n" @@ -366,9 +376,9 @@ "> > +}\n" "> > +\n" "> > +static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,\n" - "> > +\t\t\t\t\t???unsigned int virq,\n" - "> > +\t\t\t\t\t???u32 hwirq,\n" - "> > +\t\t\t\t\t???unsigned int type)\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240unsigned int virq,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240u32 hwirq,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240unsigned int type)\n" "> > +{\n" "> > +\tstruct irq_fwspec fwspec;\n" "> > +\n" @@ -382,9 +392,9 @@ "> > +}\n" "> > +\n" "> > +static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,\n" - "> > +\t\t\t\t???????unsigned int virq,\n" - "> > +\t\t\t\t???????unsigned int nr_irqs,\n" - "> > +\t\t\t\t???????void *data)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int virq,\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int nr_irqs,\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240void *data)\n" "> > +{\n" "> > +\tstruct irq_fwspec *fwspec = data;\n" "> > +\tstruct meson_gpio_irq_controller *ctl = domain->host_data;\n" @@ -406,7 +416,7 @@ "> > +\t\treturn ret;\n" "> > +\n" "> > +\tret = meson_gpio_irq_allocate_gic_irq(domain, virq,\n" - "> > +\t\t\t\t\t??????*parent_hwirq, type);\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240*parent_hwirq, type);\n" "> > +\tif (ret < 0) {\n" "> > +\t\tpr_err(\"failed to allocate gic irq %u\\n\", *parent_hwirq);\n" "> \n" @@ -419,14 +429,14 @@ "> > +\t}\n" "> > +\n" "> > +\tirq_domain_set_hwirq_and_chip(domain, virq, hwirq,\n" - "> > +\t\t\t\t??????&meson_gpio_irq_chip, parent_hwirq);\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240&meson_gpio_irq_chip, parent_hwirq);\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" "> > +static void meson_gpio_irq_domain_free(struct irq_domain *domain,\n" - "> > +\t\t\t\t???????unsigned int virq,\n" - "> > +\t\t\t\t???????unsigned int nr_irqs)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int virq,\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int nr_irqs)\n" "> > +{\n" "> > +\tstruct meson_gpio_irq_controller *ctl = domain->host_data;\n" "> > +\tstruct irq_data *irq_data;\n" @@ -450,7 +460,7 @@ "> > +};\n" "> > +\n" "> > +static int __init meson_gpio_irq_parse_dt(struct device_node *node,\n" - "> > +\t\t\t\t\t??struct meson_gpio_irq_controller\n" + "> > +\t\t\t\t\t\302\240\302\240struct meson_gpio_irq_controller\n" "> > *ctl)\n" "> > +{\n" "> > +\tconst struct of_device_id *match;\n" @@ -465,11 +475,11 @@ "> > +\tctl->nr_hwirq = params->nr_hwirq;\n" "> > +\n" "> > +\tret = of_property_read_variable_u32_array(node,\n" - "> > +\t\t\t\t\t\t??\"amlogic,upstream-\n" + "> > +\t\t\t\t\t\t\302\240\302\240\"amlogic,upstream-\n" "> > interrupts\",\n" - "> > +\t\t\t\t\t\t??ctl->upstream_irq,\n" - "> > +\t\t\t\t\t\t??NUM_UPSTREAM_IRQ,\n" - "> > +\t\t\t\t\t\t??NUM_UPSTREAM_IRQ);\n" + "> > +\t\t\t\t\t\t\302\240\302\240ctl->upstream_irq,\n" + "> > +\t\t\t\t\t\t\302\240\302\240NUM_UPSTREAM_IRQ,\n" + "> > +\t\t\t\t\t\t\302\240\302\240NUM_UPSTREAM_IRQ);\n" "> > +\tif (ret < 0) {\n" "> > +\t\tpr_err(\"can't get %d upstream interrupts\\n\",\n" "> > NUM_UPSTREAM_IRQ);\n" @@ -480,7 +490,7 @@ "> > +}\n" "> > +\n" "> > +static int __init meson_gpio_irq_of_init(struct device_node *node,\n" - "> > +\t\t\t\t\t?struct device_node *parent)\n" + "> > +\t\t\t\t\t\302\240struct device_node *parent)\n" "> > +{\n" "> > +\tstruct irq_domain *domain, *parent_domain;\n" "> > +\tstruct meson_gpio_irq_controller *ctl;\n" @@ -523,9 +533,9 @@ "> > +\n" "> > +\tdomain = irq_domain_create_hierarchy(parent_domain, 0, ctl-\n" "> > >nr_hwirq,\n" - "> > +\t\t\t\t\t?????of_node_to_fwnode(node),\n" - "> > +\t\t\t\t\t?????&meson_gpio_irq_domain_ops,\n" - "> > +\t\t\t\t\t?????ctl);\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240\302\240\302\240of_node_to_fwnode(node),\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240\302\240\302\240&meson_gpio_irq_domain_ops,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240\302\240\302\240ctl);\n" "> > +\tif (!domain) {\n" "> > +\t\tpr_err(\"failed to add domain\\n\");\n" "> > +\t\tret = -ENODEV;\n" @@ -558,6 +568,11 @@ "> \n" "> Thanks,\n" "> \n" - "> \tM." + "> \tM.\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -31fa1c18ca35de05ce9bcb1a2e58051b2d1c8b5188cdf19a2b256239167197ba +a7320a49a1f8662419b37241583e377e94ca62afa1c4180b0d1e68959cb43f0b
diff --git a/a/1.txt b/N3/1.txt index 3e7548f..281b58f 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -13,38 +13,38 @@ On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote: > > > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > > --- -> > ?drivers/irqchip/Kconfig??????????|???8 + -> > ?drivers/irqchip/Makefile?????????|???1 + -> > ?drivers/irqchip/irq-meson-gpio.c | 407 +> > drivers/irqchip/Kconfig | 8 + +> > drivers/irqchip/Makefile | 1 + +> > drivers/irqchip/irq-meson-gpio.c | 407 > > +++++++++++++++++++++++++++++++++++++++ -> > ?3 files changed, 416 insertions(+) -> > ?create mode 100644 drivers/irqchip/irq-meson-gpio.c +> > 3 files changed, 416 insertions(+) +> > create mode 100644 drivers/irqchip/irq-meson-gpio.c > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > index 478f8ace2664..be577a7512cc 100644 > > --- a/drivers/irqchip/Kconfig > > +++ b/drivers/irqchip/Kconfig > > @@ -301,3 +301,11 @@ config QCOM_IRQ_COMBINER -> > ? help -> > ? ??Say yes here to add support for the IRQ combiner devices embedded -> > ? ??in Qualcomm Technologies chips. +> > help +> > Say yes here to add support for the IRQ combiner devices embedded +> > in Qualcomm Technologies chips. > > + > > +config MESON_IRQ_GPIO -> > +???????bool "Meson GPIO Interrupt Multiplexer" -> > +???????depends on ARCH_MESON || COMPILE_TEST -> > +???????select IRQ_DOMAIN -> > +???????select IRQ_DOMAIN_HIERARCHY -> > +???????help -> > +?????????Support Meson SoC Family GPIO Interrupt Multiplexer +> > + bool "Meson GPIO Interrupt Multiplexer" +> > + depends on ARCH_MESON || COMPILE_TEST +> > + select IRQ_DOMAIN +> > + select IRQ_DOMAIN_HIERARCHY +> > + help +> > + Support Meson SoC Family GPIO Interrupt Multiplexer > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > index b64c59b838a0..95bf2715850e 100644 > > --- a/drivers/irqchip/Makefile > > +++ b/drivers/irqchip/Makefile > > @@ -76,3 +76,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq- > > eznps.o -> > ?obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o -> > ?obj-$(CONFIG_STM32_EXTI)? += irq-stm32-exti.o -> > ?obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o +> > obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o +> > obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o +> > obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o > > +obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o > > diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson- > > gpio.c @@ -65,7 +65,7 @@ On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote: > > + * > > + * This program is distributed in the hope that it will be useful, but > > + * WITHOUT ANY WARRANTY; without even the implied warranty of -> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the GNU +> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License @@ -144,8 +144,8 @@ some other change that would require some other adaptation. Also, there this comment in "include/linux/bitmap.h" : -?* Note that nbits should be always a compile time evaluable constant. -?* Otherwise many inlines will generate horrible code. + * Note that nbits should be always a compile time evaluable constant. + * Otherwise many inlines will generate horrible code. Finally there was your advice from the v2 to not make the driver unnecessarily complicated. @@ -162,7 +162,7 @@ Would you agree ? > > + > > +static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller > > *ctl, -> > + ???????unsigned int reg, u32 mask, u32 val) +> > + unsigned int reg, u32 mask, u32 val) > > +{ > > + u32 tmp; > > + @@ -174,8 +174,8 @@ Would you agree ? > > + > > +static int > > +meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, -> > + ???????unsigned long??hwirq, -> > + ???????u32 **parent_hwirq) +> > + unsigned long hwirq, +> > + u32 **parent_hwirq) > > +{ > > + unsigned int reg, channel; > > + unsigned long flags; @@ -206,9 +206,9 @@ Is this version the one I should use ? > > + set_bit(channel, ctl->map); > > + > > + /* -> > + ?* Setup the mux of the channel to route the signal of the pad -> > + ?* to the appropriate input of the GIC -> > + ?*/ +> > + * Setup the mux of the channel to route the signal of the pad +> > + * to the appropriate input of the GIC +> > + */ > > + reg = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; > > Make a helper for this (channel_to_reg?). @@ -217,8 +217,8 @@ Ok. why not. > > > + meson_gpio_irq_update_bits(ctl, reg, -> > + ???0xff << REG_PIN_SEL_SHIFT(channel), -> > + ???hwirq << REG_PIN_SEL_SHIFT(channel)); +> > + 0xff << REG_PIN_SEL_SHIFT(channel), +> > + hwirq << REG_PIN_SEL_SHIFT(channel)); > > + > > + /* Get the parent hwirq number assigned to this channel */ > > + *parent_hwirq = &(ctl->upstream_irq[channel]); @@ -234,21 +234,21 @@ To be fair, it was your idea initially :P > > + spin_unlock_irqrestore(&ctl->lock, flags); > > + > > + pr_debug("hwirq %lu assigned to channel %d - parent %u\n", -> > + ?hwirq, channel, **parent_hwirq); +> > + hwirq, channel, **parent_hwirq); > > + > > + return 0; > > +} > > + > > +static unsigned int > > +meson_gpio_irq_get_channel(struct meson_gpio_irq_controller *ctl, -> > + ???u32 *parent_hwirq) +> > + u32 *parent_hwirq) > > +{ > > + return parent_hwirq - ctl->upstream_irq; > > +} > > + > > +static void > > +meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl, -> > + ???????u32 *parent_hwirq) +> > + u32 *parent_hwirq) > > +{ > > + unsigned int channel; > > + @@ -257,8 +257,8 @@ To be fair, it was your idea initially :P > > +} > > + > > +static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, -> > + ?????unsigned int type, -> > + ?????u32 *parent_hwirq) +> > + unsigned int type, +> > + u32 *parent_hwirq) > > +{ > > + u32 val = 0; > > + unsigned int channel; @@ -267,14 +267,14 @@ To be fair, it was your idea initially :P > > + channel = meson_gpio_irq_get_channel(ctl, parent_hwirq); > > + > > + /* -> > + ?* The controller has a filter block to operate in either LEVEL or -> > + ?* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW +> > + * The controller has a filter block to operate in either LEVEL or +> > + * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW > > and -> > + ?* EDGE_FALLING support (which the GIC does not support), the +> > + * EDGE_FALLING support (which the GIC does not support), the > > filter -> > + ?* block is also able to invert the input signal it gets before -> > + ?* providing it to the GIC. -> > + ?*/ +> > + * block is also able to invert the input signal it gets before +> > + * providing it to the GIC. +> > + */ > > + type &= IRQ_TYPE_SENSE_MASK; > > + > > + if (type == IRQ_TYPE_EDGE_BOTH) @@ -289,7 +289,7 @@ To be fair, it was your idea initially :P > > + spin_lock_irqsave(&ctl->lock, flags); > > + > > + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, -> > + ???REG_EDGE_POL_MASK(channel), val); +> > + REG_EDGE_POL_MASK(channel), val); > > + > > + spin_unlock_irqrestore(&ctl->lock, flags); > > + @@ -303,9 +303,9 @@ To be fair, it was your idea initially :P > > + type &= ~IRQ_TYPE_SENSE_MASK; > > + > > + /* -> > + ?* The polarity of the signal provided to the GIC should always -> > + ?* be high. -> > + ?*/ +> > + * The polarity of the signal provided to the GIC should always +> > + * be high. +> > + */ > > + if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) > > + type |= IRQ_TYPE_LEVEL_HIGH; > > + else if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) @@ -343,9 +343,9 @@ To be fair, it was your idea initially :P > > +}; > > + > > +static int meson_gpio_irq_domain_translate(struct irq_domain *domain, -> > + ???struct irq_fwspec *fwspec, -> > + ???unsigned long *hwirq, -> > + ???unsigned int *type) +> > + struct irq_fwspec *fwspec, +> > + unsigned long *hwirq, +> > + unsigned int *type) > > +{ > > + if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) { > > + *hwirq = fwspec->param[0]; @@ -357,9 +357,9 @@ To be fair, it was your idea initially :P > > +} > > + > > +static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain, -> > + ???unsigned int virq, -> > + ???u32 hwirq, -> > + ???unsigned int type) +> > + unsigned int virq, +> > + u32 hwirq, +> > + unsigned int type) > > +{ > > + struct irq_fwspec fwspec; > > + @@ -373,9 +373,9 @@ To be fair, it was your idea initially :P > > +} > > + > > +static int meson_gpio_irq_domain_alloc(struct irq_domain *domain, -> > + ???????unsigned int virq, -> > + ???????unsigned int nr_irqs, -> > + ???????void *data) +> > + unsigned int virq, +> > + unsigned int nr_irqs, +> > + void *data) > > +{ > > + struct irq_fwspec *fwspec = data; > > + struct meson_gpio_irq_controller *ctl = domain->host_data; @@ -397,7 +397,7 @@ To be fair, it was your idea initially :P > > + return ret; > > + > > + ret = meson_gpio_irq_allocate_gic_irq(domain, virq, -> > + ??????*parent_hwirq, type); +> > + *parent_hwirq, type); > > + if (ret < 0) { > > + pr_err("failed to allocate gic irq %u\n", *parent_hwirq); > @@ -410,14 +410,14 @@ Oops ... > > + } > > + > > + irq_domain_set_hwirq_and_chip(domain, virq, hwirq, -> > + ??????&meson_gpio_irq_chip, parent_hwirq); +> > + &meson_gpio_irq_chip, parent_hwirq); > > + > > + return 0; > > +} > > + > > +static void meson_gpio_irq_domain_free(struct irq_domain *domain, -> > + ???????unsigned int virq, -> > + ???????unsigned int nr_irqs) +> > + unsigned int virq, +> > + unsigned int nr_irqs) > > +{ > > + struct meson_gpio_irq_controller *ctl = domain->host_data; > > + struct irq_data *irq_data; @@ -441,7 +441,7 @@ Oops ... > > +}; > > + > > +static int __init meson_gpio_irq_parse_dt(struct device_node *node, -> > + ??struct meson_gpio_irq_controller +> > + struct meson_gpio_irq_controller > > *ctl) > > +{ > > + const struct of_device_id *match; @@ -456,11 +456,11 @@ Oops ... > > + ctl->nr_hwirq = params->nr_hwirq; > > + > > + ret = of_property_read_variable_u32_array(node, -> > + ??"amlogic,upstream- +> > + "amlogic,upstream- > > interrupts", -> > + ??ctl->upstream_irq, -> > + ??NUM_UPSTREAM_IRQ, -> > + ??NUM_UPSTREAM_IRQ); +> > + ctl->upstream_irq, +> > + NUM_UPSTREAM_IRQ, +> > + NUM_UPSTREAM_IRQ); > > + if (ret < 0) { > > + pr_err("can't get %d upstream interrupts\n", > > NUM_UPSTREAM_IRQ); @@ -471,7 +471,7 @@ Oops ... > > +} > > + > > +static int __init meson_gpio_irq_of_init(struct device_node *node, -> > + ?struct device_node *parent) +> > + struct device_node *parent) > > +{ > > + struct irq_domain *domain, *parent_domain; > > + struct meson_gpio_irq_controller *ctl; @@ -514,9 +514,9 @@ indeed > > + > > + domain = irq_domain_create_hierarchy(parent_domain, 0, ctl- > > >nr_hwirq, -> > + ?????of_node_to_fwnode(node), -> > + ?????&meson_gpio_irq_domain_ops, -> > + ?????ctl); +> > + of_node_to_fwnode(node), +> > + &meson_gpio_irq_domain_ops, +> > + ctl); > > + if (!domain) { > > + pr_err("failed to add domain\n"); > > + ret = -ENODEV; diff --git a/a/content_digest b/N3/content_digest index 5b4ee03..d658e3d 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -1,10 +1,19 @@ "ref\020170615161804.32658-1-jbrunet@baylibre.com\0" "ref\020170615161804.32658-3-jbrunet@baylibre.com\0" "ref\0d37dae42-77df-72b7-0898-a4873ccbbcce@arm.com\0" - "From\0jbrunet@baylibre.com (Jerome Brunet)\0" - "Subject\0[PATCH v3 2/6] irqchip: meson: add support for gpio interrupt controller\0" + "From\0Jerome Brunet <jbrunet@baylibre.com>\0" + "Subject\0Re: [PATCH v3 2/6] irqchip: meson: add support for gpio interrupt controller\0" "Date\0Fri, 16 Jun 2017 12:02:55 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Marc Zyngier <marc.zyngier@arm.com>" + Jason Cooper <jason@lakedaemon.net> + Thomas Gleixner <tglx@linutronix.de> + " Kevin Hilman <khilman@baylibre.com>\0" + "Cc\0Carlo Caione <carlo@caione.org>" + linux-amlogic@lists.infradead.org + linux-arm-kernel@lists.infradead.org + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + " Heiner Kallweit <hkallweit1@gmail.com>\0" "\00:1\0" "b\0" "On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote:\n" @@ -22,38 +31,38 @@ "> > \n" "> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>\n" "> > ---\n" - "> > ?drivers/irqchip/Kconfig??????????|???8 +\n" - "> > ?drivers/irqchip/Makefile?????????|???1 +\n" - "> > ?drivers/irqchip/irq-meson-gpio.c | 407\n" + "> > \302\240drivers/irqchip/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\240\302\2408 +\n" + "> > \302\240drivers/irqchip/Makefile\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\240\302\2401 +\n" + "> > \302\240drivers/irqchip/irq-meson-gpio.c | 407\n" "> > +++++++++++++++++++++++++++++++++++++++\n" - "> > ?3 files changed, 416 insertions(+)\n" - "> > ?create mode 100644 drivers/irqchip/irq-meson-gpio.c\n" + "> > \302\2403 files changed, 416 insertions(+)\n" + "> > \302\240create mode 100644 drivers/irqchip/irq-meson-gpio.c\n" "> > \n" "> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig\n" "> > index 478f8ace2664..be577a7512cc 100644\n" "> > --- a/drivers/irqchip/Kconfig\n" "> > +++ b/drivers/irqchip/Kconfig\n" "> > @@ -301,3 +301,11 @@ config QCOM_IRQ_COMBINER\n" - "> > ?\thelp\n" - "> > ?\t??Say yes here to add support for the IRQ combiner devices embedded\n" - "> > ?\t??in Qualcomm Technologies chips.\n" + "> > \302\240\thelp\n" + "> > \302\240\t\302\240\302\240Say yes here to add support for the IRQ combiner devices embedded\n" + "> > \302\240\t\302\240\302\240in Qualcomm Technologies chips.\n" "> > +\n" "> > +config MESON_IRQ_GPIO\n" - "> > +???????bool \"Meson GPIO Interrupt Multiplexer\"\n" - "> > +???????depends on ARCH_MESON || COMPILE_TEST\n" - "> > +???????select IRQ_DOMAIN\n" - "> > +???????select IRQ_DOMAIN_HIERARCHY\n" - "> > +???????help\n" - "> > +?????????Support Meson SoC Family GPIO Interrupt Multiplexer\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240bool \"Meson GPIO Interrupt Multiplexer\"\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on ARCH_MESON || COMPILE_TEST\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240select IRQ_DOMAIN\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240select IRQ_DOMAIN_HIERARCHY\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240help\n" + "> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240Support Meson SoC Family GPIO Interrupt Multiplexer\n" "> > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile\n" "> > index b64c59b838a0..95bf2715850e 100644\n" "> > --- a/drivers/irqchip/Makefile\n" "> > +++ b/drivers/irqchip/Makefile\n" "> > @@ -76,3 +76,4 @@ obj-$(CONFIG_EZNPS_GIC)\t\t\t+= irq-\n" "> > eznps.o\n" - "> > ?obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-vic.o\n" - "> > ?obj-$(CONFIG_STM32_EXTI)?\t\t+= irq-stm32-exti.o\n" - "> > ?obj-$(CONFIG_QCOM_IRQ_COMBINER)\t\t+= qcom-irq-combiner.o\n" + "> > \302\240obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-vic.o\n" + "> > \302\240obj-$(CONFIG_STM32_EXTI)\302\240\t\t+= irq-stm32-exti.o\n" + "> > \302\240obj-$(CONFIG_QCOM_IRQ_COMBINER)\t\t+= qcom-irq-combiner.o\n" "> > +obj-$(CONFIG_MESON_IRQ_GPIO)\t\t+= irq-meson-gpio.o\n" "> > diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-\n" "> > gpio.c\n" @@ -74,7 +83,7 @@ "> > + *\n" "> > + * This program is distributed in the hope that it will be useful, but\n" "> > + * WITHOUT ANY WARRANTY; without even the implied warranty of\n" - "> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the GNU\n" + "> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\302\240\302\240See the GNU\n" "> > + * General Public License for more details.\n" "> > + *\n" "> > + * You should have received a copy of the GNU General Public License\n" @@ -153,8 +162,8 @@ "\n" "Also, there this comment in \"include/linux/bitmap.h\" :\n" "\n" - "?* Note that nbits should be always a compile time evaluable constant.\n" - "?* Otherwise many inlines will generate horrible code.\n" + "\302\240* Note that nbits should be always a compile time evaluable constant.\n" + "\302\240* Otherwise many inlines will generate horrible code.\n" "\n" "Finally there was your advice from the v2 to not make the driver unnecessarily\n" "complicated.\n" @@ -171,7 +180,7 @@ "> > +\n" "> > +static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller\n" "> > *ctl,\n" - "> > +\t\t\t\t???????unsigned int reg, u32 mask, u32 val)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int reg, u32 mask, u32 val)\n" "> > +{\n" "> > +\tu32 tmp;\n" "> > +\n" @@ -183,8 +192,8 @@ "> > +\n" "> > +static int\n" "> > +meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,\n" - "> > +\t\t\t???????unsigned long??hwirq,\n" - "> > +\t\t\t???????u32 **parent_hwirq)\n" + "> > +\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned long\302\240\302\240hwirq,\n" + "> > +\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 **parent_hwirq)\n" "> > +{\n" "> > +\tunsigned int reg, channel;\n" "> > +\tunsigned long flags;\n" @@ -215,9 +224,9 @@ "> > +\tset_bit(channel, ctl->map);\n" "> > +\n" "> > +\t/*\n" - "> > +\t?* Setup the mux of the channel to route the signal of the pad\n" - "> > +\t?* to the appropriate input of the GIC\n" - "> > +\t?*/\n" + "> > +\t\302\240* Setup the mux of the channel to route the signal of the pad\n" + "> > +\t\302\240* to the appropriate input of the GIC\n" + "> > +\t\302\240*/\n" "> > +\treg = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;\n" "> \n" "> Make a helper for this (channel_to_reg?).\n" @@ -226,8 +235,8 @@ "\n" "> \n" "> > +\tmeson_gpio_irq_update_bits(ctl, reg,\n" - "> > +\t\t\t\t???0xff << REG_PIN_SEL_SHIFT(channel),\n" - "> > +\t\t\t\t???hwirq << REG_PIN_SEL_SHIFT(channel));\n" + "> > +\t\t\t\t\302\240\302\240\302\2400xff << REG_PIN_SEL_SHIFT(channel),\n" + "> > +\t\t\t\t\302\240\302\240\302\240hwirq << REG_PIN_SEL_SHIFT(channel));\n" "> > +\n" "> > +\t/* Get the parent hwirq number assigned to this channel */\n" "> > +\t*parent_hwirq = &(ctl->upstream_irq[channel]);\n" @@ -243,21 +252,21 @@ "> > +\tspin_unlock_irqrestore(&ctl->lock, flags);\n" "> > +\n" "> > +\tpr_debug(\"hwirq %lu assigned to channel %d - parent %u\\n\",\n" - "> > +\t\t?hwirq, channel, **parent_hwirq);\n" + "> > +\t\t\302\240hwirq, channel, **parent_hwirq);\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" "> > +static unsigned int\n" "> > +meson_gpio_irq_get_channel(struct meson_gpio_irq_controller *ctl,\n" - "> > +\t\t\t???u32 *parent_hwirq)\n" + "> > +\t\t\t\302\240\302\240\302\240u32 *parent_hwirq)\n" "> > +{\n" "> > +\treturn parent_hwirq - ctl->upstream_irq;\n" "> > +}\n" "> > +\n" "> > +static void\n" "> > +meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,\n" - "> > +\t\t\t???????u32 *parent_hwirq)\n" + "> > +\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 *parent_hwirq)\n" "> > +{\n" "> > +\tunsigned int channel;\n" "> > +\n" @@ -266,8 +275,8 @@ "> > +}\n" "> > +\n" "> > +static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,\n" - "> > +\t\t\t\t?????unsigned int type,\n" - "> > +\t\t\t\t?????u32 *parent_hwirq)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240unsigned int type,\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240u32 *parent_hwirq)\n" "> > +{\n" "> > +\tu32 val = 0;\n" "> > +\tunsigned int channel;\n" @@ -276,14 +285,14 @@ "> > +\tchannel = meson_gpio_irq_get_channel(ctl, parent_hwirq);\n" "> > +\n" "> > +\t/*\n" - "> > +\t?* The controller has a filter block to operate in either LEVEL or\n" - "> > +\t?* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW\n" + "> > +\t\302\240* The controller has a filter block to operate in either LEVEL or\n" + "> > +\t\302\240* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW\n" "> > and\n" - "> > +\t?* EDGE_FALLING support (which the GIC does not support), the\n" + "> > +\t\302\240* EDGE_FALLING support (which the GIC does not support), the\n" "> > filter\n" - "> > +\t?* block is also able to invert the input signal it gets before\n" - "> > +\t?* providing it to the GIC.\n" - "> > +\t?*/\n" + "> > +\t\302\240* block is also able to invert the input signal it gets before\n" + "> > +\t\302\240* providing it to the GIC.\n" + "> > +\t\302\240*/\n" "> > +\ttype &= IRQ_TYPE_SENSE_MASK;\n" "> > +\n" "> > +\tif (type == IRQ_TYPE_EDGE_BOTH)\n" @@ -298,7 +307,7 @@ "> > +\tspin_lock_irqsave(&ctl->lock, flags);\n" "> > +\n" "> > +\tmeson_gpio_irq_update_bits(ctl, REG_EDGE_POL,\n" - "> > +\t\t\t\t???REG_EDGE_POL_MASK(channel), val);\n" + "> > +\t\t\t\t\302\240\302\240\302\240REG_EDGE_POL_MASK(channel), val);\n" "> > +\n" "> > +\tspin_unlock_irqrestore(&ctl->lock, flags);\n" "> > +\n" @@ -312,9 +321,9 @@ "> > +\ttype &= ~IRQ_TYPE_SENSE_MASK;\n" "> > +\n" "> > +\t/*\n" - "> > +\t?* The polarity of the signal provided to the GIC should always\n" - "> > +\t?* be high.\n" - "> > +\t?*/\n" + "> > +\t\302\240* The polarity of the signal provided to the GIC should always\n" + "> > +\t\302\240* be high.\n" + "> > +\t\302\240*/\n" "> > +\tif (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))\n" "> > +\t\ttype |= IRQ_TYPE_LEVEL_HIGH;\n" "> > +\telse if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))\n" @@ -352,9 +361,9 @@ "> > +};\n" "> > +\n" "> > +static int meson_gpio_irq_domain_translate(struct irq_domain *domain,\n" - "> > +\t\t\t\t\t???struct irq_fwspec *fwspec,\n" - "> > +\t\t\t\t\t???unsigned long *hwirq,\n" - "> > +\t\t\t\t\t???unsigned int *type)\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240struct irq_fwspec *fwspec,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240unsigned long *hwirq,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240unsigned int *type)\n" "> > +{\n" "> > +\tif (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {\n" "> > +\t\t*hwirq\t= fwspec->param[0];\n" @@ -366,9 +375,9 @@ "> > +}\n" "> > +\n" "> > +static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,\n" - "> > +\t\t\t\t\t???unsigned int virq,\n" - "> > +\t\t\t\t\t???u32 hwirq,\n" - "> > +\t\t\t\t\t???unsigned int type)\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240unsigned int virq,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240u32 hwirq,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240unsigned int type)\n" "> > +{\n" "> > +\tstruct irq_fwspec fwspec;\n" "> > +\n" @@ -382,9 +391,9 @@ "> > +}\n" "> > +\n" "> > +static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,\n" - "> > +\t\t\t\t???????unsigned int virq,\n" - "> > +\t\t\t\t???????unsigned int nr_irqs,\n" - "> > +\t\t\t\t???????void *data)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int virq,\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int nr_irqs,\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240void *data)\n" "> > +{\n" "> > +\tstruct irq_fwspec *fwspec = data;\n" "> > +\tstruct meson_gpio_irq_controller *ctl = domain->host_data;\n" @@ -406,7 +415,7 @@ "> > +\t\treturn ret;\n" "> > +\n" "> > +\tret = meson_gpio_irq_allocate_gic_irq(domain, virq,\n" - "> > +\t\t\t\t\t??????*parent_hwirq, type);\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240*parent_hwirq, type);\n" "> > +\tif (ret < 0) {\n" "> > +\t\tpr_err(\"failed to allocate gic irq %u\\n\", *parent_hwirq);\n" "> \n" @@ -419,14 +428,14 @@ "> > +\t}\n" "> > +\n" "> > +\tirq_domain_set_hwirq_and_chip(domain, virq, hwirq,\n" - "> > +\t\t\t\t??????&meson_gpio_irq_chip, parent_hwirq);\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240&meson_gpio_irq_chip, parent_hwirq);\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" "> > +static void meson_gpio_irq_domain_free(struct irq_domain *domain,\n" - "> > +\t\t\t\t???????unsigned int virq,\n" - "> > +\t\t\t\t???????unsigned int nr_irqs)\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int virq,\n" + "> > +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned int nr_irqs)\n" "> > +{\n" "> > +\tstruct meson_gpio_irq_controller *ctl = domain->host_data;\n" "> > +\tstruct irq_data *irq_data;\n" @@ -450,7 +459,7 @@ "> > +};\n" "> > +\n" "> > +static int __init meson_gpio_irq_parse_dt(struct device_node *node,\n" - "> > +\t\t\t\t\t??struct meson_gpio_irq_controller\n" + "> > +\t\t\t\t\t\302\240\302\240struct meson_gpio_irq_controller\n" "> > *ctl)\n" "> > +{\n" "> > +\tconst struct of_device_id *match;\n" @@ -465,11 +474,11 @@ "> > +\tctl->nr_hwirq = params->nr_hwirq;\n" "> > +\n" "> > +\tret = of_property_read_variable_u32_array(node,\n" - "> > +\t\t\t\t\t\t??\"amlogic,upstream-\n" + "> > +\t\t\t\t\t\t\302\240\302\240\"amlogic,upstream-\n" "> > interrupts\",\n" - "> > +\t\t\t\t\t\t??ctl->upstream_irq,\n" - "> > +\t\t\t\t\t\t??NUM_UPSTREAM_IRQ,\n" - "> > +\t\t\t\t\t\t??NUM_UPSTREAM_IRQ);\n" + "> > +\t\t\t\t\t\t\302\240\302\240ctl->upstream_irq,\n" + "> > +\t\t\t\t\t\t\302\240\302\240NUM_UPSTREAM_IRQ,\n" + "> > +\t\t\t\t\t\t\302\240\302\240NUM_UPSTREAM_IRQ);\n" "> > +\tif (ret < 0) {\n" "> > +\t\tpr_err(\"can't get %d upstream interrupts\\n\",\n" "> > NUM_UPSTREAM_IRQ);\n" @@ -480,7 +489,7 @@ "> > +}\n" "> > +\n" "> > +static int __init meson_gpio_irq_of_init(struct device_node *node,\n" - "> > +\t\t\t\t\t?struct device_node *parent)\n" + "> > +\t\t\t\t\t\302\240struct device_node *parent)\n" "> > +{\n" "> > +\tstruct irq_domain *domain, *parent_domain;\n" "> > +\tstruct meson_gpio_irq_controller *ctl;\n" @@ -523,9 +532,9 @@ "> > +\n" "> > +\tdomain = irq_domain_create_hierarchy(parent_domain, 0, ctl-\n" "> > >nr_hwirq,\n" - "> > +\t\t\t\t\t?????of_node_to_fwnode(node),\n" - "> > +\t\t\t\t\t?????&meson_gpio_irq_domain_ops,\n" - "> > +\t\t\t\t\t?????ctl);\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240\302\240\302\240of_node_to_fwnode(node),\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240\302\240\302\240&meson_gpio_irq_domain_ops,\n" + "> > +\t\t\t\t\t\302\240\302\240\302\240\302\240\302\240ctl);\n" "> > +\tif (!domain) {\n" "> > +\t\tpr_err(\"failed to add domain\\n\");\n" "> > +\t\tret = -ENODEV;\n" @@ -560,4 +569,4 @@ "> \n" "> \tM." -31fa1c18ca35de05ce9bcb1a2e58051b2d1c8b5188cdf19a2b256239167197ba +4dde6cb9c7eccca550eb572ae1fd7df1f48262c0ea2bfe1a085ca6050d21e1f8
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