From: <gregkh@linuxfoundation.org>
To: wens@csie.org, gregkh@linuxfoundation.org,
maxime.ripard@free-electrons.com, rah@settrans.net
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset" has been added to the 4.11-stable tree
Date: Mon, 26 Jun 2017 08:15:29 +0200 [thread overview]
Message-ID: <149845772918996@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
to the 4.11-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-sunxi-ng-a31-correct-lcd1-ch1-clock-register-offset.patch
and it can be found in the queue-4.11 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From 38b8f823864707eb1cf331d2247608c419ed388c Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 3 May 2017 11:13:46 +0800
Subject: clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
From: Chen-Yu Tsai <wens@csie.org>
commit 38b8f823864707eb1cf331d2247608c419ed388c upstream.
The register offset for the lcd1-ch1 clock was incorrectly pointing to
the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled
when the clk core disables unused clocks. This then stops the simplefb
HDMI output path.
Reported-by: Bob Ham <rah@settrans.net>
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -556,7 +556,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch
0x12c, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
- 0x12c, 0, 4, 24, 3, BIT(31),
+ 0x130, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
Patches currently in stable-queue which might be from wens@csie.org are
queue-4.11/clk-sunxi-ng-a31-correct-lcd1-ch1-clock-register-offset.patch
queue-4.11/clk-sunxi-ng-sun5i-fix-ahb_bist_clk-definition.patch
reply other threads:[~2017-06-26 6:41 UTC|newest]
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