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Tue, 14 May 2024 02:10:59 -0700 (PDT) Message-ID: <14e88990-963c-45ef-bf51-662d54857c6e@ventanamicro.com> Date: Tue, 14 May 2024 06:10:53 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/riscv: rvzicbo: Fixup CBO extension register calculation To: Alistair Francis , qemu-riscv@nongnu.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-devel@nongnu.org Cc: Alistair Francis , fabian.thomas@cispa.de, Bin Meng , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson References: <20240514023910.301766-1-alistair.francis@wdc.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20240514023910.301766-1-alistair.francis@wdc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 5/13/24 23:39, Alistair Francis wrote: > When running the instruction > > ``` > cbo.flush 0(x0) > ``` > > QEMU would segfault. > > The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0] > allocated. > > In order to fix this let's use the existing get_address() > helper. This also has the benefit of performing pointer mask > calculations on the address specified in rs1. > > The pointer masking specificiation specifically states: > > """ > Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz > """ > > So this is the correct behaviour and we previously have been incorrectly > not masking the address. > > Signed-off-by: Alistair Francis > Reported-by: Fabian Thomas > Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension") > --- LGTM but I wonder if this is the same fix as this one sent by Phil a month ago or so: https://lore.kernel.org/qemu-riscv/20240419110514.69697-1-philmd@linaro.org/ ("[PATCH] target/riscv: Use get_address() to get address with Zicbom extensions") Thanks, Daniel > target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc > index d5d7095903..15711c3140 100644 > --- a/target/riscv/insn_trans/trans_rvzicbo.c.inc > +++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc > @@ -31,27 +31,35 @@ > static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a) > { > REQUIRE_ZICBOM(ctx); > - gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]); > + TCGv src = get_address(ctx, a->rs1, 0); > + > + gen_helper_cbo_clean_flush(tcg_env, src); > return true; > } > > static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a) > { > REQUIRE_ZICBOM(ctx); > - gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]); > + TCGv src = get_address(ctx, a->rs1, 0); > + > + gen_helper_cbo_clean_flush(tcg_env, src); > return true; > } > > static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a) > { > REQUIRE_ZICBOM(ctx); > - gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]); > + TCGv src = get_address(ctx, a->rs1, 0); > + > + gen_helper_cbo_inval(tcg_env, src); > return true; > } > > static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a) > { > REQUIRE_ZICBOZ(ctx); > - gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]); > + TCGv src = get_address(ctx, a->rs1, 0); > + > + gen_helper_cbo_zero(tcg_env, src); > return true; > }