diff for duplicates of <1500474869.8952.5.camel@nxp.com>

diff --git a/a/1.txt b/N1/1.txt
index 4df7ba7..e058b37 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,114 +1,157 @@
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+On Ma, 2017-07-18 at 16:10 -0700, Stephen Boyd wrote:
+> On 07/18, Adriana Reus wrote:
+> > 
+> > IMX7d does not have an M0 Core and this particular
+> > clock doesn't seem connected to anything else.
+> > Remove this entry from the CCM driver and fix index
+> > for the remaining clocks.
+> > 
+> > Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
+> [...]
+> > 
+> > +#define IMX7D_GPT2_ROOT_DIV		305
+> > +#define IMX7D_GPT3_ROOT_CLK		306
+> > +#define IMX7D_GPT3_ROOT_SRC		307
+> > +#define IMX7D_GPT3_ROOT_CG		308
+> > +#define IMX7D_GPT3_ROOT_DIV		309
+> > +#define IMX7D_GPT4_ROOT_CLK		310
+> > +#define IMX7D_GPT4_ROOT_SRC		311
+> > +#define IMX7D_GPT4_ROOT_CG		312
+> > +#define IMX7D_GPT4_ROOT_DIV		313
+> > +#define IMX7D_TRACE_ROOT_CLK		314
+> > +#define IMX7D_TRACE_ROOT_SRC		315
+> > +#define IMX7D_TRACE_ROOT_CG		316
+> > +#define IMX7D_TRACE_ROOT_DIV		317
+> > +#define IMX7D_WDOG1_ROOT_CLK		318
+> > +#define IMX7D_WDOG_ROOT_SRC		319
+> > +#define IMX7D_WDOG_ROOT_CG		320
+> > +#define IMX7D_WDOG_ROOT_DIV		321
+> > +#define IMX7D_CSI_MCLK_ROOT_CLK		322
+> > +#define IMX7D_CSI_MCLK_ROOT_SRC		323
+> > +#define IMX7D_CSI_MCLK_ROOT_CG		324
+> > +#define IMX7D_CSI_MCLK_ROOT_DIV		325
+> > +#define IMX7D_AUDIO_MCLK_ROOT_CLK	326
+> > +#define IMX7D_AUDIO_MCLK_ROOT_SRC	327
+> > +#define IMX7D_AUDIO_MCLK_ROOT_CG	328
+> > +#define IMX7D_AUDIO_MCLK_ROOT_DIV	329
+> > +#define IMX7D_WRCLK_ROOT_CLK		330
+> > +#define IMX7D_WRCLK_ROOT_SRC		331
+> > +#define IMX7D_WRCLK_ROOT_CG		332
+> > +#define IMX7D_WRCLK_ROOT_DIV		333
+> > +#define IMX7D_CLKO1_ROOT_SRC		334
+> > +#define IMX7D_CLKO1_ROOT_CG		335
+> > +#define IMX7D_CLKO1_ROOT_DIV		336
+> > +#define IMX7D_CLKO2_ROOT_SRC		337
+> > +#define IMX7D_CLKO2_ROOT_CG		338
+> > +#define IMX7D_CLKO2_ROOT_DIV		339
+> > +#define IMX7D_MAIN_AXI_ROOT_PRE_DIV	340
+> > +#define IMX7D_DISP_AXI_ROOT_PRE_DIV	341
+> > +#define IMX7D_ENET_AXI_ROOT_PRE_DIV	342
+> > +#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 343
+> > +#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV	344
+> > +#define IMX7D_USB_HSIC_ROOT_PRE_DIV	345
+> > +#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV	346
+> > +#define IMX7D_PCIE_PHY_ROOT_PRE_DIV	347
+> > +#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV	348
+> > +#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV	349
+> > +#define IMX7D_MIPI_DSI_ROOT_PRE_DIV	350
+> > +#define IMX7D_MIPI_CSI_ROOT_PRE_DIV	351
+> > +#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV	352
+> > +#define IMX7D_SAI1_ROOT_PRE_DIV		353
+> > +#define IMX7D_SAI2_ROOT_PRE_DIV		354
+> > +#define IMX7D_SAI3_ROOT_PRE_DIV		355
+> > +#define IMX7D_SPDIF_ROOT_PRE_DIV	356
+> > +#define IMX7D_ENET1_REF_ROOT_PRE_DIV	357
+> > +#define IMX7D_ENET1_TIME_ROOT_PRE_DIV	358
+> > +#define IMX7D_ENET2_REF_ROOT_PRE_DIV	359
+> > +#define IMX7D_ENET2_TIME_ROOT_PRE_DIV	360
+> > +#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 361
+> > +#define IMX7D_EIM_ROOT_PRE_DIV		362
+> > +#define IMX7D_NAND_ROOT_PRE_DIV		363
+> > +#define IMX7D_QSPI_ROOT_PRE_DIV		364
+> > +#define IMX7D_USDHC1_ROOT_PRE_DIV	365
+> > +#define IMX7D_USDHC2_ROOT_PRE_DIV	366
+> > +#define IMX7D_USDHC3_ROOT_PRE_DIV	367
+> > +#define IMX7D_CAN1_ROOT_PRE_DIV		368
+> > +#define IMX7D_CAN2_ROOT_PRE_DIV		369
+> > +#define IMX7D_I2C1_ROOT_PRE_DIV		370
+> > +#define IMX7D_I2C2_ROOT_PRE_DIV		371
+> > +#define IMX7D_I2C3_ROOT_PRE_DIV		372
+> > +#define IMX7D_I2C4_ROOT_PRE_DIV		373
+> > +#define IMX7D_UART1_ROOT_PRE_DIV	374
+> > +#define IMX7D_UART2_ROOT_PRE_DIV	375
+> > +#define IMX7D_UART3_ROOT_PRE_DIV	376
+> > +#define IMX7D_UART4_ROOT_PRE_DIV	377
+> > +#define IMX7D_UART5_ROOT_PRE_DIV	378
+> > +#define IMX7D_UART6_ROOT_PRE_DIV	379
+> > +#define IMX7D_UART7_ROOT_PRE_DIV	380
+> > +#define IMX7D_ECSPI1_ROOT_PRE_DIV	381
+> > +#define IMX7D_ECSPI2_ROOT_PRE_DIV	382
+> > +#define IMX7D_ECSPI3_ROOT_PRE_DIV	383
+> > +#define IMX7D_ECSPI4_ROOT_PRE_DIV	384
+> > +#define IMX7D_PWM1_ROOT_PRE_DIV		385
+> > +#define IMX7D_PWM2_ROOT_PRE_DIV		386
+> > +#define IMX7D_PWM3_ROOT_PRE_DIV		387
+> > +#define IMX7D_PWM4_ROOT_PRE_DIV		388
+> > +#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV	389
+> > +#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV	390
+> > +#define IMX7D_SIM1_ROOT_PRE_DIV		391
+> > +#define IMX7D_SIM2_ROOT_PRE_DIV		392
+> > +#define IMX7D_GPT1_ROOT_PRE_DIV		393
+> > +#define IMX7D_GPT2_ROOT_PRE_DIV		394
+> > +#define IMX7D_GPT3_ROOT_PRE_DIV		395
+> > +#define IMX7D_GPT4_ROOT_PRE_DIV		396
+> > +#define IMX7D_TRACE_ROOT_PRE_DIV	397
+> > +#define IMX7D_WDOG_ROOT_PRE_DIV		398
+> > +#define IMX7D_CSI_MCLK_ROOT_PRE_DIV	399
+> > +#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV	400
+> > +#define IMX7D_WRCLK_ROOT_PRE_DIV	401
+> > +#define IMX7D_CLKO1_ROOT_PRE_DIV	402
+> > +#define IMX7D_CLKO2_ROOT_PRE_DIV	403
+> > +#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 404
+> > +#define IMX7D_DRAM_ALT_ROOT_PRE_DIV	405
+> > +#define IMX7D_LVDS1_IN_CLK		406
+> > +#define IMX7D_LVDS1_OUT_SEL		407
+> > +#define IMX7D_LVDS1_OUT_CLK		408
+> > +#define IMX7D_CLK_DUMMY			409
+> > +#define IMX7D_GPT_3M_CLK		410
+> > +#define IMX7D_OCRAM_CLK			411
+> > +#define IMX7D_OCRAM_S_CLK		412
+> > +#define IMX7D_WDOG2_ROOT_CLK		413
+> > +#define IMX7D_WDOG3_ROOT_CLK		414
+> > +#define IMX7D_WDOG4_ROOT_CLK		415
+> > +#define IMX7D_SDMA_CORE_CLK		416
+> > +#define IMX7D_USB1_MAIN_480M_CLK	417
+> > +#define IMX7D_USB_CTRL_CLK		418
+> > +#define IMX7D_USB_PHY1_CLK		419
+> > +#define IMX7D_USB_PHY2_CLK		420
+> > +#define IMX7D_IPG_ROOT_CLK		421
+> > +#define IMX7D_SAI1_IPG_CLK		422
+> > +#define IMX7D_SAI2_IPG_CLK		423
+> > +#define IMX7D_SAI3_IPG_CLK		424
+> > +#define IMX7D_PLL_AUDIO_TEST_DIV	425
+> > +#define IMX7D_PLL_AUDIO_POST_DIV	426
+> > +#define IMX7D_PLL_VIDEO_TEST_DIV	427
+> > +#define IMX7D_PLL_VIDEO_POST_DIV	428
+> > +#define IMX7D_MU_ROOT_CLK		429
+> > +#define IMX7D_SEMA4_HS_ROOT_CLK		430
+> > +#define IMX7D_PLL_DRAM_TEST_DIV		431
+> > +#define IMX7D_ADC_ROOT_CLK		432
+> > +#define IMX7D_CLK_ARM			433
+> > +#define IMX7D_CKIL			434
+> > +#define IMX7D_OCOTP_CLK			435
+> > +#define IMX7D_NAND_RAWNAND_CLK		436
+> > +#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 437
+> > +#define IMX7D_CLK_END			438
+> > ?#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
+> 
+> Are any of these defines being used already? Please just leave
+> the numbers intact and make the ones that don't exist go to
+> /dev/null in the driver. That way, we don't break some ABI where
+> people were expecting raw numbers to work still.
+> 
+They're used in the dts file for imx7 but as defines not as raw
+values. It's best to be on the safe side though so I'll leave them
+alone and send v2.
+
+Thank you
diff --git a/a/content_digest b/N1/content_digest
index dd32154..9b8477a 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,133 +1,168 @@
  "ref\01500363892-1173-1-git-send-email-adriana.reus@nxp.com\0"
  "ref\01500363892-1173-3-git-send-email-adriana.reus@nxp.com\0"
  "ref\020170718231041.GF18179@codeaurora.org\0"
- "From\0Adriana Reus <adriana.reus@nxp.com>\0"
- "Subject\0Re: [PATCH 2/2] clk: imx: imx7d: Remove ARM_M0 clock\0"
+ "From\0adriana.reus@nxp.com (Adriana Reus)\0"
+ "Subject\0[PATCH 2/2] clk: imx: imx7d: Remove ARM_M0 clock\0"
  "Date\0Wed, 19 Jul 2017 14:34:30 +0000\0"
- "To\0sboyd@codeaurora.org <sboyd@codeaurora.org>\0"
- "Cc\0robh+dt@kernel.org <robh+dt@kernel.org>"
-  mturquette@baylibre.com <mturquette@baylibre.com>
-  devicetree@vger.kernel.org <devicetree@vger.kernel.org>
-  Fabio Estevam <fabio.estevam@nxp.com>
-  shawnguo@kernel.org <shawnguo@kernel.org>
-  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
-  Anson Huang <anson.huang@nxp.com>
- " linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
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+ "On Ma, 2017-07-18 at 16:10 -0700, Stephen Boyd wrote:\n"
+ "> On 07/18, Adriana Reus wrote:\n"
+ "> > \n"
+ "> > IMX7d does not have an M0 Core and this particular\n"
+ "> > clock doesn't seem connected to anything else.\n"
+ "> > Remove this entry from the CCM driver and fix index\n"
+ "> > for the remaining clocks.\n"
+ "> > \n"
+ "> > Signed-off-by: Adriana Reus <adriana.reus@nxp.com>\n"
+ "> [...]\n"
+ "> > \n"
+ "> > +#define IMX7D_GPT2_ROOT_DIV\t\t305\n"
+ "> > +#define IMX7D_GPT3_ROOT_CLK\t\t306\n"
+ "> > +#define IMX7D_GPT3_ROOT_SRC\t\t307\n"
+ "> > +#define IMX7D_GPT3_ROOT_CG\t\t308\n"
+ "> > +#define IMX7D_GPT3_ROOT_DIV\t\t309\n"
+ "> > +#define IMX7D_GPT4_ROOT_CLK\t\t310\n"
+ "> > +#define IMX7D_GPT4_ROOT_SRC\t\t311\n"
+ "> > +#define IMX7D_GPT4_ROOT_CG\t\t312\n"
+ "> > +#define IMX7D_GPT4_ROOT_DIV\t\t313\n"
+ "> > +#define IMX7D_TRACE_ROOT_CLK\t\t314\n"
+ "> > +#define IMX7D_TRACE_ROOT_SRC\t\t315\n"
+ "> > +#define IMX7D_TRACE_ROOT_CG\t\t316\n"
+ "> > +#define IMX7D_TRACE_ROOT_DIV\t\t317\n"
+ "> > +#define IMX7D_WDOG1_ROOT_CLK\t\t318\n"
+ "> > +#define IMX7D_WDOG_ROOT_SRC\t\t319\n"
+ "> > +#define IMX7D_WDOG_ROOT_CG\t\t320\n"
+ "> > +#define IMX7D_WDOG_ROOT_DIV\t\t321\n"
+ "> > +#define IMX7D_CSI_MCLK_ROOT_CLK\t\t322\n"
+ "> > +#define IMX7D_CSI_MCLK_ROOT_SRC\t\t323\n"
+ "> > +#define IMX7D_CSI_MCLK_ROOT_CG\t\t324\n"
+ "> > +#define IMX7D_CSI_MCLK_ROOT_DIV\t\t325\n"
+ "> > +#define IMX7D_AUDIO_MCLK_ROOT_CLK\t326\n"
+ "> > +#define IMX7D_AUDIO_MCLK_ROOT_SRC\t327\n"
+ "> > +#define IMX7D_AUDIO_MCLK_ROOT_CG\t328\n"
+ "> > +#define IMX7D_AUDIO_MCLK_ROOT_DIV\t329\n"
+ "> > +#define IMX7D_WRCLK_ROOT_CLK\t\t330\n"
+ "> > +#define IMX7D_WRCLK_ROOT_SRC\t\t331\n"
+ "> > +#define IMX7D_WRCLK_ROOT_CG\t\t332\n"
+ "> > +#define IMX7D_WRCLK_ROOT_DIV\t\t333\n"
+ "> > +#define IMX7D_CLKO1_ROOT_SRC\t\t334\n"
+ "> > +#define IMX7D_CLKO1_ROOT_CG\t\t335\n"
+ "> > +#define IMX7D_CLKO1_ROOT_DIV\t\t336\n"
+ "> > +#define IMX7D_CLKO2_ROOT_SRC\t\t337\n"
+ "> > +#define IMX7D_CLKO2_ROOT_CG\t\t338\n"
+ "> > +#define IMX7D_CLKO2_ROOT_DIV\t\t339\n"
+ "> > +#define IMX7D_MAIN_AXI_ROOT_PRE_DIV\t340\n"
+ "> > +#define IMX7D_DISP_AXI_ROOT_PRE_DIV\t341\n"
+ "> > +#define IMX7D_ENET_AXI_ROOT_PRE_DIV\t342\n"
+ "> > +#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 343\n"
+ "> > +#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV\t344\n"
+ "> > +#define IMX7D_USB_HSIC_ROOT_PRE_DIV\t345\n"
+ "> > +#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV\t346\n"
+ "> > +#define IMX7D_PCIE_PHY_ROOT_PRE_DIV\t347\n"
+ "> > +#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV\t348\n"
+ "> > +#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV\t349\n"
+ "> > +#define IMX7D_MIPI_DSI_ROOT_PRE_DIV\t350\n"
+ "> > +#define IMX7D_MIPI_CSI_ROOT_PRE_DIV\t351\n"
+ "> > +#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV\t352\n"
+ "> > +#define IMX7D_SAI1_ROOT_PRE_DIV\t\t353\n"
+ "> > +#define IMX7D_SAI2_ROOT_PRE_DIV\t\t354\n"
+ "> > +#define IMX7D_SAI3_ROOT_PRE_DIV\t\t355\n"
+ "> > +#define IMX7D_SPDIF_ROOT_PRE_DIV\t356\n"
+ "> > +#define IMX7D_ENET1_REF_ROOT_PRE_DIV\t357\n"
+ "> > +#define IMX7D_ENET1_TIME_ROOT_PRE_DIV\t358\n"
+ "> > +#define IMX7D_ENET2_REF_ROOT_PRE_DIV\t359\n"
+ "> > +#define IMX7D_ENET2_TIME_ROOT_PRE_DIV\t360\n"
+ "> > +#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 361\n"
+ "> > +#define IMX7D_EIM_ROOT_PRE_DIV\t\t362\n"
+ "> > +#define IMX7D_NAND_ROOT_PRE_DIV\t\t363\n"
+ "> > +#define IMX7D_QSPI_ROOT_PRE_DIV\t\t364\n"
+ "> > +#define IMX7D_USDHC1_ROOT_PRE_DIV\t365\n"
+ "> > +#define IMX7D_USDHC2_ROOT_PRE_DIV\t366\n"
+ "> > +#define IMX7D_USDHC3_ROOT_PRE_DIV\t367\n"
+ "> > +#define IMX7D_CAN1_ROOT_PRE_DIV\t\t368\n"
+ "> > +#define IMX7D_CAN2_ROOT_PRE_DIV\t\t369\n"
+ "> > +#define IMX7D_I2C1_ROOT_PRE_DIV\t\t370\n"
+ "> > +#define IMX7D_I2C2_ROOT_PRE_DIV\t\t371\n"
+ "> > +#define IMX7D_I2C3_ROOT_PRE_DIV\t\t372\n"
+ "> > +#define IMX7D_I2C4_ROOT_PRE_DIV\t\t373\n"
+ "> > +#define IMX7D_UART1_ROOT_PRE_DIV\t374\n"
+ "> > +#define IMX7D_UART2_ROOT_PRE_DIV\t375\n"
+ "> > +#define IMX7D_UART3_ROOT_PRE_DIV\t376\n"
+ "> > +#define IMX7D_UART4_ROOT_PRE_DIV\t377\n"
+ "> > +#define IMX7D_UART5_ROOT_PRE_DIV\t378\n"
+ "> > +#define IMX7D_UART6_ROOT_PRE_DIV\t379\n"
+ "> > +#define IMX7D_UART7_ROOT_PRE_DIV\t380\n"
+ "> > +#define IMX7D_ECSPI1_ROOT_PRE_DIV\t381\n"
+ "> > +#define IMX7D_ECSPI2_ROOT_PRE_DIV\t382\n"
+ "> > +#define IMX7D_ECSPI3_ROOT_PRE_DIV\t383\n"
+ "> > +#define IMX7D_ECSPI4_ROOT_PRE_DIV\t384\n"
+ "> > +#define IMX7D_PWM1_ROOT_PRE_DIV\t\t385\n"
+ "> > +#define IMX7D_PWM2_ROOT_PRE_DIV\t\t386\n"
+ "> > +#define IMX7D_PWM3_ROOT_PRE_DIV\t\t387\n"
+ "> > +#define IMX7D_PWM4_ROOT_PRE_DIV\t\t388\n"
+ "> > +#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV\t389\n"
+ "> > +#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV\t390\n"
+ "> > +#define IMX7D_SIM1_ROOT_PRE_DIV\t\t391\n"
+ "> > +#define IMX7D_SIM2_ROOT_PRE_DIV\t\t392\n"
+ "> > +#define IMX7D_GPT1_ROOT_PRE_DIV\t\t393\n"
+ "> > +#define IMX7D_GPT2_ROOT_PRE_DIV\t\t394\n"
+ "> > +#define IMX7D_GPT3_ROOT_PRE_DIV\t\t395\n"
+ "> > +#define IMX7D_GPT4_ROOT_PRE_DIV\t\t396\n"
+ "> > +#define IMX7D_TRACE_ROOT_PRE_DIV\t397\n"
+ "> > +#define IMX7D_WDOG_ROOT_PRE_DIV\t\t398\n"
+ "> > +#define IMX7D_CSI_MCLK_ROOT_PRE_DIV\t399\n"
+ "> > +#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV\t400\n"
+ "> > +#define IMX7D_WRCLK_ROOT_PRE_DIV\t401\n"
+ "> > +#define IMX7D_CLKO1_ROOT_PRE_DIV\t402\n"
+ "> > +#define IMX7D_CLKO2_ROOT_PRE_DIV\t403\n"
+ "> > +#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 404\n"
+ "> > +#define IMX7D_DRAM_ALT_ROOT_PRE_DIV\t405\n"
+ "> > +#define IMX7D_LVDS1_IN_CLK\t\t406\n"
+ "> > +#define IMX7D_LVDS1_OUT_SEL\t\t407\n"
+ "> > +#define IMX7D_LVDS1_OUT_CLK\t\t408\n"
+ "> > +#define IMX7D_CLK_DUMMY\t\t\t409\n"
+ "> > +#define IMX7D_GPT_3M_CLK\t\t410\n"
+ "> > +#define IMX7D_OCRAM_CLK\t\t\t411\n"
+ "> > +#define IMX7D_OCRAM_S_CLK\t\t412\n"
+ "> > +#define IMX7D_WDOG2_ROOT_CLK\t\t413\n"
+ "> > +#define IMX7D_WDOG3_ROOT_CLK\t\t414\n"
+ "> > +#define IMX7D_WDOG4_ROOT_CLK\t\t415\n"
+ "> > +#define IMX7D_SDMA_CORE_CLK\t\t416\n"
+ "> > +#define IMX7D_USB1_MAIN_480M_CLK\t417\n"
+ "> > +#define IMX7D_USB_CTRL_CLK\t\t418\n"
+ "> > +#define IMX7D_USB_PHY1_CLK\t\t419\n"
+ "> > +#define IMX7D_USB_PHY2_CLK\t\t420\n"
+ "> > +#define IMX7D_IPG_ROOT_CLK\t\t421\n"
+ "> > +#define IMX7D_SAI1_IPG_CLK\t\t422\n"
+ "> > +#define IMX7D_SAI2_IPG_CLK\t\t423\n"
+ "> > +#define IMX7D_SAI3_IPG_CLK\t\t424\n"
+ "> > +#define IMX7D_PLL_AUDIO_TEST_DIV\t425\n"
+ "> > +#define IMX7D_PLL_AUDIO_POST_DIV\t426\n"
+ "> > +#define IMX7D_PLL_VIDEO_TEST_DIV\t427\n"
+ "> > +#define IMX7D_PLL_VIDEO_POST_DIV\t428\n"
+ "> > +#define IMX7D_MU_ROOT_CLK\t\t429\n"
+ "> > +#define IMX7D_SEMA4_HS_ROOT_CLK\t\t430\n"
+ "> > +#define IMX7D_PLL_DRAM_TEST_DIV\t\t431\n"
+ "> > +#define IMX7D_ADC_ROOT_CLK\t\t432\n"
+ "> > +#define IMX7D_CLK_ARM\t\t\t433\n"
+ "> > +#define IMX7D_CKIL\t\t\t434\n"
+ "> > +#define IMX7D_OCOTP_CLK\t\t\t435\n"
+ "> > +#define IMX7D_NAND_RAWNAND_CLK\t\t436\n"
+ "> > +#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 437\n"
+ "> > +#define IMX7D_CLK_END\t\t\t438\n"
+ "> > ?#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */\n"
+ "> \n"
+ "> Are any of these defines being used already? Please just leave\n"
+ "> the numbers intact and make the ones that don't exist go to\n"
+ "> /dev/null in the driver. That way, we don't break some ABI where\n"
+ "> people were expecting raw numbers to work still.\n"
+ "> \n"
+ "They're used in the dts file for imx7 but as defines not as raw\n"
+ "values. It's best to be on the safe side though so I'll leave them\n"
+ "alone and send v2.\n"
+ "\n"
+ Thank you
 
-92403f7a5cc5e93df6a0381e71c0118f07a96d305d5c4159f2f5709bd601e57c
+6a7c3ac496b1f226b9380bc2d42523d75686db5422301a4417962b726a270efb
