diff for duplicates of <1501661036.6345.15.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index 1590696..ae8911e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ Hi Vineet, -On Wed, 2017-08-02@09:09 +0530, Vineet Gupta wrote: +On Wed, 2017-08-02 at 09:09 +0530, Vineet Gupta wrote: > On 08/01/2017 03:29 PM, Alexey Brodkin wrote: > > > > It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1 @@ -9,43 +9,43 @@ On Wed, 2017-08-02@09:09 +0530, Vineet Gupta wrote: > > for example on HSDK platform where PAE40 support exists in hardware > > we saw each and every SLC region op to take seconds (sic!). > > -> > Signed-off-by: Alexey Brodkin <abrodkin at synopsys.com> -> > Reported-by: Vladimir Kondratiev <vladimir.kondratiev at intel.com> +> > Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> +> > Reported-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com> > > --- -> > ? arch/arc/include/asm/cache.h | 2 ++ -> > ? arch/arc/mm/cache.c??????????| 8 ++++++-- -> > ? 2 files changed, 8 insertions(+), 2 deletions(-) +> > arch/arc/include/asm/cache.h | 2 ++ +> > arch/arc/mm/cache.c | 8 ++++++-- +> > 2 files changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h > > index 35127ad95124..1f3c2f967471 100644 > > --- a/arch/arc/include/asm/cache.h > > +++ b/arch/arc/include/asm/cache.h > > @@ -91,7 +91,9 @@ extern unsigned long perip_base, perip_end; -> > ? #define ARC_REG_SLC_FLUSH 0x904 -> > ? #define ARC_REG_SLC_INVALIDATE 0x905 -> > ? #define ARC_REG_SLC_RGN_START 0x914 +> > #define ARC_REG_SLC_FLUSH 0x904 +> > #define ARC_REG_SLC_INVALIDATE 0x905 +> > #define ARC_REG_SLC_RGN_START 0x914 > > +#define ARC_REG_SLC_RGN_START1 0x915 -> > ? #define ARC_REG_SLC_RGN_END 0x916 +> > #define ARC_REG_SLC_RGN_END 0x916 > > +#define ARC_REG_SLC_RGN_END1 0x917 -> > ?? -> > ? /* Bit val in SLC_CONTROL */ -> > ? #define SLC_CTRL_DIS 0x001 +> > +> > /* Bit val in SLC_CONTROL */ +> > #define SLC_CTRL_DIS 0x001 > > diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c > > index b7a1face1584..0b4e2650c5de 100644 > > --- a/arch/arc/mm/cache.c > > +++ b/arch/arc/mm/cache.c > > @@ -580,6 +580,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) -> > ?? static DEFINE_SPINLOCK(lock); -> > ?? unsigned long flags; -> > ?? unsigned int ctrl; +> > static DEFINE_SPINLOCK(lock); +> > unsigned long flags; +> > unsigned int ctrl; > > + phys_addr_t end; -> > ?? -> > ?? spin_lock_irqsave(&lock, flags); -> > ?? +> > +> > spin_lock_irqsave(&lock, flags); +> > > > @@ -609,8 +610,11 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) -> > ?? ?* END needs to be setup before START (latter triggers the operation) -> > ?? ?* END can't be same as START, so add (l2_line_sz - 1) to sz -> > ?? ?*/ +> > * END needs to be setup before START (latter triggers the operation) +> > * END can't be same as START, so add (l2_line_sz - 1) to sz +> > */ > > - write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1)); > > - write_aux_reg(ARC_REG_SLC_RGN_START, paddr); > > + end = paddr + sz + l2_line_sz - 1; @@ -67,12 +67,12 @@ Path: (null) CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.13.0-rc1-next-20170718-00001-g6f0be43cd25b-dirty #1 task: 9f02ba80 task.stack: 9f02c000 -[ECR???]: 0x00020000 => Illegal Insn -[EFA???]: 0x8020bba2 +[ECR ]: 0x00020000 => Illegal Insn +[EFA ]: 0x8020bba2 [BLINK ]: slc_op+0x1a/0xac -[ERET??]: slc_op+0x4a/0xac -[STAT32]: 0x00080802 :???K????? -BTA: 0x8020bb80??SP: 0x9f02dd88??FP: 0x00000000 +[ERET ]: slc_op+0x4a/0xac +[STAT32]: 0x00080802 : K +BTA: 0x8020bb80 SP: 0x9f02dd88 FP: 0x00000000 LPS: 0x80670da4 LPE: 0x80670db8 LPC: 0x00000000 r00: 0x00000031 r01: 0x00002000 r02: 0x9f38403f r03: 0x00000917 r04: 0x00000031 r05: 0x9f38a5c0 @@ -81,22 +81,22 @@ r09: 0x00000000 r10: 0x00000000 r11: 0x80808080 r12: 0x8020bb72 Stack Trace: -? slc_op+0x4a/0xac -? arc_dma_alloc+0x7c/0xd8 -? dma_pool_alloc+0x186/0x1d0 -? ehci_qh_alloc+0x34/0xd4 -? ehci_setup+0x15c/0x420 -? ehci_platform_reset+0x48/0x68 -? usb_add_hcd+0x186/0x624 -? ehci_platform_probe+0x210/0x514 -? platform_drv_probe+0x26/0x64 -? really_probe+0x284/0x348 -? __driver_attach+0xac/0xd4 -? bus_for_each_dev+0x38/0x70 -? bus_add_driver+0xc0/0x180 -? driver_register+0x50/0xec -? do_one_initcall+0x32/0x118 -? kernel_init_freeable+0x108/0x198 + slc_op+0x4a/0xac + arc_dma_alloc+0x7c/0xd8 + dma_pool_alloc+0x186/0x1d0 + ehci_qh_alloc+0x34/0xd4 + ehci_setup+0x15c/0x420 + ehci_platform_reset+0x48/0x68 + usb_add_hcd+0x186/0x624 + ehci_platform_probe+0x210/0x514 + platform_drv_probe+0x26/0x64 + really_probe+0x284/0x348 + __driver_attach+0xac/0xd4 + bus_for_each_dev+0x38/0x70 + bus_add_driver+0xc0/0x180 + driver_register+0x50/0xec + do_one_initcall+0x32/0x118 + kernel_init_freeable+0x108/0x198 ----------------------->8---------------------- So I'll respin this patch with conditional setup of those regs diff --git a/a/content_digest b/N1/content_digest index 724ed0c..3da291b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,14 +1,17 @@ "ref\020170801095847.6425-1-abrodkin@synopsys.com\0" "ref\02f6ba6bb-ae07-0ff9-c2ff-0f162eab2ef0@synopsys.com\0" - "From\0Alexey.Brodkin@synopsys.com (Alexey Brodkin)\0" - "Subject\0[PATCH] arc: arcv2: cache: Explicitly set MSB counterpart of region ops addresses\0" + "From\0Alexey Brodkin <Alexey.Brodkin@synopsys.com>\0" + "Subject\0Re: [PATCH] arc: arcv2: cache: Explicitly set MSB counterpart of region ops addresses\0" "Date\0Wed, 2 Aug 2017 08:03:57 +0000\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0Vineet Gupta <Vineet.Gupta1@synopsys.com>\0" + "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" + vladimir.kondratiev@intel.com <vladimir.kondratiev@intel.com> + " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" "\00:1\0" "b\0" "Hi Vineet,\n" "\n" - "On Wed, 2017-08-02@09:09 +0530, Vineet Gupta wrote:\n" + "On Wed, 2017-08-02 at 09:09 +0530, Vineet Gupta wrote:\n" "> On 08/01/2017 03:29 PM, Alexey Brodkin wrote:\n" "> > \n" "> > It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1\n" @@ -17,43 +20,43 @@ "> > for example on HSDK platform where PAE40 support exists in hardware\n" "> > we saw each and every SLC region op to take seconds (sic!).\n" "> > \n" - "> > Signed-off-by: Alexey Brodkin <abrodkin at synopsys.com>\n" - "> > Reported-by: Vladimir Kondratiev <vladimir.kondratiev at intel.com>\n" + "> > Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>\n" + "> > Reported-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>\n" "> > ---\n" - "> > ? arch/arc/include/asm/cache.h | 2 ++\n" - "> > ? arch/arc/mm/cache.c??????????| 8 ++++++--\n" - "> > ? 2 files changed, 8 insertions(+), 2 deletions(-)\n" + "> > \302\240 arch/arc/include/asm/cache.h | 2 ++\n" + "> > \302\240 arch/arc/mm/cache.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 8 ++++++--\n" + "> > \302\240 2 files changed, 8 insertions(+), 2 deletions(-)\n" "> > \n" "> > diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h\n" "> > index 35127ad95124..1f3c2f967471 100644\n" "> > --- a/arch/arc/include/asm/cache.h\n" "> > +++ b/arch/arc/include/asm/cache.h\n" "> > @@ -91,7 +91,9 @@ extern unsigned long perip_base, perip_end;\n" - "> > ? #define ARC_REG_SLC_FLUSH\t0x904\n" - "> > ? #define ARC_REG_SLC_INVALIDATE\t0x905\n" - "> > ? #define ARC_REG_SLC_RGN_START\t0x914\n" + "> > \302\240 #define ARC_REG_SLC_FLUSH\t0x904\n" + "> > \302\240 #define ARC_REG_SLC_INVALIDATE\t0x905\n" + "> > \302\240 #define ARC_REG_SLC_RGN_START\t0x914\n" "> > +#define ARC_REG_SLC_RGN_START1\t0x915\n" - "> > ? #define ARC_REG_SLC_RGN_END\t0x916\n" + "> > \302\240 #define ARC_REG_SLC_RGN_END\t0x916\n" "> > +#define ARC_REG_SLC_RGN_END1\t0x917\n" - "> > ??\n" - "> > ? /* Bit val in SLC_CONTROL */\n" - "> > ? #define SLC_CTRL_DIS\t\t0x001\n" + "> > \302\240\302\240\n" + "> > \302\240 /* Bit val in SLC_CONTROL */\n" + "> > \302\240 #define SLC_CTRL_DIS\t\t0x001\n" "> > diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c\n" "> > index b7a1face1584..0b4e2650c5de 100644\n" "> > --- a/arch/arc/mm/cache.c\n" "> > +++ b/arch/arc/mm/cache.c\n" "> > @@ -580,6 +580,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)\n" - "> > ??\tstatic DEFINE_SPINLOCK(lock);\n" - "> > ??\tunsigned long flags;\n" - "> > ??\tunsigned int ctrl;\n" + "> > \302\240\302\240\tstatic DEFINE_SPINLOCK(lock);\n" + "> > \302\240\302\240\tunsigned long flags;\n" + "> > \302\240\302\240\tunsigned int ctrl;\n" "> > +\tphys_addr_t end;\n" - "> > ??\n" - "> > ??\tspin_lock_irqsave(&lock, flags);\n" - "> > ??\n" + "> > \302\240\302\240\n" + "> > \302\240\302\240\tspin_lock_irqsave(&lock, flags);\n" + "> > \302\240\302\240\n" "> > @@ -609,8 +610,11 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)\n" - "> > ??\t?* END needs to be setup before START (latter triggers the operation)\n" - "> > ??\t?* END can't be same as START, so add (l2_line_sz - 1) to sz\n" - "> > ??\t?*/\n" + "> > \302\240\302\240\t\302\240* END needs to be setup before START (latter triggers the operation)\n" + "> > \302\240\302\240\t\302\240* END can't be same as START, so add (l2_line_sz - 1) to sz\n" + "> > \302\240\302\240\t\302\240*/\n" "> > -\twrite_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));\n" "> > -\twrite_aux_reg(ARC_REG_SLC_RGN_START, paddr);\n" "> > +\tend = paddr + sz + l2_line_sz - 1;\n" @@ -75,12 +78,12 @@ "CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.13.0-rc1-next-20170718-00001-g6f0be43cd25b-dirty #1\n" "task: 9f02ba80 task.stack: 9f02c000\n" "\n" - "[ECR???]: 0x00020000 => Illegal Insn\n" - "[EFA???]: 0x8020bba2\n" + "[ECR\302\240\302\240\302\240]: 0x00020000 => Illegal Insn\n" + "[EFA\302\240\302\240\302\240]: 0x8020bba2\n" "[BLINK ]: slc_op+0x1a/0xac\n" - "[ERET??]: slc_op+0x4a/0xac\n" - "[STAT32]: 0x00080802 :???K?????\n" - "BTA: 0x8020bb80??SP: 0x9f02dd88??FP: 0x00000000\n" + "[ERET\302\240\302\240]: slc_op+0x4a/0xac\n" + "[STAT32]: 0x00080802 :\302\240\302\240\302\240K\302\240\302\240\302\240\302\240\302\240\n" + "BTA: 0x8020bb80\302\240\302\240SP: 0x9f02dd88\302\240\302\240FP: 0x00000000\n" "LPS: 0x80670da4 LPE: 0x80670db8 LPC: 0x00000000\n" "r00: 0x00000031 r01: 0x00002000 r02: 0x9f38403f\n" "r03: 0x00000917 r04: 0x00000031 r05: 0x9f38a5c0\n" @@ -89,22 +92,22 @@ "r12: 0x8020bb72\n" "\n" "Stack Trace:\n" - "? slc_op+0x4a/0xac\n" - "? arc_dma_alloc+0x7c/0xd8\n" - "? dma_pool_alloc+0x186/0x1d0\n" - "? ehci_qh_alloc+0x34/0xd4\n" - "? ehci_setup+0x15c/0x420\n" - "? ehci_platform_reset+0x48/0x68\n" - "? usb_add_hcd+0x186/0x624\n" - "? ehci_platform_probe+0x210/0x514\n" - "? platform_drv_probe+0x26/0x64\n" - "? really_probe+0x284/0x348\n" - "? __driver_attach+0xac/0xd4\n" - "? bus_for_each_dev+0x38/0x70\n" - "? bus_add_driver+0xc0/0x180\n" - "? driver_register+0x50/0xec\n" - "? do_one_initcall+0x32/0x118\n" - "? kernel_init_freeable+0x108/0x198\n" + "\302\240 slc_op+0x4a/0xac\n" + "\302\240 arc_dma_alloc+0x7c/0xd8\n" + "\302\240 dma_pool_alloc+0x186/0x1d0\n" + "\302\240 ehci_qh_alloc+0x34/0xd4\n" + "\302\240 ehci_setup+0x15c/0x420\n" + "\302\240 ehci_platform_reset+0x48/0x68\n" + "\302\240 usb_add_hcd+0x186/0x624\n" + "\302\240 ehci_platform_probe+0x210/0x514\n" + "\302\240 platform_drv_probe+0x26/0x64\n" + "\302\240 really_probe+0x284/0x348\n" + "\302\240 __driver_attach+0xac/0xd4\n" + "\302\240 bus_for_each_dev+0x38/0x70\n" + "\302\240 bus_add_driver+0xc0/0x180\n" + "\302\240 driver_register+0x50/0xec\n" + "\302\240 do_one_initcall+0x32/0x118\n" + "\302\240 kernel_init_freeable+0x108/0x198\n" "----------------------->8----------------------\n" "\n" "So I'll respin this patch with conditional setup of those regs\n" @@ -112,4 +115,4 @@ "\n" -Alexey -3ee4c01ee789ae58e8cd196159f3bcc7000f188233dd895d45803b4cef4c2ea5 +70089b1037152163ce3efaabe784bf33258a13eaf8804ecb9603b2d1e007e661
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