From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Ong, Hean Loong" Subject: Re: [PATCHv5 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite Date: Fri, 11 Aug 2017 01:07:33 +0000 Message-ID: <1502413651.1967.1.camel@intel.com> References: <1501736496-4118-1-git-send-email-hean.loong.ong@intel.com> <1501736496-4118-2-git-send-email-hean.loong.ong@intel.com> <20170810165920.73zsy2cscblisubr@rob-hp-laptop> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170810165920.73zsy2cscblisubr@rob-hp-laptop> Content-Language: en-US Content-ID: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: "robh@kernel.org" Cc: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "dinguyen@kernel.org" , "laurent.pinchart@ideasonboard.com" , "Vetter, Daniel" , "Ong@rob-hp-laptop" List-Id: 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X19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3Rv cC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmkt ZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751602AbdHKBHo (ORCPT ); Thu, 10 Aug 2017 21:07:44 -0400 Received: from mga09.intel.com ([134.134.136.24]:35962 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750841AbdHKBHm (ORCPT ); Thu, 10 Aug 2017 21:07:42 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,355,1498546800"; d="scan'208";a="298808612" From: "Ong, Hean Loong" To: "robh@kernel.org" CC: "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , "dinguyen@kernel.org" , "Ong@rob-hp-laptop" , "Vetter, Daniel" , "laurent.pinchart@ideasonboard.com" , "devicetree@vger.kernel.org" Subject: Re: [PATCHv5 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite Thread-Topic: [PATCHv5 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite Thread-Index: AQHTDBWkq5b8PN8itUWo5Lwz3I0zhKJ9VbwAgACIZoA= Date: Fri, 11 Aug 2017 01:07:33 +0000 Message-ID: <1502413651.1967.1.camel@intel.com> References: <1501736496-4118-1-git-send-email-hean.loong.ong@intel.com> <1501736496-4118-2-git-send-email-hean.loong.ong@intel.com> <20170810165920.73zsy2cscblisubr@rob-hp-laptop> In-Reply-To: <20170810165920.73zsy2cscblisubr@rob-hp-laptop> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.226.242.95] Content-Type: text/plain; charset="utf-8" Content-ID: MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v7B17oXo028825 On Thu, 2017-08-10 at 11:59 -0500, Rob Herring wrote: > On Thu, Aug 03, 2017 at 01:01:34PM +0800, Hean Loong, Ong wrote: > > > > From: Ong Hean Loong > I take back my ack... > > Laurent's comments on v4 are not addressed. > Noted. > > > > Device tree binding for Intel FPGA Video and Image > > Processing Suite. The binding involved would be generated > > from the Altera (Intel) Qsys system. The bindings would > > set the max width, max height, buts per pixel and memory > > port width. The device tree binding only supports the Intel > > Arria10 devkit and its variants. Vendor name retained as > > altr. > > > > Signed-off-by: Ong, Hean Loong > > --- > >  .../devicetree/bindings/display/altr,vip-fb2.txt   | 39 > > ++++++++++++++++++++++ > >  1 file changed, 39 insertions(+) > >  create mode 100644 > > Documentation/devicetree/bindings/display/altr,vip-fb2.txt > > > > diff --git a/Documentation/devicetree/bindings/display/altr,vip- > > fb2.txt b/Documentation/devicetree/bindings/display/altr,vip- > > fb2.txt > > new file mode 100644 > > index 0000000..c4338d9 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt > > @@ -0,0 +1,39 @@ > > +Intel Video and Image Processing(VIP) Frame Buffer II bindings > > + > > +Supported hardware: Arria 10 and above with display port IP > > + > > +The hardware associated with this device tree is a SoC FPGA. Where > > there is an ARM controller > > +and a FPGA device. The ARM controller would host the Linux OS > > while the FPGA device runs on its > > +individual IP firmware. In the Intel VIP Frame Buffer II the ARM > > controller would be > > +driving data from the Linux OS to the FPGA device programmed with > > the Frame Buffer II IP > > +to render pixels to be streamed to the Display Port connector. > Still referring to Linux as both Laurent and I pointed out. > > Wrap your lines at <80 chars. This was fine before... > > > > > + > > +The Frame Buffer II device is a simple frame buffer device. The > > device contains the display > > +properties and the bridge or connector register. The output for > > this device currently > > +is a dedicated to a single Display Port. Currently the max > > resolution supported is 1280 x 720 at > > +60Hz. > > + > > +More information the FPGA video IP component can be acquired from > > +https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/li > > terature/ug/ug_vip.pdf > > + > > + > > +New bindings: > > +============= > > +Required properties: > > +---------------------------- > > +- compatible: "altr,vip-frame-buffer-2.0" > > +- reg: Physical base address and length of the framebuffer > > controller's > > +  registers. > > +- altr,max-width: The width of the framebuffer in pixels. > > +- altr,max-height: The height of the framebuffer in pixels. > > +- altr,mem-port-width = the bus width of the avalon master port on > > the frame reader > > + > > +Example: > > +---------------------------- > > +       dp_0_frame_buf: display-controller@100000280 { > > +                       compatible = "altr,vip-frame-buffer-2.0"; > > +                       reg = <0x00000001 0x00000280 0x00000040>; > > +                       altr,max-width = <1280>; > > +                       altr,max-height = <720>; > > +                       altr,mem-port-width = <128>; > > +       };