diff for duplicates of <1503490719.15555.1.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index 67aa9ba..039da70 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,15 +1,15 @@ -On Tue, 2017-08-22@13:45 -0700, Vineet Gupta wrote: +On Tue, 2017-08-22 at 13:45 -0700, Vineet Gupta wrote: > On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote: > > Add core pll node (core_clk) to manage cpu frequency. > > core_clk represents pll itself. > > input_clk represents clock signal source (basically xtal) which > > comes to pll input. > > -> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> > > --- -> > ? arch/arc/boot/dts/axc003.dtsi?????| 11 +++++++++-- -> > ? arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++-- -> > ? 2 files changed, 18 insertions(+), 4 deletions(-) +> >  arch/arc/boot/dts/axc003.dtsi     | 11 +++++++++-- +> >  arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++-- +> >  2 files changed, 18 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arc/boot/dts/axc003.dtsi > > b/arch/arc/boot/dts/axc003.dtsi @@ -17,54 +17,54 @@ On Tue, 2017-08-22@13:45 -0700, Vineet Gupta wrote: > > --- a/arch/arc/boot/dts/axc003.dtsi > > +++ b/arch/arc/boot/dts/axc003.dtsi > > @@ -24,10 +24,17 @@ -> > ?? -> > ?? ranges = <0x00000000 0x0 0xf0000000 0x10000000>; -> > ?? +> >   +> >   ranges = <0x00000000 0x0 0xf0000000 0x10000000>; +> >   > > - core_clk: core_clk { > > + input_clk: input-clk { -> > ?? #clock-cells = <0>; -> > ?? compatible = "fixed-clock"; +> >   #clock-cells = <0>; +> >   compatible = "fixed-clock"; > > - clock-frequency = <90000000>; > > + clock-frequency = <33333333>; > > + }; > > + -> > + core_clk: core-clk at 80 { +> > + core_clk: core-clk@80 { > > + compatible = "snps,axs10x-arc-pll-clock"; > > + reg = <0x80 0x10>, <0x100 0x10>; > > + #clock-cells = <0>; > > + clocks = <&input_clk>; -> > ?? }; -> > ?? -> > ?? core_intc: archs-intc at cpu { +> >   }; +> >   +> >   core_intc: archs-intc@cpu { > > diff --git a/arch/arc/boot/dts/axc003_idu.dtsi > > b/arch/arc/boot/dts/axc003_idu.dtsi > > index 4ebb2170..5b56bef 100644 > > --- a/arch/arc/boot/dts/axc003_idu.dtsi > > +++ b/arch/arc/boot/dts/axc003_idu.dtsi > > @@ -24,10 +24,17 @@ -> > ?? -> > ?? ranges = <0x00000000 0x0 0xf0000000 0x10000000>; -> > ?? +> >   +> >   ranges = <0x00000000 0x0 0xf0000000 0x10000000>; +> >   > > - core_clk: core_clk { > > + input_clk: input-clk { -> > ?? #clock-cells = <0>; -> > ?? compatible = "fixed-clock"; +> >   #clock-cells = <0>; +> >   compatible = "fixed-clock"; > > - clock-frequency = <100000000>; > > + clock-frequency = <33333333>; > > + }; > > + -> > + core_clk: core-clk at 80 { +> > + core_clk: core-clk@80 { > > + compatible = "snps,axs10x-arc-pll-clock"; > > + reg = <0x80 0x10>, <0x100 0x10>; > > + #clock-cells = <0>; > > + clocks = <&input_clk>; -> > ?? }; -> > ?? -> > ?? core_intc: archs-intc at cpu { +> >   }; +> >   +> >   core_intc: archs-intc@cpu { > > > Do we have a bisectability issue here - isn't system broken -> temporarily at 2/5 -? +> temporarily at 2/5 - > and only 3/5 makes it work again - if so we need to squash them > together ! @@ -86,18 +86,18 @@ cpu-freq = <100000000>; in arch/arc/boot/dts/axc003.dtsi So diff should be like --------------->8----------- -+???????cpus { -+???????????????#address-cells = <1>; -+???????????????#size-cells = <0>; ++       cpus { ++               #address-cells = <1>; ++               #size-cells = <0>; + -+???????????????cpu at 0 { -+???????????????????????device_type = "cpu"; -+???????????????????????compatible = "snps,archs38"; -+???????????????????????reg = <0>; -+???????????????????????cpu-freq = <90000000>; -+???????????????????????clocks = <&core_clk>; -+???????????????}; -+???????}; ++               cpu@0 { ++                       device_type = "cpu"; ++                       compatible = "snps,archs38"; ++                       reg = <0>; ++                       cpu-freq = <90000000>; ++                       clocks = <&core_clk>; ++               }; ++       }; + --------------->8----------- @@ -105,4 +105,4 @@ Should I send you v2 respin or you'll fix that up locally? > -Vineet -- -?Eugeniy Paltsev + Eugeniy PaltsevN‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·zøœzÚÞz)í…æèw*\x1fjg¬±¨\x1e¶‰šŽŠÝ¢j.ïÛ°\½½MŽúgjÌæa×\x02››–' ™©Þ¢¸\f¢·¦j:+v‰¨ŠwèjØm¶Ÿÿ¾\a«‘êçzZ+ƒùšŽŠÝ¢j"ú!¶i diff --git a/a/content_digest b/N1/content_digest index 03db0d9..a6058b1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,24 +1,31 @@ "ref\020170814161213.17522-1-Eugeniy.Paltsev@synopsys.com\0" "ref\020170814161213.17522-4-Eugeniy.Paltsev@synopsys.com\0" "ref\09624a76d-a31f-10fc-aec5-5ffa1d437c3d@synopsys.com\0" - "From\0Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev)\0" - "Subject\0[PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency\0" + "ref\09624a76d-a31f-10fc-aec5-5ffa1d437c3d-HKixBCOQz3hWk0Htik3J/w@public.gmane.org\0" + "From\0Eugeniy Paltsev <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>\0" + "Subject\0Re: [PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency\0" "Date\0Wed, 23 Aug 2017 12:18:40 +0000\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0Vineet Gupta <Vineet.Gupta1-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>" + " linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" + "Cc\0linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>" + mark.rutland-5wv7dgnIgG8@public.gmane.org <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Alexey Brodkin <Alexey.Brodkin-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>\0" "\00:1\0" "b\0" - "On Tue, 2017-08-22@13:45 -0700, Vineet Gupta wrote:\n" + "On Tue, 2017-08-22 at 13:45 -0700, Vineet Gupta wrote:\n" "> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:\n" "> > Add core pll node (core_clk) to manage cpu frequency.\n" "> > core_clk represents pll itself.\n" "> > input_clk represents clock signal source (basically xtal) which\n" "> > comes to pll input.\n" "> > \n" - "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" "> > ---\n" - "> > ? arch/arc/boot/dts/axc003.dtsi?????| 11 +++++++++--\n" - "> > ? arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++--\n" - "> > ? 2 files changed, 18 insertions(+), 4 deletions(-)\n" + "> > \303\202\302\240 arch/arc/boot/dts/axc003.dtsi\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240| 11 +++++++++--\n" + "> > \303\202\302\240 arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++--\n" + "> > \303\202\302\240 2 files changed, 18 insertions(+), 4 deletions(-)\n" "> > \n" "> > diff --git a/arch/arc/boot/dts/axc003.dtsi\n" "> > b/arch/arc/boot/dts/axc003.dtsi\n" @@ -26,54 +33,54 @@ "> > --- a/arch/arc/boot/dts/axc003.dtsi\n" "> > +++ b/arch/arc/boot/dts/axc003.dtsi\n" "> > @@ -24,10 +24,17 @@\n" - "> > ??\n" - "> > ??\t\tranges = <0x00000000 0x0 0xf0000000 0x10000000>;\n" - "> > ??\n" + "> > \303\202\302\240\303\202\302\240\n" + "> > \303\202\302\240\303\202\302\240\t\tranges = <0x00000000 0x0 0xf0000000 0x10000000>;\n" + "> > \303\202\302\240\303\202\302\240\n" "> > -\t\tcore_clk: core_clk {\n" "> > +\t\tinput_clk: input-clk {\n" - "> > ??\t\t\t#clock-cells = <0>;\n" - "> > ??\t\t\tcompatible = \"fixed-clock\";\n" + "> > \303\202\302\240\303\202\302\240\t\t\t#clock-cells = <0>;\n" + "> > \303\202\302\240\303\202\302\240\t\t\tcompatible = \"fixed-clock\";\n" "> > -\t\t\tclock-frequency = <90000000>;\n" "> > +\t\t\tclock-frequency = <33333333>;\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tcore_clk: core-clk at 80 {\n" + "> > +\t\tcore_clk: core-clk@80 {\n" "> > +\t\t\tcompatible = \"snps,axs10x-arc-pll-clock\";\n" "> > +\t\t\treg = <0x80 0x10>, <0x100 0x10>;\n" "> > +\t\t\t#clock-cells = <0>;\n" "> > +\t\t\tclocks = <&input_clk>;\n" - "> > ??\t\t};\n" - "> > ??\n" - "> > ??\t\tcore_intc: archs-intc at cpu {\n" + "> > \303\202\302\240\303\202\302\240\t\t};\n" + "> > \303\202\302\240\303\202\302\240\n" + "> > \303\202\302\240\303\202\302\240\t\tcore_intc: archs-intc@cpu {\n" "> > diff --git a/arch/arc/boot/dts/axc003_idu.dtsi\n" "> > b/arch/arc/boot/dts/axc003_idu.dtsi\n" "> > index 4ebb2170..5b56bef 100644\n" "> > --- a/arch/arc/boot/dts/axc003_idu.dtsi\n" "> > +++ b/arch/arc/boot/dts/axc003_idu.dtsi\n" "> > @@ -24,10 +24,17 @@\n" - "> > ??\n" - "> > ??\t\tranges = <0x00000000 0x0 0xf0000000 0x10000000>;\n" - "> > ??\n" + "> > \303\202\302\240\303\202\302\240\n" + "> > \303\202\302\240\303\202\302\240\t\tranges = <0x00000000 0x0 0xf0000000 0x10000000>;\n" + "> > \303\202\302\240\303\202\302\240\n" "> > -\t\tcore_clk: core_clk {\n" "> > +\t\tinput_clk: input-clk {\n" - "> > ??\t\t\t#clock-cells = <0>;\n" - "> > ??\t\t\tcompatible = \"fixed-clock\";\n" + "> > \303\202\302\240\303\202\302\240\t\t\t#clock-cells = <0>;\n" + "> > \303\202\302\240\303\202\302\240\t\t\tcompatible = \"fixed-clock\";\n" "> > -\t\t\tclock-frequency = <100000000>;\n" "> > +\t\t\tclock-frequency = <33333333>;\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tcore_clk: core-clk at 80 {\n" + "> > +\t\tcore_clk: core-clk@80 {\n" "> > +\t\t\tcompatible = \"snps,axs10x-arc-pll-clock\";\n" "> > +\t\t\treg = <0x80 0x10>, <0x100 0x10>;\n" "> > +\t\t\t#clock-cells = <0>;\n" "> > +\t\t\tclocks = <&input_clk>;\n" - "> > ??\t\t};\n" - "> > ??\n" - "> > ??\t\tcore_intc: archs-intc at cpu {\n" + "> > \303\202\302\240\303\202\302\240\t\t};\n" + "> > \303\202\302\240\303\202\302\240\n" + "> > \303\202\302\240\303\202\302\240\t\tcore_intc: archs-intc@cpu {\n" "> \n" "> \n" "> Do we have a bisectability issue here - isn't system broken\n" - "> temporarily at 2/5 -?\n" + "> temporarily at 2/5 -\303\202\302\240\n" "> and only 3/5 makes it work again - if so we need to squash them\n" "> together !\n" "\n" @@ -95,18 +102,18 @@ "in arch/arc/boot/dts/axc003.dtsi\n" "So diff should be like\n" "--------------->8-----------\n" - "+???????cpus {\n" - "+???????????????#address-cells = <1>;\n" - "+???????????????#size-cells = <0>;\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240cpus {\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240#address-cells = <1>;\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240#size-cells = <0>;\n" "+\n" - "+???????????????cpu at 0 {\n" - "+???????????????????????device_type = \"cpu\";\n" - "+???????????????????????compatible = \"snps,archs38\";\n" - "+???????????????????????reg = <0>;\n" - "+???????????????????????cpu-freq = <90000000>;\n" - "+???????????????????????clocks = <&core_clk>;\n" - "+???????????????};\n" - "+???????};\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240cpu@0 {\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240device_type = \"cpu\";\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240compatible = \"snps,archs38\";\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240reg = <0>;\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240cpu-freq = <90000000>;\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240clocks = <&core_clk>;\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240};\n" + "+\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240\303\202\302\240};\n" "+\n" "--------------->8-----------\n" "\n" @@ -114,6 +121,6 @@ " \n" "> -Vineet\n" "-- \n" - ?Eugeniy Paltsev + "\303\202\302\240Eugeniy PaltsevN\302\213\302\247\302\262\303\246\303\254r\302\270\302\233y\303\272\303\250\302\232\303\230b\302\262X\302\254\302\266\303\207\302\247v\303\230^\302\226)\303\236\302\272{.n\303\207+\302\211\302\267\302\235z\303\270\302\234z\303\232\303\236z)\303\255\302\205\303\246\303\250w*\037jg\302\254\302\261\302\250\036\302\266\302\211\302\232\302\216\302\212\303\235\302\242j.\303\257\303\233\302\260\\\302\275\302\275M\302\216\303\272gj\303\214\303\246a\303\227\002\302\233\302\233\302\226' \302\231\302\251\303\236\302\242\302\270\f\302\242\302\267\302\246j:+v\302\211\302\250\302\212w\303\250j\303\230m\302\266\302\237\303\277\302\276\a\302\253\302\221\303\252\303\247zZ+\302\203\303\271\302\232\302\216\302\212\303\235\302\242j\"\302\235\303\272!\302\266i" -ce751b47d9610bdf76aaa3ceac05119cf04be27d5ee084fe1761ea757b45d124 +a178b1728d33caac2151d2b13dd5cb45b812a36da620ff82d47d2f17ed7df85e
diff --git a/a/1.txt b/N2/1.txt index 67aa9ba..87c9b9b 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,15 +1,15 @@ -On Tue, 2017-08-22@13:45 -0700, Vineet Gupta wrote: +On Tue, 2017-08-22 at 13:45 -0700, Vineet Gupta wrote: > On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote: > > Add core pll node (core_clk) to manage cpu frequency. > > core_clk represents pll itself. > > input_clk represents clock signal source (basically xtal) which > > comes to pll input. > > -> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> > > --- -> > ? arch/arc/boot/dts/axc003.dtsi?????| 11 +++++++++-- -> > ? arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++-- -> > ? 2 files changed, 18 insertions(+), 4 deletions(-) +> > arch/arc/boot/dts/axc003.dtsi | 11 +++++++++-- +> > arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++-- +> > 2 files changed, 18 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arc/boot/dts/axc003.dtsi > > b/arch/arc/boot/dts/axc003.dtsi @@ -17,54 +17,54 @@ On Tue, 2017-08-22@13:45 -0700, Vineet Gupta wrote: > > --- a/arch/arc/boot/dts/axc003.dtsi > > +++ b/arch/arc/boot/dts/axc003.dtsi > > @@ -24,10 +24,17 @@ -> > ?? -> > ?? ranges = <0x00000000 0x0 0xf0000000 0x10000000>; -> > ?? +> > +> > ranges = <0x00000000 0x0 0xf0000000 0x10000000>; +> > > > - core_clk: core_clk { > > + input_clk: input-clk { -> > ?? #clock-cells = <0>; -> > ?? compatible = "fixed-clock"; +> > #clock-cells = <0>; +> > compatible = "fixed-clock"; > > - clock-frequency = <90000000>; > > + clock-frequency = <33333333>; > > + }; > > + -> > + core_clk: core-clk at 80 { +> > + core_clk: core-clk@80 { > > + compatible = "snps,axs10x-arc-pll-clock"; > > + reg = <0x80 0x10>, <0x100 0x10>; > > + #clock-cells = <0>; > > + clocks = <&input_clk>; -> > ?? }; -> > ?? -> > ?? core_intc: archs-intc at cpu { +> > }; +> > +> > core_intc: archs-intc@cpu { > > diff --git a/arch/arc/boot/dts/axc003_idu.dtsi > > b/arch/arc/boot/dts/axc003_idu.dtsi > > index 4ebb2170..5b56bef 100644 > > --- a/arch/arc/boot/dts/axc003_idu.dtsi > > +++ b/arch/arc/boot/dts/axc003_idu.dtsi > > @@ -24,10 +24,17 @@ -> > ?? -> > ?? ranges = <0x00000000 0x0 0xf0000000 0x10000000>; -> > ?? +> > +> > ranges = <0x00000000 0x0 0xf0000000 0x10000000>; +> > > > - core_clk: core_clk { > > + input_clk: input-clk { -> > ?? #clock-cells = <0>; -> > ?? compatible = "fixed-clock"; +> > #clock-cells = <0>; +> > compatible = "fixed-clock"; > > - clock-frequency = <100000000>; > > + clock-frequency = <33333333>; > > + }; > > + -> > + core_clk: core-clk at 80 { +> > + core_clk: core-clk@80 { > > + compatible = "snps,axs10x-arc-pll-clock"; > > + reg = <0x80 0x10>, <0x100 0x10>; > > + #clock-cells = <0>; > > + clocks = <&input_clk>; -> > ?? }; -> > ?? -> > ?? core_intc: archs-intc at cpu { +> > }; +> > +> > core_intc: archs-intc@cpu { > > > Do we have a bisectability issue here - isn't system broken -> temporarily at 2/5 -? +> temporarily at 2/5 - > and only 3/5 makes it work again - if so we need to squash them > together ! @@ -86,18 +86,18 @@ cpu-freq = <100000000>; in arch/arc/boot/dts/axc003.dtsi So diff should be like --------------->8----------- -+???????cpus { -+???????????????#address-cells = <1>; -+???????????????#size-cells = <0>; ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; + -+???????????????cpu at 0 { -+???????????????????????device_type = "cpu"; -+???????????????????????compatible = "snps,archs38"; -+???????????????????????reg = <0>; -+???????????????????????cpu-freq = <90000000>; -+???????????????????????clocks = <&core_clk>; -+???????????????}; -+???????}; ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "snps,archs38"; ++ reg = <0>; ++ cpu-freq = <90000000>; ++ clocks = <&core_clk>; ++ }; ++ }; + --------------->8----------- @@ -105,4 +105,4 @@ Should I send you v2 respin or you'll fix that up locally? > -Vineet -- -?Eugeniy Paltsev + Eugeniy Paltsev diff --git a/a/content_digest b/N2/content_digest index 03db0d9..a2adeb5 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,24 +1,30 @@ "ref\020170814161213.17522-1-Eugeniy.Paltsev@synopsys.com\0" "ref\020170814161213.17522-4-Eugeniy.Paltsev@synopsys.com\0" "ref\09624a76d-a31f-10fc-aec5-5ffa1d437c3d@synopsys.com\0" - "From\0Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev)\0" - "Subject\0[PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency\0" + "From\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\0" + "Subject\0Re: [PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency\0" "Date\0Wed, 23 Aug 2017 12:18:40 +0000\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0Vineet Gupta <Vineet.Gupta1@synopsys.com>" + " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" + "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" + mark.rutland@arm.com <mark.rutland@arm.com> + Alexey Brodkin <Alexey.Brodkin@synopsys.com> + robh+dt@kernel.org <robh+dt@kernel.org> + " devicetree@vger.kernel.org <devicetree@vger.kernel.org>\0" "\00:1\0" "b\0" - "On Tue, 2017-08-22@13:45 -0700, Vineet Gupta wrote:\n" + "On Tue, 2017-08-22 at 13:45 -0700, Vineet Gupta wrote:\n" "> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:\n" "> > Add core pll node (core_clk) to manage cpu frequency.\n" "> > core_clk represents pll itself.\n" "> > input_clk represents clock signal source (basically xtal) which\n" "> > comes to pll input.\n" "> > \n" - "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" "> > ---\n" - "> > ? arch/arc/boot/dts/axc003.dtsi?????| 11 +++++++++--\n" - "> > ? arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++--\n" - "> > ? 2 files changed, 18 insertions(+), 4 deletions(-)\n" + "> > \302\240 arch/arc/boot/dts/axc003.dtsi\302\240\302\240\302\240\302\240\302\240| 11 +++++++++--\n" + "> > \302\240 arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++--\n" + "> > \302\240 2 files changed, 18 insertions(+), 4 deletions(-)\n" "> > \n" "> > diff --git a/arch/arc/boot/dts/axc003.dtsi\n" "> > b/arch/arc/boot/dts/axc003.dtsi\n" @@ -26,54 +32,54 @@ "> > --- a/arch/arc/boot/dts/axc003.dtsi\n" "> > +++ b/arch/arc/boot/dts/axc003.dtsi\n" "> > @@ -24,10 +24,17 @@\n" - "> > ??\n" - "> > ??\t\tranges = <0x00000000 0x0 0xf0000000 0x10000000>;\n" - "> > ??\n" + "> > \302\240\302\240\n" + "> > \302\240\302\240\t\tranges = <0x00000000 0x0 0xf0000000 0x10000000>;\n" + "> > \302\240\302\240\n" "> > -\t\tcore_clk: core_clk {\n" "> > +\t\tinput_clk: input-clk {\n" - "> > ??\t\t\t#clock-cells = <0>;\n" - "> > ??\t\t\tcompatible = \"fixed-clock\";\n" + "> > \302\240\302\240\t\t\t#clock-cells = <0>;\n" + "> > \302\240\302\240\t\t\tcompatible = \"fixed-clock\";\n" "> > -\t\t\tclock-frequency = <90000000>;\n" "> > +\t\t\tclock-frequency = <33333333>;\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tcore_clk: core-clk at 80 {\n" + "> > +\t\tcore_clk: core-clk@80 {\n" "> > +\t\t\tcompatible = \"snps,axs10x-arc-pll-clock\";\n" "> > +\t\t\treg = <0x80 0x10>, <0x100 0x10>;\n" "> > +\t\t\t#clock-cells = <0>;\n" "> > +\t\t\tclocks = <&input_clk>;\n" - "> > ??\t\t};\n" - "> > ??\n" - "> > ??\t\tcore_intc: archs-intc at cpu {\n" + "> > \302\240\302\240\t\t};\n" + "> > \302\240\302\240\n" + "> > \302\240\302\240\t\tcore_intc: archs-intc@cpu {\n" "> > diff --git a/arch/arc/boot/dts/axc003_idu.dtsi\n" "> > b/arch/arc/boot/dts/axc003_idu.dtsi\n" "> > index 4ebb2170..5b56bef 100644\n" "> > --- a/arch/arc/boot/dts/axc003_idu.dtsi\n" "> > +++ b/arch/arc/boot/dts/axc003_idu.dtsi\n" "> > @@ -24,10 +24,17 @@\n" - "> > ??\n" - "> > ??\t\tranges = <0x00000000 0x0 0xf0000000 0x10000000>;\n" - "> > ??\n" + "> > \302\240\302\240\n" + "> > \302\240\302\240\t\tranges = <0x00000000 0x0 0xf0000000 0x10000000>;\n" + "> > \302\240\302\240\n" "> > -\t\tcore_clk: core_clk {\n" "> > +\t\tinput_clk: input-clk {\n" - "> > ??\t\t\t#clock-cells = <0>;\n" - "> > ??\t\t\tcompatible = \"fixed-clock\";\n" + "> > \302\240\302\240\t\t\t#clock-cells = <0>;\n" + "> > \302\240\302\240\t\t\tcompatible = \"fixed-clock\";\n" "> > -\t\t\tclock-frequency = <100000000>;\n" "> > +\t\t\tclock-frequency = <33333333>;\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tcore_clk: core-clk at 80 {\n" + "> > +\t\tcore_clk: core-clk@80 {\n" "> > +\t\t\tcompatible = \"snps,axs10x-arc-pll-clock\";\n" "> > +\t\t\treg = <0x80 0x10>, <0x100 0x10>;\n" "> > +\t\t\t#clock-cells = <0>;\n" "> > +\t\t\tclocks = <&input_clk>;\n" - "> > ??\t\t};\n" - "> > ??\n" - "> > ??\t\tcore_intc: archs-intc at cpu {\n" + "> > \302\240\302\240\t\t};\n" + "> > \302\240\302\240\n" + "> > \302\240\302\240\t\tcore_intc: archs-intc@cpu {\n" "> \n" "> \n" "> Do we have a bisectability issue here - isn't system broken\n" - "> temporarily at 2/5 -?\n" + "> temporarily at 2/5 -\302\240\n" "> and only 3/5 makes it work again - if so we need to squash them\n" "> together !\n" "\n" @@ -95,18 +101,18 @@ "in arch/arc/boot/dts/axc003.dtsi\n" "So diff should be like\n" "--------------->8-----------\n" - "+???????cpus {\n" - "+???????????????#address-cells = <1>;\n" - "+???????????????#size-cells = <0>;\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240cpus {\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240#address-cells = <1>;\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240#size-cells = <0>;\n" "+\n" - "+???????????????cpu at 0 {\n" - "+???????????????????????device_type = \"cpu\";\n" - "+???????????????????????compatible = \"snps,archs38\";\n" - "+???????????????????????reg = <0>;\n" - "+???????????????????????cpu-freq = <90000000>;\n" - "+???????????????????????clocks = <&core_clk>;\n" - "+???????????????};\n" - "+???????};\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240cpu@0 {\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240device_type = \"cpu\";\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240compatible = \"snps,archs38\";\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240reg = <0>;\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240cpu-freq = <90000000>;\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clocks = <&core_clk>;\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240};\n" + "+\302\240\302\240\302\240\302\240\302\240\302\240\302\240};\n" "+\n" "--------------->8-----------\n" "\n" @@ -114,6 +120,6 @@ " \n" "> -Vineet\n" "-- \n" - ?Eugeniy Paltsev + "\302\240Eugeniy Paltsev" -ce751b47d9610bdf76aaa3ceac05119cf04be27d5ee084fe1761ea757b45d124 +7918a5ccf494d15391d3ccb9242d363a0808b83ee51e8ad7becc1d47f47cb31c
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