Re: [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
Date: Wed, 30 Aug 2017 14:13:29 +0300	[thread overview]
Message-ID: <1504091609.8378.7.camel@linux.intel.com> (raw)
In-Reply-To: <20170829230907.21363-1-rodrigo.vivi@intel.com>

On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> Driver’s CPU access to GTT is via the GTTMMADR BAR.
> 
> The current HW implementation of that BAR is to only
> support <= DW (and maybe QW) writes—not 16/32/64B writes
> that could occur with WC and/or SSE/AVX moves.
> 
> GTTMMADR must be marked uncacheable (UC).
> Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry).
> 
> v2: Get clarification on the reasons and spec is getting
>     updated to reflect it now.
> 
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Suggested-by: Ben Widawsky <benjamin.widawsky@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Rodrigo, can you double-check how this interacts with the patch from
Zhi that adds the WB flag to PPAT_CACHE_INDEX on CNL.

If that doesn't help with the problem, this is;

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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