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From: Michael Neuling <mikey@neuling.org>
To: Paul Mackerras <paulus@ozlabs.org>, linuxppc-dev@ozlabs.org
Subject: Re: [PATCH v3 00/17] powerpc: Do alignment fixups using analyse_instr etc.
Date: Thu, 31 Aug 2017 10:49:58 +1000	[thread overview]
Message-ID: <1504140598.4670.32.camel@neuling.org> (raw)
In-Reply-To: <1504066360-30128-1-git-send-email-paulus@ozlabs.org>

Tested-by: Michael Neuling <mikey@neuling.org>

FWIW I've written a test case for alignment faults (which I'll convert to a
selftest and upstream). It tests all load stores supported by POWER9 (resul=
ts
below).

VSX: 2.06B
	Doing lxvd2x:	PASSED
	Doing lxvw4x:	PASSED
	Doing lxsdx:	PASSED
	Doing lxvdsx:	PASSED
	Doing stxvd2x:	PASSED
	Doing stxvw4x:	PASSED
	Doing stxsdx:	PASSED
VSX: 2.07B
	Doing lxsspx:	PASSED
	Doing lxsiwax:	PASSED
	Doing lxsiwzx:	PASSED
	Doing stxsspx:	PASSED
	Doing stxsiwx:	PASSED
VSX: 3.00B
	Doing lxsd:	PASSED
	Doing lxsibzx:	PASSED
	Doing lxsihzx:	PASSED
	Doing lxssp:	PASSED
	Doing lxv:	PASSED
	Doing lxvb16x:	PASSED
	Doing lxvh8x:	PASSED
	Doing lxvx:	PASSED
	Doing lxvwsx:	PASSED
	Doing lxvl:	PASSED
	Doing lxvll:	PASSED
	Doing stxsd:	PASSED
	Doing stxsibx:	PASSED
	Doing stxsihx:	PASSED
	Doing stxssp:	PASSED
	Doing stxv:	PASSED
	Doing stxvb16x:	PASSED
	Doing stxvh8x:	PASSED
	Doing stxvx:	PASSED
	Doing stxvl:	PASSED
	Doing stxvll:	PASSED
Integer
	Doing lbz:	PASSED
	Doing lbzu:	PASSED
	Doing lbzx:	PASSED
	Doing lbzux:	PASSED
	Doing lhz:	PASSED
	Doing lhzu:	PASSED
	Doing lhzx:	PASSED
	Doing lhzux:	PASSED
	Doing lha:	PASSED
	Doing lhau:	PASSED
	Doing lhax:	PASSED
	Doing lhaux:	PASSED
	Doing lhbrx:	PASSED
	Doing lwz:	PASSED
	Doing lwzu:	PASSED
	Doing lwzx:	PASSED
	Doing lwzux:	PASSED
	Doing lwa:	PASSED
	Doing lwax:	PASSED
	Doing lwaux:	PASSED
	Doing lwbrx:	PASSED
	Doing ld:	PASSED
	Doing ldu:	PASSED
	Doing ldx:	PASSED
	Doing ldux:	PASSED
	Doing ldbrx:	PASSED
	Doing lmw:	PASSED
	Doing stb:	PASSED
	Doing stbx:	PASSED
	Doing stbu:	PASSED
	Doing stbux:	PASSED
	Doing sth:	PASSED
	Doing sthx:	PASSED
	Doing sthu:	PASSED
	Doing sthux:	PASSED
	Doing sthbrx:	PASSED
	Doing stw:	PASSED
	Doing stwx:	PASSED
	Doing stwu:	PASSED
	Doing stwux:	PASSED
	Doing stwbrx:	PASSED
	Doing std:	PASSED
	Doing stdx:	PASSED
	Doing stdu:	PASSED
	Doing stdux:	PASSED
	Doing stdbrx:	PASSED
	Doing stmw:	PASSED
VMX
	Doing stvx:	PASSED
	Doing stvebx:	PASSED
	Doing stvehx:	PASSED
	Doing stvewx:	PASSED
	Doing stvxl:	PASSED
Floating point
	Doing lfd:	PASSED
	Doing lfdx:	PASSED
	Doing lfdp:	PASSED
	Doing lfdpx:	PASSED
	Doing lfdu:	PASSED
	Doing lfdux:	PASSED
	Doing lfs:	PASSED
	Doing lfsx:	PASSED
	Doing lfsu:	PASSED
	Doing lfsux:	PASSED
	Doing lfiwzx:	PASSED
	Doing lfiwax:	PASSED
	Doing stfd:	PASSED
	Doing stfdx:	PASSED
	Doing stfdp:	PASSED
	Doing stfdpx:	PASSED
	Doing stfdu:	PASSED
	Doing stfdux:	PASSED
	Doing stfs:	PASSED
	Doing stfsx:	PASSED
	Doing stfsu:	PASSED
	Doing stfsux:	PASSED
	Doing stfiwx:	PASSED


On Wed, 2017-08-30 at 14:12 +1000, Paul Mackerras wrote:
> This series extends the instruction emulation infrastructure in
> arch/powerpc/lib/sstep.c and uses it for emulating instructions when
> we get an alignment interrupt.=C2=A0=C2=A0The advantage of this is that w=
e only
> have to add the new POWER9 instructions in one place, and it fixes
> several bugs in alignment interrupt handling that have been identified
> recently.
>=20
> With this, analyse_instr() and emulate_step() handle almost all load
> and store instructions in Power ISA v3.00 -- all except the atomic
> memory operations (lwat, stwat, etc.).=C2=A0=C2=A0We now always use the l=
argest
> possible aligned memory accesses (up to 8 bytes) to emulate unaligned
> accesses.=C2=A0=C2=A0If we get a fault, the faulting address is accuratel=
y
> recorded in regs->dar.=C2=A0=C2=A0We also can now access FP/VMX/VSX regis=
ters
> directly if they are live, without having to spill them all to the
> thread_struct and the reload them all later.=C2=A0=C2=A0There are also va=
rious
> other fixes in the series.
>=20
> This version is based on the current powerpc next branch.
>=20
> Paul.
>=20
> =C2=A0arch/powerpc/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=
=A0=C2=A0=C2=A04 -
> =C2=A0arch/powerpc/include/asm/ppc-opcode.h |=C2=A0=C2=A0=C2=A010 +-
> =C2=A0arch/powerpc/include/asm/sstep.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0|=C2=A0=C2=A0=C2=A090 +-
> =C2=A0arch/powerpc/kernel/align.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A0774 +-----------
> =C2=A0arch/powerpc/lib/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A0=C2=A0=C2=A03 +-
> =C2=A0arch/powerpc/lib/ldstfp.S=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A0307 ++---
> =C2=A0arch/powerpc/lib/quad.S=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A0=C2=A062 +
> =C2=A0arch/powerpc/lib/sstep.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0| 2139 +++++++++++++++++++++++---=
------
> -
> =C2=A08 files changed, 1802 insertions(+), 1587 deletions(-)
>=20

  parent reply	other threads:[~2017-08-31  0:49 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-30  4:12 [PATCH v3 00/17] powerpc: Do alignment fixups using analyse_instr etc Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 01/17] powerpc: Correct instruction code for xxlor instruction Paul Mackerras
2017-09-01 13:29   ` [v3, " Michael Ellerman
2017-08-30  4:12 ` [PATCH v3 02/17] powerpc: Change analyse_instr so it doesn't modify *regs Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 03/17] powerpc: Don't check MSR FP/VMX/VSX enable bits in analyse_instr() Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 04/17] powerpc: Handle most loads and stores in instruction emulation code Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 05/17] powerpc/64: Fix update forms of loads and stores to write 64-bit EA Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 06/17] powerpc: Fix emulation of the isel instruction Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 07/17] powerpc: Don't update CR0 in emulation of popcnt, prty, bpermd instructions Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 08/17] powerpc: Add emulation for the addpcis instruction Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 09/17] powerpc: Make load/store emulation use larger memory accesses Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 10/17] powerpc: Emulate FP/vector/VSX loads/stores correctly when regs not live Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 11/17] powerpc: Emulate vector element load/store instructions Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 12/17] powerpc: Emulate load/store floating double pair instructions Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 13/17] powerpc: Emulate the dcbz instruction Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 14/17] powerpc: Set regs->dar if memory access fails in emulate_step() Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 15/17] powerpc: Handle opposite-endian processes in emulation code Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 16/17] powerpc: Separate out load/store emulation into its own function Paul Mackerras
2017-08-30  4:12 ` [PATCH v3 17/17] powerpc: Use instruction emulation infrastructure to handle alignment faults Paul Mackerras
2017-08-30  6:34 ` [PATCH v3 18/17] powerpc: Emulate load/store floating point as integer word instructions Paul Mackerras
2017-08-31  0:49 ` Michael Neuling [this message]
2017-08-31  0:54   ` [PATCH v3 00/17] powerpc: Do alignment fixups using analyse_instr etc Michael Neuling
2017-08-31 23:51 ` [PATCH 19/17] powerpc: Wrap register number correctly for string load/store instructions Paul Mackerras

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