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From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
To: Lionel Landwerlin <lionel.g.landwerlin@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [RFC PATCH 4/4] drm/i915: Expose RPCS (SSEU) configuration to userspace
Date: Mon, 04 Sep 2017 09:49:07 +0300	[thread overview]
Message-ID: <1504507747.4737.2.camel@linux.intel.com> (raw)
In-Reply-To: <20170901171230.28677-5-lionel.g.landwerlin@intel.com>

On Fri, 2017-09-01 at 18:12 +0100, Lionel Landwerlin wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
> 
> We want to allow userspace to reconfigure the subslice configuration for
> its own use case. To do so, we expose a context parameter to allow
> adjustment of the RPCS register stored within the context image (and
> currently not accessible via LRI). If the context is adjusted before
> first use, the adjustment is for "free"; otherwise if the context is
> active we flush the context off the GPU (stalling all users) and forcing
> the GPU to save the context to memory where we can modify it and so
> ensure that the register is reloaded on next execution.
> 
> The overhead of managing additional EU subslices can be significant,
> especially in multi-context workloads. Non-GPGPU contexts should
> preferably disable the subslices it is not using, and others should
> fine-tune the number to match their workload.
> 
> We expose complete control over the RPCS register, allowing
> configuration of slice/subslice, via masks packed into a u64 for
> simplicity. For example,
> 
> 	struct drm_i915_gem_context_param arg;
> 
> 	memset(&arg, 0, sizeof(arg));
> 	arg.ctx_id = ctx;
> 	arg.param = I915_CONTEXT_PARAM_SSEU;
> 	if (drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg) == 0) {
> 		union drm_i915_gem_context_param_sseu *sseu = &arg.value;
> 
> 		sseu->packed.subslice_mask = 0;
> 
> 		drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg);
> 	}
> 
> could be used to disable all subslices where supported.
> 
> v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
> CC: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> CC: Zhipeng Gong <zhipeng.gong@intel.com>
> CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Please do link to the userspace patches, will be easier to track them
that way.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2017-09-04  6:49 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-01 17:12 [RFC PATCH 0/4] drm/i915: enable userspace to program slice/subslice programming Lionel Landwerlin
2017-09-01 17:12 ` [RFC PATCH 1/4] drm/i915: Record both min/max eu_per_subslice in sseu_dev_info Lionel Landwerlin
2017-09-01 17:12 ` [RFC PATCH 2/4] drm/i915: Program RPCS for Broadwell Lionel Landwerlin
2017-09-01 17:12 ` [RFC PATCH 3/4] drm/i915: Record the sseu configuration per-context & engine Lionel Landwerlin
2017-09-01 17:12 ` [RFC PATCH 4/4] drm/i915: Expose RPCS (SSEU) configuration to userspace Lionel Landwerlin
2017-09-01 18:58   ` Chris Wilson
2017-09-21 17:16     ` Lionel Landwerlin
2017-09-04  6:49   ` Joonas Lahtinen [this message]
2017-09-01 17:44 ` ✓ Fi.CI.BAT: success for drm/i915: enable userspace to program slice/subslice programming Patchwork
2017-09-01 22:21 ` ✗ Fi.CI.IGT: failure " Patchwork

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