diff for duplicates of <1505315684.30546.32.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index e875d7e..a712229 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,4 +1,4 @@ -On Tue, 2017-09-12@11:38 -0700, Vineet Gupta wrote: +On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote: > On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote: > > DW sdio controller has external ciu clock divider controlled > > via register in SDIO IP. It divides sdio_ref_clk @@ -10,13 +10,13 @@ On Tue, 2017-09-12@11:38 -0700, Vineet Gupta wrote: > Is this a preventive fix or there are known issues with what we have today. Yes, it's kinda a preventive fix. -We check axs10x?ciu frequency when we found what hsdk?ciu frequency was wrong +We check axs10x ciu frequency when we found what hsdk ciu frequency was wrong and found that it is wring too. -I tried to run SD stress test with wrong ciu?frequency (50000000 Hz) and it passed +I tried to run SD stress test with wrong ciu frequency (50000000 Hz) and it passed successfully, but we must take into account the fact that it depends on SD -card itself. For example: this SD card mostly works fine on HSDK with ciu? -frequency 8x times?higher than expected! +card itself. For example: this SD card mostly works fine on HSDK with ciu +frequency 8x times higher than expected! Alexey says that he faced with unstable SD card work on axs103 earlier but he didn't save any artifacts about it. @@ -25,32 +25,32 @@ he didn't save any artifacts about it. No. > > -> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> > > --- -> > ? arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++- -> > ? 1 file changed, 8 insertions(+), 1 deletion(-) +> > arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++- +> > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi > > index 0ff7e07..7bdf581 100644 > > --- a/arch/arc/boot/dts/axs10x_mb.dtsi > > +++ b/arch/arc/boot/dts/axs10x_mb.dtsi > > @@ -44,7 +44,14 @@ -> > ?? -> > ?? mmcclk: mmcclk { -> > ?? compatible = "fixed-clock"; +> > +> > mmcclk: mmcclk { +> > compatible = "fixed-clock"; > > - clock-frequency = <50000000>; > > + /* -> > + ?* DW sdio controller has external ciu clock divider -> > + ?* controlled via register in SDIO IP. It divides -> > + ?* sdio_ref_clk (which comes from CGU) by 16 for -> > + ?* default. So default mmcclk clock (which comes -> > + ?* to sdk_in) is 25000000 Hz. -> > + ?*/ +> > + * DW sdio controller has external ciu clock divider +> > + * controlled via register in SDIO IP. It divides +> > + * sdio_ref_clk (which comes from CGU) by 16 for +> > + * default. So default mmcclk clock (which comes +> > + * to sdk_in) is 25000000 Hz. +> > + */ > > + clock-frequency = <25000000>; -> > ?? #clock-cells = <0>; -> > ?? }; -> > ?? +> > #clock-cells = <0>; +> > }; +> > > > -- -?Eugeniy Paltsev + Eugeniy Paltsev diff --git a/a/content_digest b/N1/content_digest index 0a6b57a..74df7dc 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,12 +1,17 @@ "ref\020170912182045.20941-1-Eugeniy.Paltsev@synopsys.com\0" "ref\04df1bb54-5fa1-5089-7d96-799ccfc78fce@synopsys.com\0" - "From\0Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev)\0" - "Subject\0[PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency\0" + "From\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\0" + "Subject\0Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency\0" "Date\0Wed, 13 Sep 2017 15:14:45 +0000\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0Vineet Gupta <Vineet.Gupta1@synopsys.com>" + " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" + "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" + Alexey Brodkin <Alexey.Brodkin@synopsys.com> + robh+dt@kernel.org <robh+dt@kernel.org> + " devicetree@vger.kernel.org <devicetree@vger.kernel.org>\0" "\00:1\0" "b\0" - "On Tue, 2017-09-12@11:38 -0700, Vineet Gupta wrote:\n" + "On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote:\n" "> On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:\n" "> > DW sdio controller has external ciu clock divider controlled\n" "> > via register in SDIO IP. It divides sdio_ref_clk\n" @@ -18,13 +23,13 @@ "> Is this a preventive fix or there are known issues with what we have today.\n" "\n" "Yes, it's kinda a preventive fix.\n" - "We check axs10x?ciu frequency when we found what hsdk?ciu frequency was wrong\n" + "We check axs10x\302\240ciu frequency when we found what hsdk\302\240ciu frequency was wrong\n" "and found that it is wring too.\n" "\n" - "I tried to run SD stress test with wrong ciu?frequency (50000000 Hz) and it passed\n" + "I tried to run SD stress test with wrong ciu\302\240frequency (50000000 Hz) and it passed\n" "successfully, but we must take into account the fact that it depends on SD\n" - "card itself. For example: this SD card mostly works fine on HSDK with ciu?\n" - "frequency 8x times?higher than expected!\n" + "card itself. For example: this SD card mostly works fine on HSDK with ciu\302\240\n" + "frequency 8x times\302\240higher than expected!\n" "\n" "Alexey says that he faced with unstable SD card work on axs103 earlier but\n" "he didn't save any artifacts about it.\n" @@ -33,34 +38,34 @@ "No.\n" "\n" "> > \n" - "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" "> > ---\n" - "> > ? arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-\n" - "> > ? 1 file changed, 8 insertions(+), 1 deletion(-)\n" + "> > \302\240 arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++-\n" + "> > \302\240 1 file changed, 8 insertions(+), 1 deletion(-)\n" "> > \n" "> > diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi\n" "> > index 0ff7e07..7bdf581 100644\n" "> > --- a/arch/arc/boot/dts/axs10x_mb.dtsi\n" "> > +++ b/arch/arc/boot/dts/axs10x_mb.dtsi\n" "> > @@ -44,7 +44,14 @@\n" - "> > ??\n" - "> > ??\t\t\tmmcclk: mmcclk {\n" - "> > ??\t\t\t\tcompatible = \"fixed-clock\";\n" + "> > \302\240\302\240\n" + "> > \302\240\302\240\t\t\tmmcclk: mmcclk {\n" + "> > \302\240\302\240\t\t\t\tcompatible = \"fixed-clock\";\n" "> > -\t\t\t\tclock-frequency = <50000000>;\n" "> > +\t\t\t\t/*\n" - "> > +\t\t\t\t?* DW sdio controller has external ciu clock divider\n" - "> > +\t\t\t\t?* controlled via register in SDIO IP. It divides\n" - "> > +\t\t\t\t?* sdio_ref_clk (which comes from CGU) by 16 for\n" - "> > +\t\t\t\t?* default. So default mmcclk clock (which comes\n" - "> > +\t\t\t\t?* to sdk_in) is 25000000 Hz.\n" - "> > +\t\t\t\t?*/\n" + "> > +\t\t\t\t\302\240* DW sdio controller has external ciu clock divider\n" + "> > +\t\t\t\t\302\240* controlled via register in SDIO IP. It divides\n" + "> > +\t\t\t\t\302\240* sdio_ref_clk (which comes from CGU) by 16 for\n" + "> > +\t\t\t\t\302\240* default. So default mmcclk clock (which comes\n" + "> > +\t\t\t\t\302\240* to sdk_in) is 25000000 Hz.\n" + "> > +\t\t\t\t\302\240*/\n" "> > +\t\t\t\tclock-frequency = <25000000>;\n" - "> > ??\t\t\t\t#clock-cells = <0>;\n" - "> > ??\t\t\t};\n" - "> > ??\n" + "> > \302\240\302\240\t\t\t\t#clock-cells = <0>;\n" + "> > \302\240\302\240\t\t\t};\n" + "> > \302\240\302\240\n" "> \n" "> \n" "-- \n" - ?Eugeniy Paltsev + "\302\240Eugeniy Paltsev" -5ce6dc9fc37d30bb327a9b88a41b80e3f0e9e9f496246d4f04ddcc7a7ad85b00 +fee5740436e4f351938a73f32fefc795123c8e638f0e1c8470d5b95877b46748
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