From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev) Date: Wed, 13 Sep 2017 15:14:45 +0000 Subject: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency In-Reply-To: <4df1bb54-5fa1-5089-7d96-799ccfc78fce@synopsys.com> References: <20170912182045.20941-1-Eugeniy.Paltsev@synopsys.com> <4df1bb54-5fa1-5089-7d96-799ccfc78fce@synopsys.com> List-ID: Message-ID: <1505315684.30546.32.camel@synopsys.com> To: linux-snps-arc@lists.infradead.org On Tue, 2017-09-12@11:38 -0700, Vineet Gupta wrote: > On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote: > > DW sdio controller has external ciu clock divider controlled > > via register in SDIO IP. It divides sdio_ref_clk > > (which comes from CGU) by 16 for default. So default mmcclk > > clock (which comes to sdk_in) is 25000000 Hz. > > > > So fix wrong current value (50000000 Hz) to actual 25000000 Hz. > > Is this a preventive fix or there are known issues with what we have today. Yes, it's kinda a preventive fix. We check axs10x?ciu frequency when we found what hsdk?ciu frequency was wrong and found that it is wring too. I tried to run SD stress test with wrong ciu?frequency (50000000 Hz) and it passed successfully, but we must take into account the fact that it depends on SD card itself. For example: this SD card mostly works fine on HSDK with ciu? frequency 8x times?higher than expected! Alexey says that he faced with unstable SD card work on axs103 earlier but he didn't save any artifacts about it. > Is this triggered after addition of AXS clk driver ? No. > > > > Signed-off-by: Eugeniy Paltsev > > --- > > ? arch/arc/boot/dts/axs10x_mb.dtsi | 9 ++++++++- > > ? 1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi > > index 0ff7e07..7bdf581 100644 > > --- a/arch/arc/boot/dts/axs10x_mb.dtsi > > +++ b/arch/arc/boot/dts/axs10x_mb.dtsi > > @@ -44,7 +44,14 @@ > > ?? > > ?? mmcclk: mmcclk { > > ?? compatible = "fixed-clock"; > > - clock-frequency = <50000000>; > > + /* > > + ?* DW sdio controller has external ciu clock divider > > + ?* controlled via register in SDIO IP. It divides > > + ?* sdio_ref_clk (which comes from CGU) by 16 for > > + ?* default. So default mmcclk clock (which comes > > + ?* to sdk_in) is 25000000 Hz. > > + ?*/ > > + clock-frequency = <25000000>; > > ?? #clock-cells = <0>; > > ?? }; > > ?? > > -- ?Eugeniy Paltsev From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeniy Paltsev Subject: Re: [PATCH] ARC: [plat-axs10x]: DTS: fix sdio ciu frequency Date: Wed, 13 Sep 2017 15:14:45 +0000 Message-ID: <1505315684.30546.32.camel@synopsys.com> References: <20170912182045.20941-1-Eugeniy.Paltsev@synopsys.com> <4df1bb54-5fa1-5089-7d96-799ccfc78fce@synopsys.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <4df1bb54-5fa1-5089-7d96-799ccfc78fce@synopsys.com> Content-Language: en-US Content-ID: Sender: linux-kernel-owner@vger.kernel.org To: Vineet Gupta , "linux-snps-arc@lists.infradead.org" Cc: "linux-kernel@vger.kernel.org" , Alexey Brodkin , "robh+dt@kernel.org" , "devicetree@vger.kernel.org" List-Id: devicetree@vger.kernel.org T24gVHVlLCAyMDE3LTA5LTEyIGF0IDExOjM4IC0wNzAwLCBWaW5lZXQgR3VwdGEgd3JvdGU6DQo+ IE9uIDA5LzEyLzIwMTcgMTE6MjAgQU0sIEV1Z2VuaXkgUGFsdHNldiB3cm90ZToNCj4gPiBEVyBz ZGlvIGNvbnRyb2xsZXIgaGFzIGV4dGVybmFsIGNpdSBjbG9jayBkaXZpZGVyIGNvbnRyb2xsZWQN Cj4gPiB2aWEgcmVnaXN0ZXIgaW4gU0RJTyBJUC4gSXQgZGl2aWRlcyBzZGlvX3JlZl9jbGsNCj4g PiAod2hpY2ggY29tZXMgZnJvbSBDR1UpIGJ5IDE2IGZvciBkZWZhdWx0LiBTbyBkZWZhdWx0IG1t Y2Nsaw0KPiA+IGNsb2NrICh3aGljaCBjb21lcyB0byBzZGtfaW4pIGlzIDI1MDAwMDAwIEh6Lg0K PiA+IA0KPiA+IFNvIGZpeCB3cm9uZyBjdXJyZW50IHZhbHVlICg1MDAwMDAwMCBIeikgdG8gYWN0 dWFsIDI1MDAwMDAwIEh6Lg0KPiANCj4gSXMgdGhpcyBhIHByZXZlbnRpdmUgZml4IG9yIHRoZXJl IGFyZSBrbm93biBpc3N1ZXMgd2l0aCB3aGF0IHdlIGhhdmUgdG9kYXkuDQoNClllcywgaXQncyBr aW5kYSBhIHByZXZlbnRpdmUgZml4Lg0KV2UgY2hlY2sgYXhzMTB4wqBjaXUgZnJlcXVlbmN5IHdo ZW4gd2UgZm91bmQgd2hhdCBoc2RrwqBjaXUgZnJlcXVlbmN5IHdhcyB3cm9uZw0KYW5kIGZvdW5k IHRoYXQgaXQgaXMgd3JpbmcgdG9vLg0KDQpJIHRyaWVkIHRvIHJ1biBTRCBzdHJlc3MgdGVzdCB3 aXRoIHdyb25nIGNpdcKgZnJlcXVlbmN5ICg1MDAwMDAwMCBIeikgYW5kIGl0IHBhc3NlZA0Kc3Vj Y2Vzc2Z1bGx5LCBidXQgd2UgbXVzdCB0YWtlIGludG8gYWNjb3VudCB0aGUgZmFjdCB0aGF0IGl0 IGRlcGVuZHMgb24gU0QNCmNhcmQgaXRzZWxmLiBGb3IgZXhhbXBsZTogdGhpcyBTRCBjYXJkIG1v c3RseSB3b3JrcyBmaW5lIG9uIEhTREsgd2l0aCBjaXXCoA0KZnJlcXVlbmN5IDh4IHRpbWVzwqBo aWdoZXIgdGhhbiBleHBlY3RlZCENCg0KQWxleGV5IHNheXMgdGhhdCBoZSBmYWNlZCB3aXRoIHVu c3RhYmxlIFNEIGNhcmQgd29yayBvbiBheHMxMDMgZWFybGllciBidXQNCmhlIGRpZG4ndCBzYXZl IGFueSBhcnRpZmFjdHMgYWJvdXQgaXQuDQoNCj4gSXMgdGhpcyB0cmlnZ2VyZWQgYWZ0ZXIgYWRk aXRpb24gb2YgQVhTIGNsayBkcml2ZXIgPw0KTm8uDQoNCj4gPiANCj4gPiBTaWduZWQtb2ZmLWJ5 OiBFdWdlbml5IFBhbHRzZXYgPEV1Z2VuaXkuUGFsdHNldkBzeW5vcHN5cy5jb20+DQo+ID4gLS0t DQo+ID4gwqAgYXJjaC9hcmMvYm9vdC9kdHMvYXhzMTB4X21iLmR0c2kgfCA5ICsrKysrKysrLQ0K PiA+IMKgIDEgZmlsZSBjaGFuZ2VkLCA4IGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkNCj4g PiANCj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcmMvYm9vdC9kdHMvYXhzMTB4X21iLmR0c2kgYi9h cmNoL2FyYy9ib290L2R0cy9heHMxMHhfbWIuZHRzaQ0KPiA+IGluZGV4IDBmZjdlMDcuLjdiZGY1 ODEgMTAwNjQ0DQo+ID4gLS0tIGEvYXJjaC9hcmMvYm9vdC9kdHMvYXhzMTB4X21iLmR0c2kNCj4g PiArKysgYi9hcmNoL2FyYy9ib290L2R0cy9heHMxMHhfbWIuZHRzaQ0KPiA+IEBAIC00NCw3ICs0 NCwxNCBAQA0KPiA+IMKgwqANCj4gPiDCoMKgCQkJbW1jY2xrOiBtbWNjbGsgew0KPiA+IMKgwqAJ CQkJY29tcGF0aWJsZSA9ICJmaXhlZC1jbG9jayI7DQo+ID4gLQkJCQljbG9jay1mcmVxdWVuY3kg PSA8NTAwMDAwMDA+Ow0KPiA+ICsJCQkJLyoNCj4gPiArCQkJCcKgKiBEVyBzZGlvIGNvbnRyb2xs ZXIgaGFzIGV4dGVybmFsIGNpdSBjbG9jayBkaXZpZGVyDQo+ID4gKwkJCQnCoCogY29udHJvbGxl ZCB2aWEgcmVnaXN0ZXIgaW4gU0RJTyBJUC4gSXQgZGl2aWRlcw0KPiA+ICsJCQkJwqAqIHNkaW9f cmVmX2NsayAod2hpY2ggY29tZXMgZnJvbSBDR1UpIGJ5IDE2IGZvcg0KPiA+ICsJCQkJwqAqIGRl ZmF1bHQuIFNvIGRlZmF1bHQgbW1jY2xrIGNsb2NrICh3aGljaCBjb21lcw0KPiA+ICsJCQkJwqAq IHRvIHNka19pbikgaXMgMjUwMDAwMDAgSHouDQo+ID4gKwkJCQnCoCovDQo+ID4gKwkJCQljbG9j ay1mcmVxdWVuY3kgPSA8MjUwMDAwMDA+Ow0KPiA+IMKgwqAJCQkJI2Nsb2NrLWNlbGxzID0gPDA+ Ow0KPiA+IMKgwqAJCQl9Ow0KPiA+IMKgwqANCj4gDQo+IA0KLS0gDQrCoEV1Z2VuaXkgUGFsdHNl dg==