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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare
Date: Mon, 25 Sep 2017 20:47:33 -0300	[thread overview]
Message-ID: <1506383253.2634.3.camel@intel.com> (raw)
In-Reply-To: <20170925231624.uo4656ntciq3e6nu@intel.com>

Em Seg, 2017-09-25 às 16:16 -0700, Rodrigo Vivi escreveu:
> Shouldn't we filter them out per platform?

Yes, although doing it like this doesn't hurt much. See the cover
letter: we can probably organize our structs in per-platform unions or
something like that.

Thanks for the review.

> 
> Anyways it is good for me
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> On Fri, Sep 22, 2017 at 08:53:42PM +0000, Paulo Zanoni wrote:
> > Looks like we were missing them.
> > 
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 026fa54..64a4105 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -11336,6 +11336,18 @@ intel_pipe_config_compare(struct
> > drm_i915_private *dev_priv,
> >  	PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> >  	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> >  	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > +	PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> >  
> >  	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> >  	PIPE_CONF_CHECK_X(dsi_pll.div);
> > -- 
> > 2.9.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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  reply	other threads:[~2017-09-25 23:47 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-22 20:53 [PATCH 0/2] Add missing BXT/CNL DPLL debugging/checking code Paulo Zanoni
2017-09-22 20:53 ` [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare Paulo Zanoni
2017-09-25 23:16   ` Rodrigo Vivi
2017-09-25 23:47     ` Paulo Zanoni [this message]
2017-09-22 20:53 ` [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info Paulo Zanoni
2017-09-25 23:21   ` Rodrigo Vivi
2017-09-22 21:23 ` ✗ Fi.CI.BAT: failure for Add missing BXT/CNL DPLL debugging/checking code Patchwork
2017-09-23  8:05 ` ✓ Fi.CI.BAT: success " Patchwork
2017-09-23  9:19 ` ✓ Fi.CI.IGT: " Patchwork

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