From: See, Chin Liang <chin.liang.see@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 06/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC
Date: Fri, 29 Sep 2017 12:51:58 +0000 [thread overview]
Message-ID: <1506775964.2766.1.camel@intel.com> (raw)
In-Reply-To: <CADhT+weDn14XjOF4i6ucLvin7LtS1C_hEu9gYrMsfhr09kDRjg@mail.gmail.com>
On Tue, 2017-09-26 at 17:46 -0500, Dinh Nguyen wrote:
> On Tue, Sep 19, 2017 at 4:22 AM, <chin.liang.see@intel.com> wrote:
> >
> > From: Chin Liang See <chin.liang.see@intel.com>
> >
> > Add misc support for Stratix SoC
> Just because the file is call misc.c doesn't mean you can just keep
> the commit
> message that simple. Can you add what functions are you adding?
>
Definitely can add more details here
> >
> >
> > Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> > ---
> > arch/arm/mach-socfpga/Makefile | 1 +
> > arch/arm/mach-socfpga/misc.c | 4 +
> > arch/arm/mach-socfpga/misc_s10.c | 165
> > +++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 170 insertions(+)
> > create mode 100644 arch/arm/mach-socfpga/misc_s10.c
> >
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index 910eb6f..b253914 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -32,6 +32,7 @@ endif
> >
> > ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
> > obj-y += clock_manager_s10.o
> > +obj-y += misc_s10.o
> > obj-y += reset_manager_s10.o
> > obj-y += system_manager_s10.o
> > obj-y += wrap_pinmux_config_s10.o
> > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-
> > socfpga/misc.c
> > index 00eff90..2ea94bc 100644
> > --- a/arch/arm/mach-socfpga/misc.c
> > +++ b/arch/arm/mach-socfpga/misc.c
> > @@ -23,8 +23,10 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +#ifdef CONFIG_SYS_L2_PL310
> > static const struct pl310_regs *const pl310 =
> > (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > +#endif
> >
> > struct bsel bsel_str[] = {
> > { "rsvd", "Reserved", },
> > @@ -53,6 +55,7 @@ void enable_caches(void)
> > #endif
> > }
> >
> > +#ifdef CONFIG_SYS_L2_PL310
> > void v7_outer_cache_enable(void)
> > {
> > /* Disable the L2 cache */
> > @@ -73,6 +76,7 @@ void v7_outer_cache_disable(void)
> > /* Disable the L2 cache */
> > clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
> > }
> > +#endif
> >
> > #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
> > defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
> > diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-
> > socfpga/misc_s10.c
> > new file mode 100644
> > index 0000000..b84f055
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/misc_s10.c
> This misc_s10.c look very similar to the Gen5 stuff, can you re-use
> it?
Yes, its true.
Let me move eth stuff to common.
Chin Liang
>
> Dinh
next prev parent reply other threads:[~2017-09-29 12:51 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-19 9:22 [U-Boot] [PATCH 00/14] Enable Stratix10 SoC support chin.liang.see at intel.com
2017-09-19 9:22 ` [U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC chin.liang.see at intel.com
2017-09-19 9:51 ` Marek Vasut
2017-09-19 13:13 ` See, Chin Liang
2017-09-19 9:22 ` [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC chin.liang.see at intel.com
2017-09-26 21:34 ` Dinh Nguyen
2017-09-29 13:06 ` See, Chin Liang
2017-09-26 21:37 ` Dinh Nguyen
2017-09-29 13:07 ` See, Chin Liang
2017-09-19 9:22 ` [U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock Manager driver " chin.liang.see at intel.com
2017-09-26 22:04 ` Dinh Nguyen
2017-09-29 12:58 ` See, Chin Liang
2017-09-19 9:22 ` [U-Boot] [PATCH 04/14] arm: socfpga: stratix10: Add Reset " chin.liang.see at intel.com
2017-09-26 22:08 ` Dinh Nguyen
2017-09-29 12:53 ` See, Chin Liang
2017-10-02 14:10 ` Dinh Nguyen
2017-09-19 9:22 ` [U-Boot] [PATCH 05/14] arm: socfpga: stratix10: Add pinmux support " chin.liang.see at intel.com
2017-09-19 9:22 ` [U-Boot] [PATCH 06/14] arm: socfpga: stratix10: Add misc " chin.liang.see at intel.com
2017-09-26 22:46 ` Dinh Nguyen
2017-09-29 12:51 ` See, Chin Liang [this message]
2017-09-19 9:22 ` [U-Boot] [PATCH 07/14] arm: socfpga: stratix10: Add mailbox " chin.liang.see at intel.com
2017-09-19 9:22 ` [U-Boot] [PATCH 08/14] arm: socfpga: stratix10: Add MMU " chin.liang.see at intel.com
2017-09-19 9:22 ` [U-Boot] [PATCH 09/14] arm: socfpga: Restructure the SPL file chin.liang.see at intel.com
2017-09-19 9:22 ` [U-Boot] [PATCH 10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC chin.liang.see at intel.com
2017-09-19 9:22 ` [U-Boot] [PATCH 11/14] arm: socfpga: stratix10: Add timer support " chin.liang.see at intel.com
2017-09-19 9:22 ` [U-Boot] [PATCH 12/14] ddr: altera: stratix10: Add DDR " chin.liang.see at intel.com
2017-09-19 9:22 ` [U-Boot] [PATCH 13/14] board: altera: stratix10: Add socdk board " chin.liang.see at intel.com
2017-09-19 9:22 ` [U-Boot] [PATCH 14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build chin.liang.see at intel.com
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1506775964.2766.1.camel@intel.com \
--to=chin.liang.see@intel.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.