diff for duplicates of <1507185388.5452.61.camel@aj.id.au> diff --git a/a/1.txt b/N1/1.txt index 7ef9411..fafd9ac 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ On Tue, 2017-10-03 at 17:25 +1030, Joel Stanley wrote: > This adds the stub of a driver for the ASPEED SoCs. The clocks are > defined and the static registration is set up. -> +>? > Signed-off-by: Joel Stanley <joel@jms.id.au> With respect to use of the Aspeed hardware, @@ -10,30 +10,30 @@ Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > --- > v3: -> - use named initlisers for aspeed_gates table -> - fix clocks typo -> - Move ASPEED_NUM_CLKS to the bottom of the list -> - Put gates at the start of the list, so we can use them to initalise -> the aspeed_gates table -> - Add ASPEED_CLK_SELECTION_2 -> - Set parent of network MAC gates +> ?- use named initlisers for aspeed_gates table +> ?- fix clocks typo +> ?- Move ASPEED_NUM_CLKS to the bottom of the list +> ?- Put gates at the start of the list, so we can use them to initalise +> ???the aspeed_gates table +> ?- Add ASPEED_CLK_SELECTION_2 +> ?- Set parent of network MAC gates > --- -> drivers/clk/Kconfig | 12 +++ -> drivers/clk/Makefile | 1 + -> drivers/clk/clk-aspeed.c | 148 +++++++++++++++++++++++++++++++ -> include/dt-bindings/clock/aspeed-clock.h | 42 +++++++++ -> 4 files changed, 203 insertions(+) -> create mode 100644 drivers/clk/clk-aspeed.c -> create mode 100644 include/dt-bindings/clock/aspeed-clock.h -> +> ?drivers/clk/Kconfig??????????????????????|??12 +++ +> ?drivers/clk/Makefile?????????????????????|???1 + +> ?drivers/clk/clk-aspeed.c?????????????????| 148 +++++++++++++++++++++++++++++++ +> ?include/dt-bindings/clock/aspeed-clock.h |??42 +++++++++ +> ?4 files changed, 203 insertions(+) +> ?create mode 100644 drivers/clk/clk-aspeed.c +> ?create mode 100644 include/dt-bindings/clock/aspeed-clock.h +>? > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index 1c4e1aa6767e..9abe063ef8d2 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -142,6 +142,18 @@ config COMMON_CLK_GEMINI -> This driver supports the SoC clocks on the Cortina Systems Gemini -> platform, also known as SL3516 or CS3516. -> +> ? ??This driver supports the SoC clocks on the Cortina Systems Gemini +> ? ??platform, also known as SL3516 or CS3516. +> ? > +config COMMON_CLK_ASPEED > + bool "Clock driver for Aspeed BMC SoCs" > + depends on ARCH_ASPEED || COMPILE_TEST @@ -41,26 +41,26 @@ Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > + select MFD_SYSCON > + select RESET_CONTROLLER > + ---help--- -> + This driver supports the SoC clocks on the Aspeed BMC platforms. +> + ??This driver supports the SoC clocks on the Aspeed BMC platforms. > + -> + The G4 and G5 series, including the ast2400 and ast2500, are supported -> + by this driver. +> + ??The G4 and G5 series, including the ast2400 and ast2500, are supported +> + ??by this driver. > + -> config COMMON_CLK_S2MPS11 -> tristate "Clock driver for S2MPS1X/S5M8767 MFD" -> depends on MFD_SEC_CORE || COMPILE_TEST +> ?config COMMON_CLK_S2MPS11 +> ? tristate "Clock driver for S2MPS1X/S5M8767 MFD" +> ? depends on MFD_SEC_CORE || COMPILE_TEST > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index c99f363826f0..575c68919d9b 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o -> obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o -> obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o -> obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o +> ?obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o +> ?obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o +> ?obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o > +obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o -> obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o -> obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o -> obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o +> ?obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o +> ?obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o +> ?obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o > diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c > new file mode 100644 > index 000000000000..a45eb351bb05 @@ -100,7 +100,7 @@ Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > + * struct aspeed_gate_data - Aspeed gated clocks > + * @clock_idx: bit used to gate this clock in the clock register > + * @reset_idx: bit used to reset this IP in the reset register. -1 if no -> + * reset is required when enabling the clock +> + *?????????????reset is required when enabling the clock > + * @name: the clock name > + * @parent_name: the name of the parent clock > + * @flags: standard clock framework flags @@ -140,19 +140,19 @@ Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > + > +/* TODO: ask Aspeed about the actual parent data */ > +static const struct aspeed_gate_data aspeed_gates[] __initconst = { -> + /* clk rst name parent flags */ -> + [ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ -> + [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ -> + [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ -> + [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ -> + [ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ -> + [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */ -> + [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, -> + [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ -> + [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */ -> + [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ +> + /* ?clk rst???name parent flags */ +> + [ASPEED_CLK_GATE_ECLK] = {??0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ +> + [ASPEED_CLK_GATE_GCLK] = {??1,??7, "gclk-gate", NULL, 0 }, /* 2D engine */ +> + [ASPEED_CLK_GATE_MCLK] = {??2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ +> + [ASPEED_CLK_GATE_VCLK] = {??3,??6, "vclk-gate", NULL, 0 }, /* Video Capture */ +> + [ASPEED_CLK_GATE_BCLK] = {??4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ +> + [ASPEED_CLK_GATE_DCLK] = {??5, -1, "dclk-gate", NULL, 0 }, /* DAC */ +> + [ASPEED_CLK_GATE_REFCLK] = {??6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, +> + [ASPEED_CLK_GATE_USBPORT2CLK] = {??7,??3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ +> + [ASPEED_CLK_GATE_LCLK] = {??8,??5, "lclk-gate", NULL, 0 }, /* LPC */ +> + [ASPEED_CLK_GATE_USBUHCICLK] = {??9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ > + [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */ -> + [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ +> + [ASPEED_CLK_GATE_YCLK] = { 13,??4, "yclk-gate", NULL, 0 }, /* HAC */ > + [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ > + [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ > + [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ @@ -185,9 +185,9 @@ Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > + return; > + > + /* -> + * This way all clocks fetched before the platform device probes, -> + * except those we assign here for early use, will be deferred. -> + */ +> + ?* This way all clocks fetched before the platform device probes, +> + ?* except those we assign here for early use, will be deferred. +> + ?*/ > + for (i = 0; i < ASPEED_NUM_CLKS; i++) > + aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); > + @@ -197,11 +197,11 @@ Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > + return; > + } > + /* -> + * We check that the regmap works on this very first access, -> + * but as this is an MMIO-backed regmap, subsequent regmap -> + * access is not going to fail and we skip error checks from -> + * this point. -> + */ +> + ?* We check that the regmap works on this very first access, +> + ?* but as this is an MMIO-backed regmap, subsequent regmap +> + ?* access is not going to fail and we skip error checks from +> + ?* this point. +> + ?*/ > + ret = regmap_read(map, ASPEED_STRAP, &val); > + if (ret) { > + pr_err("failed to read strapping register\n"); @@ -263,3 +263,10 @@ Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > +#define ASPEED_NUM_CLKS 35 > + > +#endif +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: signature.asc +Type: application/pgp-signature +Size: 801 bytes +Desc: This is a digitally signed message part +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20171005/9e67fbdd/attachment-0001.sig> diff --git a/a/2.bin b/a/2.bin deleted file mode 100644 index 049c654..0000000 --- a/a/2.bin +++ /dev/null @@ -1,16 +0,0 @@ ------BEGIN PGP SIGNATURE----- - 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"From\0Andrew Jeffery <andrew@aj.id.au>\0" - "Subject\0Re: [PATCH v4 1/5] clk: Add clock driver for ASPEED BMC SoCs\0" + "From\0andrew@aj.id.au (Andrew Jeffery)\0" + "Subject\0[PATCH v4 1/5] clk: Add clock driver for ASPEED BMC SoCs\0" "Date\0Thu, 05 Oct 2017 17:06:28 +1030\0" - "To\0Joel Stanley <joel@jms.id.au>" - Lee Jones <lee.jones@linaro.org> - Michael Turquette <mturquette@baylibre.com> - " Stephen Boyd <sboyd@codeaurora.org>\0" - "Cc\0linux-kernel@vger.kernel.org" - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - Benjamin Herrenschmidt <benh@kernel.crashing.org> - Jeremy Kerr <jk@ozlabs.org> - Rick Altherr <raltherr@google.com> - Ryan Chen <ryan_chen@aspeedtech.com> - " Arnd Bergmann <arnd@arndb.de>\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "On Tue, 2017-10-03 at 17:25 +1030, Joel Stanley wrote:\n" "> This adds the stub of a driver for the ASPEED SoCs. The clocks are\n" "> defined and the static registration is set up.\n" - ">\302\240\n" + ">?\n" "> Signed-off-by: Joel Stanley <joel@jms.id.au>\n" "\n" "With respect to use of the Aspeed hardware,\n" @@ -29,30 +18,30 @@ "\n" "> ---\n" "> v3:\n" - "> \302\240- use named initlisers for aspeed_gates table\n" - "> \302\240- fix clocks typo\n" - "> \302\240- Move ASPEED_NUM_CLKS to the bottom of the list\n" - "> \302\240- Put gates at the start of the list, so we can use them to initalise\n" - "> \302\240\302\240\302\240the aspeed_gates table\n" - "> \302\240- Add ASPEED_CLK_SELECTION_2\n" - "> \302\240- Set parent of network MAC gates\n" + "> ?- use named initlisers for aspeed_gates table\n" + "> ?- fix clocks typo\n" + "> ?- Move ASPEED_NUM_CLKS to the bottom of the list\n" + "> ?- Put gates at the start of the list, so we can use them to initalise\n" + "> ???the aspeed_gates table\n" + "> ?- Add ASPEED_CLK_SELECTION_2\n" + "> ?- Set parent of network MAC gates\n" "> ---\n" - "> \302\240drivers/clk/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\24012 +++\n" - "> \302\240drivers/clk/Makefile\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\240\302\2401 +\n" - "> \302\240drivers/clk/clk-aspeed.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 148 +++++++++++++++++++++++++++++++\n" - "> \302\240include/dt-bindings/clock/aspeed-clock.h |\302\240\302\24042 +++++++++\n" - "> \302\2404 files changed, 203 insertions(+)\n" - "> \302\240create mode 100644 drivers/clk/clk-aspeed.c\n" - "> \302\240create mode 100644 include/dt-bindings/clock/aspeed-clock.h\n" - ">\302\240\n" + "> ?drivers/clk/Kconfig??????????????????????|??12 +++\n" + "> ?drivers/clk/Makefile?????????????????????|???1 +\n" + "> ?drivers/clk/clk-aspeed.c?????????????????| 148 +++++++++++++++++++++++++++++++\n" + "> ?include/dt-bindings/clock/aspeed-clock.h |??42 +++++++++\n" + "> ?4 files changed, 203 insertions(+)\n" + "> ?create mode 100644 drivers/clk/clk-aspeed.c\n" + "> ?create mode 100644 include/dt-bindings/clock/aspeed-clock.h\n" + ">?\n" "> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig\n" "> index 1c4e1aa6767e..9abe063ef8d2 100644\n" "> --- a/drivers/clk/Kconfig\n" "> +++ b/drivers/clk/Kconfig\n" "> @@ -142,6 +142,18 @@ config COMMON_CLK_GEMINI\n" - "> \302\240\t\302\240\302\240This driver supports the SoC clocks on the Cortina Systems Gemini\n" - "> \302\240\t\302\240\302\240platform, also known as SL3516 or CS3516.\n" - "> \302\240\n" + "> ?\t??This driver supports the SoC clocks on the Cortina Systems Gemini\n" + "> ?\t??platform, also known as SL3516 or CS3516.\n" + "> ?\n" "> +config COMMON_CLK_ASPEED\n" "> +\tbool \"Clock driver for Aspeed BMC SoCs\"\n" "> +\tdepends on ARCH_ASPEED || COMPILE_TEST\n" @@ -60,26 +49,26 @@ "> +\tselect MFD_SYSCON\n" "> +\tselect RESET_CONTROLLER\n" "> +\t---help---\n" - "> +\t\302\240\302\240This driver supports the SoC clocks on the Aspeed BMC platforms.\n" + "> +\t??This driver supports the SoC clocks on the Aspeed BMC platforms.\n" "> +\n" - "> +\t\302\240\302\240The G4 and G5 series, including the ast2400 and ast2500, are supported\n" - "> +\t\302\240\302\240by this driver.\n" + "> +\t??The G4 and G5 series, including the ast2400 and ast2500, are supported\n" + "> +\t??by this driver.\n" "> +\n" - "> \302\240config COMMON_CLK_S2MPS11\n" - "> \302\240\ttristate \"Clock driver for S2MPS1X/S5M8767 MFD\"\n" - "> \302\240\tdepends on MFD_SEC_CORE || COMPILE_TEST\n" + "> ?config COMMON_CLK_S2MPS11\n" + "> ?\ttristate \"Clock driver for S2MPS1X/S5M8767 MFD\"\n" + "> ?\tdepends on MFD_SEC_CORE || COMPILE_TEST\n" "> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\n" "> index c99f363826f0..575c68919d9b 100644\n" "> --- a/drivers/clk/Makefile\n" "> +++ b/drivers/clk/Makefile\n" "> @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_CLPS711X)\t\t+= clk-clps711x.o\n" - "> \302\240obj-$(CONFIG_COMMON_CLK_CS2000_CP)\t+= clk-cs2000-cp.o\n" - "> \302\240obj-$(CONFIG_ARCH_EFM32)\t\t+= clk-efm32gg.o\n" - "> \302\240obj-$(CONFIG_COMMON_CLK_GEMINI)\t\t+= clk-gemini.o\n" + "> ?obj-$(CONFIG_COMMON_CLK_CS2000_CP)\t+= clk-cs2000-cp.o\n" + "> ?obj-$(CONFIG_ARCH_EFM32)\t\t+= clk-efm32gg.o\n" + "> ?obj-$(CONFIG_COMMON_CLK_GEMINI)\t\t+= clk-gemini.o\n" "> +obj-$(CONFIG_COMMON_CLK_ASPEED)\t\t+= clk-aspeed.o\n" - "> \302\240obj-$(CONFIG_ARCH_HIGHBANK)\t\t+= clk-highbank.o\n" - "> \302\240obj-$(CONFIG_CLK_HSDK)\t\t\t+= clk-hsdk-pll.o\n" - "> \302\240obj-$(CONFIG_COMMON_CLK_MAX77686)\t+= clk-max77686.o\n" + "> ?obj-$(CONFIG_ARCH_HIGHBANK)\t\t+= clk-highbank.o\n" + "> ?obj-$(CONFIG_CLK_HSDK)\t\t\t+= clk-hsdk-pll.o\n" + "> ?obj-$(CONFIG_COMMON_CLK_MAX77686)\t+= clk-max77686.o\n" "> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c\n" "> new file mode 100644\n" "> index 000000000000..a45eb351bb05\n" @@ -119,7 +108,7 @@ "> + * struct aspeed_gate_data - Aspeed gated clocks\n" "> + * @clock_idx: bit used to gate this clock in the clock register\n" "> + * @reset_idx: bit used to reset this IP in the reset register. -1 if no\n" - "> + *\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240reset is required when enabling the clock\n" + "> + *?????????????reset is required when enabling the clock\n" "> + * @name: the clock name\n" "> + * @parent_name: the name of the parent clock\n" "> + * @flags: standard clock framework flags\n" @@ -159,19 +148,19 @@ "> +\n" "> +/* TODO: ask Aspeed about the actual parent data */\n" "> +static const struct aspeed_gate_data aspeed_gates[] __initconst = {\n" - "> +\t/*\t\t\t\t\302\240clk rst\302\240\302\240\302\240name\t\t\tparent\tflags */\n" - "> +\t[ASPEED_CLK_GATE_ECLK] =\t{\302\240\302\2400, -1, \"eclk-gate\",\t\t\"eclk\",\t0 }, /* Video Engine */\n" - "> +\t[ASPEED_CLK_GATE_GCLK] =\t{\302\240\302\2401,\302\240\302\2407, \"gclk-gate\",\t\tNULL,\t0 }, /* 2D engine */\n" - "> +\t[ASPEED_CLK_GATE_MCLK] =\t{\302\240\302\2402, -1, \"mclk-gate\",\t\t\"mpll\",\tCLK_IS_CRITICAL }, /* SDRAM */\n" - "> +\t[ASPEED_CLK_GATE_VCLK] =\t{\302\240\302\2403,\302\240\302\2406, \"vclk-gate\",\t\tNULL,\t0 }, /* Video Capture */\n" - "> +\t[ASPEED_CLK_GATE_BCLK] =\t{\302\240\302\2404, 10, \"bclk-gate\",\t\t\"bclk\",\t0 }, /* PCIe/PCI */\n" - "> +\t[ASPEED_CLK_GATE_DCLK] =\t{\302\240\302\2405, -1, \"dclk-gate\",\t\tNULL,\t0 }, /* DAC */\n" - "> +\t[ASPEED_CLK_GATE_REFCLK] =\t{\302\240\302\2406, -1, \"refclk-gate\",\t\"clkin\", CLK_IS_CRITICAL },\n" - "> +\t[ASPEED_CLK_GATE_USBPORT2CLK] =\t{\302\240\302\2407,\302\240\302\2403, \"usb-port2-gate\",\tNULL,\t0 }, /* USB2.0 Host port 2 */\n" - "> +\t[ASPEED_CLK_GATE_LCLK] =\t{\302\240\302\2408,\302\240\302\2405, \"lclk-gate\",\t\tNULL,\t0 }, /* LPC */\n" - "> +\t[ASPEED_CLK_GATE_USBUHCICLK] =\t{\302\240\302\2409, 15, \"usb-uhci-gate\",\tNULL,\t0 }, /* USB1.1 (requires port 2 enabled) */\n" + "> +\t/*\t\t\t\t?clk rst???name\t\t\tparent\tflags */\n" + "> +\t[ASPEED_CLK_GATE_ECLK] =\t{??0, -1, \"eclk-gate\",\t\t\"eclk\",\t0 }, /* Video Engine */\n" + "> +\t[ASPEED_CLK_GATE_GCLK] =\t{??1,??7, \"gclk-gate\",\t\tNULL,\t0 }, /* 2D engine */\n" + "> +\t[ASPEED_CLK_GATE_MCLK] =\t{??2, -1, \"mclk-gate\",\t\t\"mpll\",\tCLK_IS_CRITICAL }, /* SDRAM */\n" + "> +\t[ASPEED_CLK_GATE_VCLK] =\t{??3,??6, \"vclk-gate\",\t\tNULL,\t0 }, /* Video Capture */\n" + "> +\t[ASPEED_CLK_GATE_BCLK] =\t{??4, 10, \"bclk-gate\",\t\t\"bclk\",\t0 }, /* PCIe/PCI */\n" + "> +\t[ASPEED_CLK_GATE_DCLK] =\t{??5, -1, \"dclk-gate\",\t\tNULL,\t0 }, /* DAC */\n" + "> +\t[ASPEED_CLK_GATE_REFCLK] =\t{??6, -1, \"refclk-gate\",\t\"clkin\", CLK_IS_CRITICAL },\n" + "> +\t[ASPEED_CLK_GATE_USBPORT2CLK] =\t{??7,??3, \"usb-port2-gate\",\tNULL,\t0 }, /* USB2.0 Host port 2 */\n" + "> +\t[ASPEED_CLK_GATE_LCLK] =\t{??8,??5, \"lclk-gate\",\t\tNULL,\t0 }, /* LPC */\n" + "> +\t[ASPEED_CLK_GATE_USBUHCICLK] =\t{??9, 15, \"usb-uhci-gate\",\tNULL,\t0 }, /* USB1.1 (requires port 2 enabled) */\n" "> +\t[ASPEED_CLK_GATE_D1CLK] =\t{ 10, 13, \"d1clk-gate\",\t\tNULL,\t0 }, /* GFX CRT */\n" - "> +\t[ASPEED_CLK_GATE_YCLK] =\t{ 13,\302\240\302\2404, \"yclk-gate\",\t\tNULL,\t0 }, /* HAC */\n" + "> +\t[ASPEED_CLK_GATE_YCLK] =\t{ 13,??4, \"yclk-gate\",\t\tNULL,\t0 }, /* HAC */\n" "> +\t[ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, \"usb-port1-gate\",\tNULL,\t0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */\n" "> +\t[ASPEED_CLK_GATE_UART1CLK] =\t{ 15, -1, \"uart1clk-gate\",\t\"uart\",\t0 }, /* UART1 */\n" "> +\t[ASPEED_CLK_GATE_UART2CLK] =\t{ 16, -1, \"uart2clk-gate\",\t\"uart\",\t0 }, /* UART2 */\n" @@ -204,9 +193,9 @@ "> +\t\treturn;\n" "> +\n" "> +\t/*\n" - "> +\t\302\240* This way all clocks fetched before the platform device probes,\n" - "> +\t\302\240* except those we assign here for early use, will be deferred.\n" - "> +\t\302\240*/\n" + "> +\t?* This way all clocks fetched before the platform device probes,\n" + "> +\t?* except those we assign here for early use, will be deferred.\n" + "> +\t?*/\n" "> +\tfor (i = 0; i < ASPEED_NUM_CLKS; i++)\n" "> +\t\taspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);\n" "> +\n" @@ -216,11 +205,11 @@ "> +\t\treturn;\n" "> +\t}\n" "> +\t/*\n" - "> +\t\302\240* We check that the regmap works on this very first access,\n" - "> +\t\302\240* but as this is an MMIO-backed regmap, subsequent regmap\n" - "> +\t\302\240* access is not going to fail and we skip error checks from\n" - "> +\t\302\240* this point.\n" - "> +\t\302\240*/\n" + "> +\t?* We check that the regmap works on this very first access,\n" + "> +\t?* but as this is an MMIO-backed regmap, subsequent regmap\n" + "> +\t?* access is not going to fail and we skip error checks from\n" + "> +\t?* this point.\n" + "> +\t?*/\n" "> +\tret = regmap_read(map, ASPEED_STRAP, &val);\n" "> +\tif (ret) {\n" "> +\t\tpr_err(\"failed to read strapping register\\n\");\n" @@ -281,26 +270,13 @@ "> +\n" "> +#define ASPEED_NUM_CLKS\t\t\t35\n" "> +\n" - > +#endif - "\01:2\0" - "fn\0signature.asc\0" - "d\0This is a digitally signed message part\0" - "b\0" - "-----BEGIN PGP SIGNATURE-----\n" - "\n" - "iQIcBAABCgAGBQJZ1dLtAAoJEJ0dnzgO5LT5RjwQAITk2RyyhKAwVAozJvPpl7e5\n" - "H2kyJr5veBbkex1H0vgmLTue/FvR7UO7lQG/csgDvE36662yl0pwlZaLGAmHmILE\n" - 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