diff for duplicates of <1507186800.5452.63.camel@aj.id.au> diff --git a/a/1.txt b/N1/1.txt index f8db26a..c2076ed 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,53 +2,53 @@ On Tue, 2017-10-03 at 17:25 +1030, Joel Stanley wrote: > This registers the core clocks; those which are required to calculate > the rate of the timer peripheral so the system can load a clocksource > driver. -> +>? > Signed-off-by: Joel Stanley <joel@jms.id.au> -> +>? > --- > v4: -> - Add defines to document the BIT() macros +> ? - Add defines to document the BIT() macros > v3: -> - Fix ast2400 ahb calculation -> - Remove incorrect 'this is wrong' comment -> - Separate out clkin calc to be per platform -> - Support 48MHz clkin on ast2400 +> ? - Fix ast2400 ahb calculation +> ? - Remove incorrect 'this is wrong' comment +> ? - Separate out clkin calc to be per platform +> ? - Support 48MHz clkin on ast2400 > --- -> drivers/clk/clk-aspeed.c | 177 +++++++++++++++++++++++++++++++++++++++++++++++ -> 1 file changed, 177 insertions(+) -> +> ?drivers/clk/clk-aspeed.c | 177 +++++++++++++++++++++++++++++++++++++++++++++++ +> ?1 file changed, 177 insertions(+) +>? > diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c > index a45eb351bb05..d39cf51a5114 100644 > --- a/drivers/clk/clk-aspeed.c > +++ b/drivers/clk/clk-aspeed.c > @@ -20,7 +20,23 @@ -> -> #include <dt-bindings/clock/aspeed-clock.h> -> +> ? +> ?#include <dt-bindings/clock/aspeed-clock.h> +> ? > +#define ASPEED_RESET_CTRL 0x04 > +#define ASPEED_CLK_SELECTION 0x08 > +#define ASPEED_CLK_STOP_CTRL 0x0c > +#define ASPEED_MPLL_PARAM 0x20 > +#define ASPEED_HPLL_PARAM 0x24 -> +#define AST2500_HPLL_BYPASS_EN BIT(20) -> +#define AST2400_HPLL_STRAPPED BIT(18) -> +#define AST2400_HPLL_BYPASS_EN BIT(17) +> +#define??AST2500_HPLL_BYPASS_EN BIT(20) +> +#define??AST2400_HPLL_STRAPPED BIT(18) +> +#define??AST2400_HPLL_BYPASS_EN BIT(17) > +#define ASPEED_MISC_CTRL 0x2c -> +#define UART_DIV13_EN BIT(12) -> #define ASPEED_STRAP 0x70 -> +#define CLKIN_25MHZ_EN BIT(23) -> +#define AST2400_CLK_SOURCE_SEL BIT(18) +> +#define??UART_DIV13_EN BIT(12) +> ?#define ASPEED_STRAP 0x70 +> +#define??CLKIN_25MHZ_EN BIT(23) +> +#define??AST2400_CLK_SOURCE_SEL BIT(18) > +#define ASPEED_CLK_SELECTION_2 0xd8 > + > +/* Globally visible clocks */ > +static DEFINE_SPINLOCK(aspeed_clk_lock); -> -> /* Keeps track of all clocks */ -> static struct clk_hw_onecell_data *aspeed_clk_data; +> ? +> ?/* Keeps track of all clocks */ +> ?static struct clk_hw_onecell_data *aspeed_clk_data; > @@ -98,6 +114,160 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { -> [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ -> }; -> +> ? [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ +> ?}; +> ? > +static const struct clk_div_table ast2400_div_table[] = { > + { 0x0, 2 }, > + { 0x1, 4 }, @@ -120,9 +120,9 @@ On Tue, 2017-10-03 at 17:25 +1030, Joel Stanley wrote: > + u32 val, freq, div; > + > + /* -> + * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by -> + * strapping -> + */ +> + ?* CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by +> + ?* strapping +> + ?*/ > + regmap_read(map, ASPEED_STRAP, &val); > + if (val & CLKIN_25MHZ_EN) > + freq = 25000000; @@ -134,20 +134,20 @@ On Tue, 2017-10-03 at 17:25 +1030, Joel Stanley wrote: > + pr_debug("clkin @%u MHz\n", freq / 1000000); > + > + /* -> + * High-speed PLL clock derived from the crystal. This the CPU clock, -> + * and we assume that it is enabled -> + */ +> + ?* High-speed PLL clock derived from the crystal. This the CPU clock, +> + ?* and we assume that it is enabled +> + ?*/ > + regmap_read(map, ASPEED_HPLL_PARAM, &val); > + WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured"); > + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val); > + > + /* -> + * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) -> + * 00: Select CPU:AHB = 1:1 -> + * 01: Select CPU:AHB = 2:1 -> + * 10: Select CPU:AHB = 4:1 -> + * 11: Select CPU:AHB = 3:1 -> + */ +> + ?* Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) +> + ?*???00: Select CPU:AHB = 1:1 +> + ?*???01: Select CPU:AHB = 2:1 +> + ?*???10: Select CPU:AHB = 4:1 +> + ?*???11: Select CPU:AHB = 3:1 +> + ?*/ > + regmap_read(map, ASPEED_STRAP, &val); > + val = (val >> 10) & 0x3; > + div = val + 1; @@ -181,9 +181,9 @@ On Tue, 2017-10-03 at 17:25 +1030, Joel Stanley wrote: > + pr_debug("clkin @%u MHz\n", freq / 1000000); > + > + /* -> + * High-speed PLL clock derived from the crystal. This the CPU clock, -> + * and we assume that it is enabled -> + */ +> + ?* High-speed PLL clock derived from the crystal. This the CPU clock, +> + ?* and we assume that it is enabled +> + ?*/ > + regmap_read(map, ASPEED_HPLL_PARAM, &val); > + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); > + @@ -203,13 +203,13 @@ On Tue, 2017-10-03 at 17:25 +1030, Joel Stanley wrote: > + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; > +}; > + -> static void __init aspeed_cc_init(struct device_node *np) -> { -> struct regmap *map; +> ?static void __init aspeed_cc_init(struct device_node *np) +> ?{ +> ? struct regmap *map; > @@ -139,6 +309,13 @@ static void __init aspeed_cc_init(struct device_node *np) -> return; -> } -> +> ? return; +> ? } +> ? > + if (of_device_is_compatible(np, "aspeed,ast2400-scu")) > + aspeed_ast2400_cc(map); > + else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) @@ -222,6 +222,13 @@ I'm still unsure about this approach with the scu compatible, but otherwise: Reviewed-by: Andrew Jeffery <andrew@aj.id.au> -> aspeed_clk_data->num = ASPEED_NUM_CLKS; -> ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); -> if (ret) +> ? aspeed_clk_data->num = ASPEED_NUM_CLKS; +> ? ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); +> ? if (ret) +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: signature.asc +Type: application/pgp-signature +Size: 801 bytes +Desc: This is a digitally signed message part +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20171005/300aa628/attachment.sig> diff --git a/a/2.bin b/a/2.bin deleted file mode 100644 index 6e6b227..0000000 --- a/a/2.bin +++ /dev/null @@ -1,16 +0,0 @@ ------BEGIN PGP SIGNATURE----- - -iQIbBAABCgAGBQJZ1dhwAAoJEJ0dnzgO5LT5TZcP8wRMANyZ8jm8gWhvCKAoGq9F -7PIonE0X7X6bAl4V0rBKQ6DzlueR1Qvw47l3FRGUKClO99czY0PxK2M0sMxE/YTZ -drsz6GfukR51TP6Mfa23+AvtsjoDL/uRDX+BZOR//xO2rCIfDf8iqBdZwAPzxxWN -pL5ThzNMhFdgwb/GWyF7aUMulcqI4UJf94MJVm5XHS43Eggdn7IPxTCYNrvTlMF2 -nppRPDu3i0Lbx1paxukhG7Ryb9Gzo/7W8gwD6zmWe4Ohi/hzsH7k0xcXyaqZEhFk -HY3DuobIAU/gmxXHHHs4q0idvs+71V3Syhtp0G/zT7YhRVfTyntCRYIA9vEgyCJI -QvbvKqXTrVIARhpKNUAHs8upeML4CgvWs2o37IinF185xjVwLjmR2nXuZHmmLV4v -yyqNHIbmakjj4KiTSTilPs/iF7/MtHmm+r85etkWA3VhjHst47Wr+scDd1mEkQq6 -rJbbwnXZThsX/FoE3e7knRF8/cfFTfbYmAK2ENJPyMAvgdQU2gTzENsG8g825ziY -J9bCo6tbek33RNzCHrAQsU+MrynfeMdy/s3Z2OsYJokJ/SV84r4XwUoy9UlYPvmi -hWULm1mgo7s86pupnqAds0/YHrw43I9yZXNc4AfPQuQCFFmzmyyv0ZvhuctT0mp7 -mKv8AT7UsbjwOL5b7gE= -=i6TV ------END PGP SIGNATURE----- diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index da6d245..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,3 +0,0 @@ -Content-Type: application/pgp-signature; name="signature.asc" -Content-Description: This is a digitally signed message part -Content-Transfer-Encoding: 7bit diff --git a/a/content_digest b/N1/content_digest index 30d1694..b7b9246 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,73 +1,62 @@ "ref\020171003065540.11722-1-joel@jms.id.au\0" "ref\020171003065540.11722-3-joel@jms.id.au\0" - "From\0Andrew Jeffery <andrew@aj.id.au>\0" - "Subject\0Re: [PATCH v4 2/5] clk: aspeed: Register core clocks\0" + "From\0andrew@aj.id.au (Andrew Jeffery)\0" + "Subject\0[PATCH v4 2/5] clk: aspeed: Register core clocks\0" "Date\0Thu, 05 Oct 2017 17:30:00 +1030\0" - "To\0Joel Stanley <joel@jms.id.au>" - Lee Jones <lee.jones@linaro.org> - Michael Turquette <mturquette@baylibre.com> - " Stephen Boyd <sboyd@codeaurora.org>\0" - "Cc\0linux-kernel@vger.kernel.org" - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - Benjamin Herrenschmidt <benh@kernel.crashing.org> - Jeremy Kerr <jk@ozlabs.org> - Rick Altherr <raltherr@google.com> - Ryan Chen <ryan_chen@aspeedtech.com> - " Arnd Bergmann <arnd@arndb.de>\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "On Tue, 2017-10-03 at 17:25 +1030, Joel Stanley wrote:\n" "> This registers the core clocks; those which are required to calculate\n" "> the rate of the timer peripheral so the system can load a clocksource\n" "> driver.\n" - ">\302\240\n" + ">?\n" "> Signed-off-by: Joel Stanley <joel@jms.id.au>\n" - ">\302\240\n" + ">?\n" "> ---\n" "> v4:\n" - "> \302\240 - Add defines to document the BIT() macros\n" + "> ? - Add defines to document the BIT() macros\n" "> v3:\n" - "> \302\240 - Fix ast2400 ahb calculation\n" - "> \302\240 - Remove incorrect 'this is wrong' comment\n" - "> \302\240 - Separate out clkin calc to be per platform\n" - "> \302\240 - Support 48MHz clkin on ast2400\n" + "> ? - Fix ast2400 ahb calculation\n" + "> ? - Remove incorrect 'this is wrong' comment\n" + "> ? - Separate out clkin calc to be per platform\n" + "> ? - Support 48MHz clkin on ast2400\n" "> ---\n" - "> \302\240drivers/clk/clk-aspeed.c | 177 +++++++++++++++++++++++++++++++++++++++++++++++\n" - "> \302\2401 file changed, 177 insertions(+)\n" - ">\302\240\n" + "> ?drivers/clk/clk-aspeed.c | 177 +++++++++++++++++++++++++++++++++++++++++++++++\n" + "> ?1 file changed, 177 insertions(+)\n" + ">?\n" "> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c\n" "> index a45eb351bb05..d39cf51a5114 100644\n" "> --- a/drivers/clk/clk-aspeed.c\n" "> +++ b/drivers/clk/clk-aspeed.c\n" "> @@ -20,7 +20,23 @@\n" - "> \302\240\n" - "> \302\240#include <dt-bindings/clock/aspeed-clock.h>\n" - "> \302\240\n" + "> ?\n" + "> ?#include <dt-bindings/clock/aspeed-clock.h>\n" + "> ?\n" "> +#define ASPEED_RESET_CTRL\t0x04\n" "> +#define ASPEED_CLK_SELECTION\t0x08\n" "> +#define ASPEED_CLK_STOP_CTRL\t0x0c\n" "> +#define ASPEED_MPLL_PARAM\t0x20\n" "> +#define ASPEED_HPLL_PARAM\t0x24\n" - "> +#define\302\240\302\240AST2500_HPLL_BYPASS_EN\tBIT(20)\n" - "> +#define\302\240\302\240AST2400_HPLL_STRAPPED\tBIT(18)\n" - "> +#define\302\240\302\240AST2400_HPLL_BYPASS_EN\tBIT(17)\n" + "> +#define??AST2500_HPLL_BYPASS_EN\tBIT(20)\n" + "> +#define??AST2400_HPLL_STRAPPED\tBIT(18)\n" + "> +#define??AST2400_HPLL_BYPASS_EN\tBIT(17)\n" "> +#define ASPEED_MISC_CTRL\t0x2c\n" - "> +#define\302\240\302\240UART_DIV13_EN\t\tBIT(12)\n" - "> \302\240#define ASPEED_STRAP\t\t0x70\n" - "> +#define\302\240\302\240CLKIN_25MHZ_EN\t\tBIT(23)\n" - "> +#define\302\240\302\240AST2400_CLK_SOURCE_SEL\tBIT(18)\n" + "> +#define??UART_DIV13_EN\t\tBIT(12)\n" + "> ?#define ASPEED_STRAP\t\t0x70\n" + "> +#define??CLKIN_25MHZ_EN\t\tBIT(23)\n" + "> +#define??AST2400_CLK_SOURCE_SEL\tBIT(18)\n" "> +#define ASPEED_CLK_SELECTION_2\t0xd8\n" "> +\n" "> +/* Globally visible clocks */\n" "> +static DEFINE_SPINLOCK(aspeed_clk_lock);\n" - "> \302\240\n" - "> \302\240/* Keeps track of all clocks */\n" - "> \302\240static struct clk_hw_onecell_data *aspeed_clk_data;\n" + "> ?\n" + "> ?/* Keeps track of all clocks */\n" + "> ?static struct clk_hw_onecell_data *aspeed_clk_data;\n" "> @@ -98,6 +114,160 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = {\n" - "> \302\240\t[ASPEED_CLK_GATE_LHCCLK] =\t{ 28, -1, \"lhclk-gate\",\t\t\"lhclk\", 0 }, /* LPC master/LPC+ */\n" - "> \302\240};\n" - "> \302\240\n" + "> ?\t[ASPEED_CLK_GATE_LHCCLK] =\t{ 28, -1, \"lhclk-gate\",\t\t\"lhclk\", 0 }, /* LPC master/LPC+ */\n" + "> ?};\n" + "> ?\n" "> +static const struct clk_div_table ast2400_div_table[] = {\n" "> +\t{ 0x0, 2 },\n" "> +\t{ 0x1, 4 },\n" @@ -139,9 +128,9 @@ "> +\tu32 val, freq, div;\n" "> +\n" "> +\t/*\n" - "> +\t\302\240* CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by\n" - "> +\t\302\240* strapping\n" - "> +\t\302\240*/\n" + "> +\t?* CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by\n" + "> +\t?* strapping\n" + "> +\t?*/\n" "> +\tregmap_read(map, ASPEED_STRAP, &val);\n" "> +\tif (val & CLKIN_25MHZ_EN)\n" "> +\t\tfreq = 25000000;\n" @@ -153,20 +142,20 @@ "> +\tpr_debug(\"clkin @%u MHz\\n\", freq / 1000000);\n" "> +\n" "> +\t/*\n" - "> +\t\302\240* High-speed PLL clock derived from the crystal. This the CPU clock,\n" - "> +\t\302\240* and we assume that it is enabled\n" - "> +\t\302\240*/\n" + "> +\t?* High-speed PLL clock derived from the crystal. This the CPU clock,\n" + "> +\t?* and we assume that it is enabled\n" + "> +\t?*/\n" "> +\tregmap_read(map, ASPEED_HPLL_PARAM, &val);\n" "> +\tWARN(val & AST2400_HPLL_STRAPPED, \"hpll is strapped not configured\");\n" "> +\taspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll(\"hpll\", val);\n" "> +\n" "> +\t/*\n" - "> +\t\302\240* Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)\n" - "> +\t\302\240*\302\240\302\240\302\24000: Select CPU:AHB = 1:1\n" - "> +\t\302\240*\302\240\302\240\302\24001: Select CPU:AHB = 2:1\n" - "> +\t\302\240*\302\240\302\240\302\24010: Select CPU:AHB = 4:1\n" - "> +\t\302\240*\302\240\302\240\302\24011: Select CPU:AHB = 3:1\n" - "> +\t\302\240*/\n" + "> +\t?* Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)\n" + "> +\t?*???00: Select CPU:AHB = 1:1\n" + "> +\t?*???01: Select CPU:AHB = 2:1\n" + "> +\t?*???10: Select CPU:AHB = 4:1\n" + "> +\t?*???11: Select CPU:AHB = 3:1\n" + "> +\t?*/\n" "> +\tregmap_read(map, ASPEED_STRAP, &val);\n" "> +\tval = (val >> 10) & 0x3;\n" "> +\tdiv = val + 1;\n" @@ -200,9 +189,9 @@ "> +\tpr_debug(\"clkin @%u MHz\\n\", freq / 1000000);\n" "> +\n" "> +\t/*\n" - "> +\t\302\240* High-speed PLL clock derived from the crystal. This the CPU clock,\n" - "> +\t\302\240* and we assume that it is enabled\n" - "> +\t\302\240*/\n" + "> +\t?* High-speed PLL clock derived from the crystal. This the CPU clock,\n" + "> +\t?* and we assume that it is enabled\n" + "> +\t?*/\n" "> +\tregmap_read(map, ASPEED_HPLL_PARAM, &val);\n" "> +\taspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll(\"hpll\", val);\n" "> +\n" @@ -222,13 +211,13 @@ "> +\taspeed_clk_data->hws[ASPEED_CLK_APB] = hw;\n" "> +};\n" "> +\n" - "> \302\240static void __init aspeed_cc_init(struct device_node *np)\n" - "> \302\240{\n" - "> \302\240\tstruct regmap *map;\n" + "> ?static void __init aspeed_cc_init(struct device_node *np)\n" + "> ?{\n" + "> ?\tstruct regmap *map;\n" "> @@ -139,6 +309,13 @@ static void __init aspeed_cc_init(struct device_node *np)\n" - "> \302\240\t\treturn;\n" - "> \302\240\t}\n" - "> \302\240\n" + "> ?\t\treturn;\n" + "> ?\t}\n" + "> ?\n" "> +\tif (of_device_is_compatible(np, \"aspeed,ast2400-scu\"))\n" "> +\t\taspeed_ast2400_cc(map);\n" "> +\telse if (of_device_is_compatible(np, \"aspeed,ast2500-scu\"))\n" @@ -241,28 +230,15 @@ "\n" "Reviewed-by: Andrew Jeffery <andrew@aj.id.au>\n" "\n" - "> \302\240\taspeed_clk_data->num = ASPEED_NUM_CLKS;\n" - "> \302\240\tret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);\n" - "> \302\240\tif (ret)" - "\01:2\0" - "fn\0signature.asc\0" - "d\0This is a digitally signed message part\0" - "b\0" - "-----BEGIN PGP SIGNATURE-----\n" - "\n" - "iQIbBAABCgAGBQJZ1dhwAAoJEJ0dnzgO5LT5TZcP8wRMANyZ8jm8gWhvCKAoGq9F\n" - "7PIonE0X7X6bAl4V0rBKQ6DzlueR1Qvw47l3FRGUKClO99czY0PxK2M0sMxE/YTZ\n" - "drsz6GfukR51TP6Mfa23+AvtsjoDL/uRDX+BZOR//xO2rCIfDf8iqBdZwAPzxxWN\n" - "pL5ThzNMhFdgwb/GWyF7aUMulcqI4UJf94MJVm5XHS43Eggdn7IPxTCYNrvTlMF2\n" - "nppRPDu3i0Lbx1paxukhG7Ryb9Gzo/7W8gwD6zmWe4Ohi/hzsH7k0xcXyaqZEhFk\n" - "HY3DuobIAU/gmxXHHHs4q0idvs+71V3Syhtp0G/zT7YhRVfTyntCRYIA9vEgyCJI\n" - "QvbvKqXTrVIARhpKNUAHs8upeML4CgvWs2o37IinF185xjVwLjmR2nXuZHmmLV4v\n" - "yyqNHIbmakjj4KiTSTilPs/iF7/MtHmm+r85etkWA3VhjHst47Wr+scDd1mEkQq6\n" - "rJbbwnXZThsX/FoE3e7knRF8/cfFTfbYmAK2ENJPyMAvgdQU2gTzENsG8g825ziY\n" - "J9bCo6tbek33RNzCHrAQsU+MrynfeMdy/s3Z2OsYJokJ/SV84r4XwUoy9UlYPvmi\n" - "hWULm1mgo7s86pupnqAds0/YHrw43I9yZXNc4AfPQuQCFFmzmyyv0ZvhuctT0mp7\n" - "mKv8AT7UsbjwOL5b7gE=\n" - "=i6TV\n" - "-----END PGP SIGNATURE-----\n" + "> ?\taspeed_clk_data->num = ASPEED_NUM_CLKS;\n" + "> ?\tret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);\n" + "> ?\tif (ret)\n" + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: signature.asc\n" + "Type: application/pgp-signature\n" + "Size: 801 bytes\n" + "Desc: This is a digitally signed message part\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20171005/300aa628/attachment.sig> -b4205a784579bd0053c996ab413c597c8b0087eb9e2935e3bf330027644e17dd +5712a336a12091ab614a1ebece9fe9cf8e1e68d562a2d947539bba922a571cf7
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.