diff for duplicates of <1507656569.3555.41.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index d0a8f3a..9869e20 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ Hi Vineet, -On Tue, 2017-10-10@10:09 -0700, Vineet Gupta wrote: +On Tue, 2017-10-10 at 10:09 -0700, Vineet Gupta wrote: > On 10/10/2017 09:11 AM, Eugeniy Paltsev wrote: > > > > Increase SDIO CIU frequency from 12500000Hz to 50000000Hz by @@ -8,11 +8,11 @@ On Tue, 2017-10-10@10:09 -0700, Vineet Gupta wrote: > > minimum possible value of the divisor (div-by-2) in HSDK platform > > code. > -> Please describe the problem first not the solution. That some SD cards don't work? +> Please describe the problem first not the solution. That some SD cards don't work > blah blah .... > You could add me as reported-by - just for completeness ! > -> While I will test it to see if it cures my issue, I'll need Alexey to sign off /? +> While I will test it to see if it cures my issue, I'll need Alexey to sign off / > ack as well ! Sure once you update us with your findings and we know it helps you @@ -26,63 +26,63 @@ there will be a "normal" patch which I'll ack. > > > > > -> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> > > --- > > NOTE: This patch can possibly fix last issue with SD card initialization > > fault. > > -> > ? arch/arc/boot/dts/hsdk.dts????| 11 ++++++----- -> > ? arch/arc/plat-hsdk/platform.c |??7 +++++++ -> > ? 2 files changed, 13 insertions(+), 5 deletions(-) +> > arch/arc/boot/dts/hsdk.dts | 11 ++++++----- +> > arch/arc/plat-hsdk/platform.c | 7 +++++++ +> > 2 files changed, 13 insertions(+), 5 deletions(-) > > > > diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts > > index 8adde1b..8f627c2 100644 > > --- a/arch/arc/boot/dts/hsdk.dts > > +++ b/arch/arc/boot/dts/hsdk.dts > > @@ -137,14 +137,15 @@ -> > ?? /* -> > ?? ?* DW sdio controller has external ciu clock divider -> > ?? ?* controlled via register in SDIO IP. Due to its -> > - ?* unexpected default value (it should devide by 1 -> > - ?* but it devides by 8) SDIO IP uses wrong clock and -> > + ?* unexpected default value (it should divide by 1 -> > + ?* but it divides by 8) SDIO IP uses wrong clock and -> > ?? ?* works unstable (see STAR 9001204800) -> > + ?* We switched to the minimum possible value of the -> > + ?* divisor (div-by-2) in HSDK platform code. -> > ?? ?* So add temporary fix and change clock frequency -> > - ?* from 100000000 to 12500000 Hz until we fix dw sdio -> > - ?* driver itself. -> > + ?* to 50000000 Hz until we fix dw sdio driver itself. -> > ?? ?*/ +> > /* +> > * DW sdio controller has external ciu clock divider +> > * controlled via register in SDIO IP. Due to its +> > - * unexpected default value (it should devide by 1 +> > - * but it devides by 8) SDIO IP uses wrong clock and +> > + * unexpected default value (it should divide by 1 +> > + * but it divides by 8) SDIO IP uses wrong clock and +> > * works unstable (see STAR 9001204800) +> > + * We switched to the minimum possible value of the +> > + * divisor (div-by-2) in HSDK platform code. +> > * So add temporary fix and change clock frequency +> > - * from 100000000 to 12500000 Hz until we fix dw sdio +> > - * driver itself. +> > + * to 50000000 Hz until we fix dw sdio driver itself. +> > */ > > - clock-frequency = <12500000>; > > + clock-frequency = <50000000>; -> > ?? #clock-cells = <0>; -> > ?? }; -> > ?? +> > #clock-cells = <0>; +> > }; +> > > > diff --git a/arch/arc/plat-hsdk/platform.c b/arch/arc/plat-hsdk/platform.c > > index 744e62e..f0cdb13 100644 > > --- a/arch/arc/plat-hsdk/platform.c > > +++ b/arch/arc/plat-hsdk/platform.c > > @@ -74,6 +74,10 @@ static void __init hsdk_set_cpu_freq_1ghz(void) -> > ?? pr_err("Failed to setup CPU frequency to 1GHz!"); -> > ? } -> > ?? +> > pr_err("Failed to setup CPU frequency to 1GHz!"); +> > } +> > > > +#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000) > > +#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108) > > +#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30) > > + -> > ? static void __init hsdk_init_early(void) -> > ? { -> > ?? /* +> > static void __init hsdk_init_early(void) +> > { +> > /* > > @@ -89,6 +93,9 @@ static void __init hsdk_init_early(void) -> > ?? /* Really apply settings made above */ -> > ?? writel(1, (void __iomem *) CREG_PAE_UPDATE); -> > ?? +> > /* Really apply settings made above */ +> > writel(1, (void __iomem *) CREG_PAE_UPDATE); +> > > > + /* Switch SDIO external ciu clock divider from div-by-8 to div-by-2 */ > > + iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT); > > + -> > ?? /* -> > ?? ?* Setup CPU frequency to 1GHz. -> > ?? ?* TODO: remove it after smart hsdk pll driver will be introduced. +> > /* +> > * Setup CPU frequency to 1GHz. +> > * TODO: remove it after smart hsdk pll driver will be introduced. > diff --git a/a/content_digest b/N1/content_digest index e8fbef4..b2ef967 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,14 +1,17 @@ "ref\020171010161152.5604-1-Eugeniy.Paltsev@synopsys.com\0" "ref\0a1a4863d-c9e4-5dd0-b4e0-8c5d7e7b32e3@synopsys.com\0" - "From\0Alexey.Brodkin@synopsys.com (Alexey Brodkin)\0" - "Subject\0[RFC] ARC: [plat-hsdk]: Increase SDIO CIU frequency to 50000000Hz\0" + "From\0Alexey Brodkin <Alexey.Brodkin@synopsys.com>\0" + "Subject\0Re: [RFC] ARC: [plat-hsdk]: Increase SDIO CIU frequency to 50000000Hz\0" "Date\0Tue, 10 Oct 2017 17:29:29 +0000\0" - "To\0linux-snps-arc@lists.infradead.org\0" + "To\0Vineet Gupta <Vineet.Gupta1@synopsys.com>\0" + "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" + Eugeniy.Paltsev@synopsys.com <Eugeniy.Paltsev@synopsys.com> + " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" "\00:1\0" "b\0" "Hi Vineet,\n" "\n" - "On Tue, 2017-10-10@10:09 -0700, Vineet Gupta wrote:\n" + "On Tue, 2017-10-10 at 10:09 -0700, Vineet Gupta wrote:\n" "> On 10/10/2017 09:11 AM, Eugeniy Paltsev wrote:\n" "> > \n" "> > Increase SDIO CIU frequency from 12500000Hz to 50000000Hz by\n" @@ -16,11 +19,11 @@ "> > minimum possible value of the divisor (div-by-2) in HSDK platform\n" "> > code.\n" "> \n" - "> Please describe the problem first not the solution. That some SD cards don't work?\n" + "> Please describe the problem first not the solution. That some SD cards don't work\302\240\n" "> blah blah ....\n" "> You could add me as reported-by - just for completeness !\n" "> \n" - "> While I will test it to see if it cures my issue, I'll need Alexey to sign off /?\n" + "> While I will test it to see if it cures my issue, I'll need Alexey to sign off /\302\240\n" "> ack as well !\n" "\n" "Sure once you update us with your findings and we know it helps you\n" @@ -34,65 +37,65 @@ "> \n" "> > \n" "> > \n" - "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" "> > ---\n" "> > NOTE: This patch can possibly fix last issue with SD card initialization\n" "> > fault.\n" "> > \n" - "> > ? arch/arc/boot/dts/hsdk.dts????| 11 ++++++-----\n" - "> > ? arch/arc/plat-hsdk/platform.c |??7 +++++++\n" - "> > ? 2 files changed, 13 insertions(+), 5 deletions(-)\n" + "> > \302\240 arch/arc/boot/dts/hsdk.dts\302\240\302\240\302\240\302\240| 11 ++++++-----\n" + "> > \302\240 arch/arc/plat-hsdk/platform.c |\302\240\302\2407 +++++++\n" + "> > \302\240 2 files changed, 13 insertions(+), 5 deletions(-)\n" "> > \n" "> > diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts\n" "> > index 8adde1b..8f627c2 100644\n" "> > --- a/arch/arc/boot/dts/hsdk.dts\n" "> > +++ b/arch/arc/boot/dts/hsdk.dts\n" "> > @@ -137,14 +137,15 @@\n" - "> > ??\t\t\t/*\n" - "> > ??\t\t\t?* DW sdio controller has external ciu clock divider\n" - "> > ??\t\t\t?* controlled via register in SDIO IP. Due to its\n" - "> > -\t\t\t?* unexpected default value (it should devide by 1\n" - "> > -\t\t\t?* but it devides by 8) SDIO IP uses wrong clock and\n" - "> > +\t\t\t?* unexpected default value (it should divide by 1\n" - "> > +\t\t\t?* but it divides by 8) SDIO IP uses wrong clock and\n" - "> > ??\t\t\t?* works unstable (see STAR 9001204800)\n" - "> > +\t\t\t?* We switched to the minimum possible value of the\n" - "> > +\t\t\t?* divisor (div-by-2) in HSDK platform code.\n" - "> > ??\t\t\t?* So add temporary fix and change clock frequency\n" - "> > -\t\t\t?* from 100000000 to 12500000 Hz until we fix dw sdio\n" - "> > -\t\t\t?* driver itself.\n" - "> > +\t\t\t?* to 50000000 Hz until we fix dw sdio driver itself.\n" - "> > ??\t\t\t?*/\n" + "> > \302\240\302\240\t\t\t/*\n" + "> > \302\240\302\240\t\t\t\302\240* DW sdio controller has external ciu clock divider\n" + "> > \302\240\302\240\t\t\t\302\240* controlled via register in SDIO IP. Due to its\n" + "> > -\t\t\t\302\240* unexpected default value (it should devide by 1\n" + "> > -\t\t\t\302\240* but it devides by 8) SDIO IP uses wrong clock and\n" + "> > +\t\t\t\302\240* unexpected default value (it should divide by 1\n" + "> > +\t\t\t\302\240* but it divides by 8) SDIO IP uses wrong clock and\n" + "> > \302\240\302\240\t\t\t\302\240* works unstable (see STAR 9001204800)\n" + "> > +\t\t\t\302\240* We switched to the minimum possible value of the\n" + "> > +\t\t\t\302\240* divisor (div-by-2) in HSDK platform code.\n" + "> > \302\240\302\240\t\t\t\302\240* So add temporary fix and change clock frequency\n" + "> > -\t\t\t\302\240* from 100000000 to 12500000 Hz until we fix dw sdio\n" + "> > -\t\t\t\302\240* driver itself.\n" + "> > +\t\t\t\302\240* to 50000000 Hz until we fix dw sdio driver itself.\n" + "> > \302\240\302\240\t\t\t\302\240*/\n" "> > -\t\t\tclock-frequency = <12500000>;\n" "> > +\t\t\tclock-frequency = <50000000>;\n" - "> > ??\t\t\t#clock-cells = <0>;\n" - "> > ??\t\t};\n" - "> > ??\n" + "> > \302\240\302\240\t\t\t#clock-cells = <0>;\n" + "> > \302\240\302\240\t\t};\n" + "> > \302\240\302\240\n" "> > diff --git a/arch/arc/plat-hsdk/platform.c b/arch/arc/plat-hsdk/platform.c\n" "> > index 744e62e..f0cdb13 100644\n" "> > --- a/arch/arc/plat-hsdk/platform.c\n" "> > +++ b/arch/arc/plat-hsdk/platform.c\n" "> > @@ -74,6 +74,10 @@ static void __init hsdk_set_cpu_freq_1ghz(void)\n" - "> > ??\t\tpr_err(\"Failed to setup CPU frequency to 1GHz!\");\n" - "> > ? }\n" - "> > ??\n" + "> > \302\240\302\240\t\tpr_err(\"Failed to setup CPU frequency to 1GHz!\");\n" + "> > \302\240 }\n" + "> > \302\240\302\240\n" "> > +#define SDIO_BASE\t\t(ARC_PERIPHERAL_BASE + 0xA000)\n" "> > +#define SDIO_UHS_REG_EXT\t(SDIO_BASE + 0x108)\n" "> > +#define SDIO_UHS_REG_EXT_DIV_2\t(2 << 30)\n" "> > +\n" - "> > ? static void __init hsdk_init_early(void)\n" - "> > ? {\n" - "> > ??\t/*\n" + "> > \302\240 static void __init hsdk_init_early(void)\n" + "> > \302\240 {\n" + "> > \302\240\302\240\t/*\n" "> > @@ -89,6 +93,9 @@ static void __init hsdk_init_early(void)\n" - "> > ??\t/* Really apply settings made above */\n" - "> > ??\twritel(1, (void __iomem *) CREG_PAE_UPDATE);\n" - "> > ??\n" + "> > \302\240\302\240\t/* Really apply settings made above */\n" + "> > \302\240\302\240\twritel(1, (void __iomem *) CREG_PAE_UPDATE);\n" + "> > \302\240\302\240\n" "> > +\t/* Switch SDIO external ciu clock divider from div-by-8 to div-by-2 */\n" "> > +\tiowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);\n" "> > +\n" - "> > ??\t/*\n" - "> > ??\t?* Setup CPU frequency to 1GHz.\n" - "> > ??\t?* TODO: remove it after smart hsdk pll driver will be introduced.\n" + "> > \302\240\302\240\t/*\n" + "> > \302\240\302\240\t\302\240* Setup CPU frequency to 1GHz.\n" + "> > \302\240\302\240\t\302\240* TODO: remove it after smart hsdk pll driver will be introduced.\n" > -0568cac3a885918fff0f5c6000657dbce843ff13744a1567963fbb0711458a05 +9ba460a43c1e54627691120b494267682942083c30238f5c14b6969540c4ac9f
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