From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:42388 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751378AbdJSNPQ (ORCPT ); Thu, 19 Oct 2017 09:15:16 -0400 Subject: Patch "powerpc/perf: Add restrictions to PMC5 in power9 DD1" has been added to the 4.9-stable tree To: maddy@linux.vnet.ibm.com, alexander.levin@verizon.com, gregkh@linuxfoundation.org, mpe@ellerman.id.au Cc: , From: Date: Thu, 19 Oct 2017 15:14:34 +0200 Message-ID: <1508418874188188@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled powerpc/perf: Add restrictions to PMC5 in power9 DD1 to the 4.9-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: powerpc-perf-add-restrictions-to-pmc5-in-power9-dd1.patch and it can be found in the queue-4.9 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From foo@baz Thu Oct 19 15:04:02 CEST 2017 From: Madhavan Srinivasan Date: Sun, 12 Feb 2017 22:33:15 +0530 Subject: powerpc/perf: Add restrictions to PMC5 in power9 DD1 From: Madhavan Srinivasan [ Upstream commit 8d911904f3ce412b20874a9c95f82009dcbb007c ] PMC5 on POWER9 DD1 may not provide right counts in all sampling scenarios, hence use PM_INST_DISP event instead in PMC2 or PMC3 in preference. Signed-off-by: Madhavan Srinivasan Signed-off-by: Michael Ellerman Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/perf/isa207-common.h | 4 ++++ arch/powerpc/perf/power9-pmu.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -201,6 +201,10 @@ CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \ CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL +/* + * Lets restrict use of PMC5 for instruction counting. + */ +#define P9_DD1_TEST_ADDER (ISA207_TEST_ADDER | CNST_PMC_VAL(5)) /* Bits in MMCR1 for PowerISA v2.07 */ #define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1))) --- a/arch/powerpc/perf/power9-pmu.c +++ b/arch/powerpc/perf/power9-pmu.c @@ -295,7 +295,7 @@ static struct power_pmu power9_pmu = { .name = "POWER9", .n_counter = MAX_PMU_COUNTERS, .add_fields = ISA207_ADD_FIELDS, - .test_adder = ISA207_TEST_ADDER, + .test_adder = P9_DD1_TEST_ADDER, .compute_mmcr = isa207_compute_mmcr, .config_bhrb = power9_config_bhrb, .bhrb_filter_map = power9_bhrb_filter_map, Patches currently in stable-queue which might be from maddy@linux.vnet.ibm.com are queue-4.9/powerpc-perf-add-restrictions-to-pmc5-in-power9-dd1.patch