From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity
Date: Tue, 31 Oct 2017 13:11:27 +0000 [thread overview]
Message-ID: <1509455489-14101-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org>
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Fixed incorrect frame size mask, validated maximum frame
size in spi_write and removed dead code.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1508898544-10307-1-git-send-email-sundeep.lkml@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/ssi/mss-spi.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
index 5a8e308..d60daba 100644
--- a/hw/ssi/mss-spi.c
+++ b/hw/ssi/mss-spi.c
@@ -76,9 +76,10 @@
#define C_BIGFIFO (1 << 29)
#define C_RESET (1 << 31)
-#define FRAMESZ_MASK 0x1F
+#define FRAMESZ_MASK 0x3F
#define FMCOUNT_MASK 0x00FFFF00
#define FMCOUNT_SHIFT 8
+#define FRAMESZ_MAX 32
static void txfifo_reset(MSSSpiState *s)
{
@@ -104,10 +105,8 @@ static void set_fifodepth(MSSSpiState *s)
s->fifo_depth = 32;
} else if (size <= 16) {
s->fifo_depth = 16;
- } else if (size <= 32) {
- s->fifo_depth = 8;
} else {
- s->fifo_depth = 4;
+ s->fifo_depth = 8;
}
}
@@ -301,6 +300,17 @@ static void spi_write(void *opaque, hwaddr addr,
if (s->enabled) {
break;
}
+ /*
+ * [31:6] bits are reserved bits and for future use.
+ * [5:0] are for frame size. Only [5:0] bits are validated
+ * during write, [31:6] bits are untouched.
+ */
+ if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %u provided."
+ "Maximum frame size is %u\n",
+ __func__, value & FRAMESZ_MASK, FRAMESZ_MAX);
+ break;
+ }
s->regs[R_SPI_DFSIZE] = value;
break;
--
2.7.4
next prev parent reply other threads:[~2017-10-31 13:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-31 13:11 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs Peter Maydell
2017-10-31 13:11 ` Peter Maydell [this message]
2017-10-31 13:11 ` [Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset Peter Maydell
2017-10-31 13:11 ` [Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking Peter Maydell
2017-10-31 15:33 ` [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
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