diff for duplicates of <1509958288489.45871@axon.tv> diff --git a/a/1.txt b/N1/1.txt index 4e1b93a..375f0af 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,13 +1,13 @@ Hi, according to Xilinx, from a computer host it happens in a second, while for us in the Zynq (ARM) takes way more than that as explained before. And indeed the programming is done via config accesses, and can't happen otherwise as this is the way Xilinx created its FPGA IP (Intellectual Property) cores. Still if I do a baremetal test (so no Linux) and write from the ARMs to the FPGA via those registers, it takes only 17 cycles instead of the Linux implementation which takes 250 cycles. Ruben Guerra Marin -ruben.guerra.marin@axon.tv +ruben.guerra.marin at axon.tv ________________________________________ From: Bjorn Helgaas <helgaas@kernel.org> Sent: Friday, November 3, 2017 2:54 PM To: Michal Simek -Cc: Ruben Guerra Marin; bhelgaas@google.com; soren.brinkmann@xilinx.com; bharat.kumar.gogada@xilinx.com; linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org +Cc: Ruben Guerra Marin; bhelgaas at google.com; soren.brinkmann at xilinx.com; bharat.kumar.gogada at xilinx.com; linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org Subject: Re: Performance issues writing to PCIe in a Zynq On Fri, Nov 03, 2017 at 09:12:04AM +0100, Michal Simek wrote: diff --git a/a/content_digest b/N1/content_digest index 9ced271..af6f580 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,28 +1,22 @@ "ref\01509636637116.27702@axon.tv\0" "ref\0eca01e58-3da1-d5c4-00f7-71dd6a926870@xilinx.com\0" "ref\020171103135457.GA8457@bhelgaas-glaptop.roam.corp.google.com\0" - "From\0Ruben Guerra Marin <ruben.guerra.marin@axon.tv>\0" - "Subject\0Re: Performance issues writing to PCIe in a Zynq\0" + "From\0ruben.guerra.marin@axon.tv (Ruben Guerra Marin)\0" + "Subject\0Performance issues writing to PCIe in a Zynq\0" "Date\0Mon, 6 Nov 2017 08:51:28 +0000\0" - "To\0Bjorn Helgaas <helgaas@kernel.org>" - " Michal Simek <michal.simek@xilinx.com>\0" - "Cc\0bhelgaas@google.com <bhelgaas@google.com>" - soren.brinkmann@xilinx.com <soren.brinkmann@xilinx.com> - bharat.kumar.gogada@xilinx.com <bharat.kumar.gogada@xilinx.com> - linux-pci@vger.kernel.org <linux-pci@vger.kernel.org> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi, according to Xilinx, from a computer host it happens in a second, while for us in the Zynq (ARM) takes way more than that as explained before. And indeed the programming is done via config accesses, and can't happen otherwise as this is the way Xilinx created its FPGA IP (Intellectual Property) cores. Still if I do a baremetal test (so no Linux) and write from the ARMs to the FPGA via those registers, it takes only 17 cycles instead of the Linux implementation which takes 250 cycles. \n" "\n" "Ruben Guerra Marin\n" - "ruben.guerra.marin@axon.tv\n" + "ruben.guerra.marin at axon.tv\n" "\n" "________________________________________\n" "From: Bjorn Helgaas <helgaas@kernel.org>\n" "Sent: Friday, November 3, 2017 2:54 PM\n" "To: Michal Simek\n" - "Cc: Ruben Guerra Marin; bhelgaas@google.com; soren.brinkmann@xilinx.com; bharat.kumar.gogada@xilinx.com; linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org\n" + "Cc: Ruben Guerra Marin; bhelgaas at google.com; soren.brinkmann at xilinx.com; bharat.kumar.gogada at xilinx.com; linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org\n" "Subject: Re: Performance issues writing to PCIe in a Zynq\n" "\n" "On Fri, Nov 03, 2017 at 09:12:04AM +0100, Michal Simek wrote:\n" @@ -77,4 +71,4 @@ "\n" Bjorn -1eb25115ed508b38464ed1997a61c223dc5bc30e014bac796f059590994f878c +c9ded81e6ccd068a90563192608d24a22fc1094ab93754b5795b4f55211e4c80
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