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From: <gregkh@linuxfoundation.org>
To: gary.hook@amd.com, alexander.levin@verizon.com,
	gregkh@linuxfoundation.org, herbert@gondor.apana.org.au
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "crypto: ccp - Set the AES size field for all modes" has been added to the 4.9-stable tree
Date: Mon, 06 Nov 2017 10:11:32 +0100	[thread overview]
Message-ID: <1509959492320@kroah.com> (raw)


This is a note to let you know that I've just added the patch titled

    crypto: ccp - Set the AES size field for all modes

to the 4.9-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     crypto-ccp-set-the-aes-size-field-for-all-modes.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.


>From foo@baz Mon Nov  6 10:07:35 CET 2017
From: Gary R Hook <gary.hook@amd.com>
Date: Sat, 7 Oct 2017 22:36:46 +0000
Subject: crypto: ccp - Set the AES size field for all modes

From: Gary R Hook <gary.hook@amd.com>


[ Upstream commit f7cc02b3c3a33a10dd5bb9e5dfd22e47e09503a2 ]

Ensure that the size field is correctly populated for
all AES modes.

Signed-off-by: Gary R Hook <gary.hook@amd.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/crypto/ccp/ccp-dev-v5.c |    3 +--
 drivers/crypto/ccp/ccp-dev.h    |    1 +
 drivers/crypto/ccp/ccp-ops.c    |    8 ++++++++
 3 files changed, 10 insertions(+), 2 deletions(-)

--- a/drivers/crypto/ccp/ccp-dev-v5.c
+++ b/drivers/crypto/ccp/ccp-dev-v5.c
@@ -278,8 +278,7 @@ static int ccp5_perform_aes(struct ccp_o
 	CCP_AES_ENCRYPT(&function) = op->u.aes.action;
 	CCP_AES_MODE(&function) = op->u.aes.mode;
 	CCP_AES_TYPE(&function) = op->u.aes.type;
-	if (op->u.aes.mode == CCP_AES_MODE_CFB)
-		CCP_AES_SIZE(&function) = 0x7f;
+	CCP_AES_SIZE(&function) = op->u.aes.size;
 
 	CCP5_CMD_FUNCTION(&desc) = function.raw;
 
--- a/drivers/crypto/ccp/ccp-dev.h
+++ b/drivers/crypto/ccp/ccp-dev.h
@@ -470,6 +470,7 @@ struct ccp_aes_op {
 	enum ccp_aes_type type;
 	enum ccp_aes_mode mode;
 	enum ccp_aes_action action;
+	unsigned int size;
 };
 
 struct ccp_xts_aes_op {
--- a/drivers/crypto/ccp/ccp-ops.c
+++ b/drivers/crypto/ccp/ccp-ops.c
@@ -692,6 +692,14 @@ static int ccp_run_aes_cmd(struct ccp_cm
 			goto e_ctx;
 		}
 	}
+	switch (aes->mode) {
+	case CCP_AES_MODE_CFB: /* CFB128 only */
+	case CCP_AES_MODE_CTR:
+		op.u.aes.size = AES_BLOCK_SIZE * BITS_PER_BYTE - 1;
+		break;
+	default:
+		op.u.aes.size = 0;
+	}
 
 	/* Prepare the input and output data workareas. For in-place
 	 * operations we need to set the dma direction to BIDIRECTIONAL


Patches currently in stable-queue which might be from gary.hook@amd.com are

queue-4.9/crypto-ccp-set-the-aes-size-field-for-all-modes.patch

                 reply	other threads:[~2017-11-06  9:11 UTC|newest]

Thread overview: [no followups] expand[flat|nested]  mbox.gz  Atom feed

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