Patch "clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum" has been added to the 4.9-stable tree

[<gregkh@linuxfoundation.org>]

This is a note to let you know that I've just added the patch titled

    clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum

to the 4.9-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clocksource-drivers-arm_arch_timer-add-dt-binding-for-hisilicon-161010101-erratum.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.


>From foo@baz Mon Nov  6 10:07:35 CET 2017
From: Ding Tianhong <dingtianhong@huawei.com>
Date: Sat, 7 Oct 2017 22:36:51 +0000
Subject: clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum

From: Ding Tianhong <dingtianhong@huawei.com>


[ Upstream commit 729e55225b1f6225ee7a2a358d5141a3264627c4 ]

This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward.  So, describe it
in the device tree.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 Documentation/devicetree/bindings/arm/arch_timer.txt |    6 ++++++
 1 file changed, 6 insertions(+)

--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,12 @@ to deliver its interrupts via SPIs.
   This also affects writes to the tval register, due to the implicit
   counter read.
 
+- hisilicon,erratum-161010101 : A boolean property. Indicates the
+  presence of Hisilicon erratum 161010101, which says that reading the
+  counters is unreliable in some cases, and reads may return a value 32
+  beyond the correct value. This also affects writes to the tval
+  registers, due to the implicit counter read.
+
 ** Optional properties:
 
 - arm,cpu-registers-not-fw-configured : Firmware does not initialize


Patches currently in stable-queue which might be from dingtianhong@huawei.com are

queue-4.9/clocksource-drivers-arm_arch_timer-add-dt-binding-for-hisilicon-161010101-erratum.patch