From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shanker Donthineni Subject: [PATCH v2 0/2] Implement a software workaround for Falkor erratum 1041 Date: Sun, 12 Nov 2017 19:16:40 -0600 Message-ID: <1510535802-2799-1-git-send-email-shankerd@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 5714C49D82 for ; Sun, 12 Nov 2017 20:14:49 -0500 (EST) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OHtp1xa7lG4E for ; Sun, 12 Nov 2017 20:14:48 -0500 (EST) Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 130C049D4B for ; Sun, 12 Nov 2017 20:14:48 -0500 (EST) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Will Deacon , Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: linux-efi@vger.kernel.org, Ard Biesheuvel , Matt Fleming , Catalin Marinas , linux-kernel@vger.kernel.org, kvmarm@lists.cs.columbia.edu List-Id: kvmarm@lists.cs.columbia.edu T24gRmFsa29yIENQVSwgd2XigJl2ZSBkaXNjb3ZlcmVkIGEgaGFyZHdhcmUgaXNzdWUgd2hpY2gg bWlnaHQgbGVhZCB0byBhCmtlcm5lbCBjcmFzaCBvciB0aGUgdW5leHBlY3RlZCBiZWhhdmlvci4g VGhlIEZhbGtvciBjb3JlIG1heSBlcnJhbnRseQphY2Nlc3MgbWVtb3J5IGxvY2F0aW9ucyBvbiBz cGVjdWxhdGl2ZSBpbnN0cnVjdGlvbiBmZXRjaGVzLiBUaGlzIG1heQpoYXBwZW4gd2hlbmV2ZXIg TU1VIHRyYW5zbGF0aW9uIHN0YXRlLCBTQ1RMUl9FTG5bTV0gYml0IGlzIGJlaW5nIGNoYW5nZWQK ZnJvbSBlbmFibGVkIHRvIGRpc2FibGVkIGZvciB0aGUgY3VycmVudGx5IHJ1bm5pbmcgZXhjZXB0 aW9uIGxldmVsLiBUbwpwcmV2ZW50IHRoZSBlcnJhbnQgaGFyZHdhcmUgYmVoYXZpb3IsIHNvZnR3 YXJlIG11c3QgZXhlY3V0ZSBhbiBJU0IKaW1tZWRpYXRlbHkgcHJpb3IgdG8gZXhlY3V0aW5nIHRo ZSBNU1IgdGhhdCBjaGFuZ2VzIFNDVExSX0VMbltNXSBmcm9tIGEKdmFsdWUgb2YgMSB0byAwLiBU byBzaW1wbGlmeSB0aGUgY29tcGxleGl0eSBvZiBhIHdvcmthcm91bmQsIHRoaXMgcGF0Y2gKc2Vy aWVzIGlzc3VlcyBhbiBJU0Igd2hlbmV2ZXIgU0NUTFJfRUxuW01dIGlzIGNoYW5nZWQgdG8gMCB0 byBmaXggdGhlCkZhbGtvciBlcnJhdHVtIDEwNDEuCgpQYXRjaDIgZnJvbSBWMSBzZXJpZXMgZ290 IGRyb3BwZWQgdG8gYWNjb21tb2RhdGUgcmV2aWV3IGNvbW1lbnRzLiBBcHBseQp0aGUgd29ya2Fy b3VuZCB3aGVyZSBpdCdzIHJlcXVpcmVkLgoKUGF0Y2gxOgogIC0gQ1BVVFlQRSBkZWZpbml0aW9u cyBmb3IgRmFsa29yIENQVS4KClBhdGNoMjoKICAtIEFjdHVhbCB3b3JrYXJvdW5kIGNoYW5nZXMg Zm9yIGVycmF0dW0gRTEwNDEuCgpTaGFua2VyIERvbnRoaW5lbmkgKDIpOgogIGFybTY0OiBEZWZp bmUgY3B1dHlwZSBtYWNyb3MgZm9yIEZhbGtvciBDUFUKICBhcm02NDogQWRkIHNvZnR3YXJlIHdv cmthcm91bmQgZm9yIEZhbGtvciBlcnJhdHVtIDEwNDEKCiBEb2N1bWVudGF0aW9uL2FybTY0L3Np bGljb24tZXJyYXRhLnR4dCB8ICAxICsKIGFyY2gvYXJtNjQvS2NvbmZpZyAgICAgICAgICAgICAg ICAgICAgIHwgMTAgKysrKysrKysrKwogYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9hc3NlbWJsZXIu aCAgICAgfCAxOCArKysrKysrKysrKysrKysrKysKIGFyY2gvYXJtNjQvaW5jbHVkZS9hc20vY3B1 Y2Fwcy5oICAgICAgIHwgIDMgKystCiBhcmNoL2FybTY0L2luY2x1ZGUvYXNtL2NwdXR5cGUuaCAg ICAgICB8ICAyICsrCiBhcmNoL2FybTY0L2tlcm5lbC9jcHUtcmVzZXQuUyAgICAgICAgICB8ICAx ICsKIGFyY2gvYXJtNjQva2VybmVsL2NwdV9lcnJhdGEuYyAgICAgICAgIHwgMTYgKysrKysrKysr KysrKysrKwogYXJjaC9hcm02NC9rZXJuZWwvZWZpLWVudHJ5LlMgICAgICAgICAgfCAgMiArKwog YXJjaC9hcm02NC9rZXJuZWwvaGVhZC5TICAgICAgICAgICAgICAgfCAgMSArCiBhcmNoL2FybTY0 L2tlcm5lbC9yZWxvY2F0ZV9rZXJuZWwuUyAgICB8ICAxICsKIGFyY2gvYXJtNjQva3ZtL2h5cC1p bml0LlMgICAgICAgICAgICAgIHwgIDEgKwogMTEgZmlsZXMgY2hhbmdlZCwgNTUgaW5zZXJ0aW9u cygrKSwgMSBkZWxldGlvbigtKQoKLS0gClF1YWxjb21tIERhdGFjZW50ZXIgVGVjaG5vbG9naWVz LCBJbmMuIG9uIGJlaGFsZiBvZiB0aGUgUXVhbGNvbW0gVGVjaG5vbG9naWVzLCBJbmMuClF1YWxj b21tIFRlY2hub2xvZ2llcywgSW5jLiBpcyBhIG1lbWJlciBvZiB0aGUgQ29kZSBBdXJvcmEgRm9y dW0sIGEgTGludXggRm91bmRhdGlvbiBDb2xsYWJvcmF0aXZlIFByb2plY3QuCgpfX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwprdm1hcm0gbWFpbGluZyBsaXN0 Cmt2bWFybUBsaXN0cy5jcy5jb2x1bWJpYS5lZHUKaHR0cHM6Ly9saXN0cy5jcy5jb2x1bWJpYS5l ZHUvbWFpbG1hbi9saXN0aW5mby9rdm1hcm0K From mboxrd@z Thu Jan 1 00:00:00 1970 From: shankerd@codeaurora.org (Shanker Donthineni) Date: Sun, 12 Nov 2017 19:16:40 -0600 Subject: [PATCH v2 0/2] Implement a software workaround for Falkor erratum 1041 Message-ID: <1510535802-2799-1-git-send-email-shankerd@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Falkor CPU, we?ve discovered a hardware issue which might lead to a kernel crash or the unexpected behavior. The Falkor core may errantly access memory locations on speculative instruction fetches. This may happen whenever MMU translation state, SCTLR_ELn[M] bit is being changed from enabled to disabled for the currently running exception level. To prevent the errant hardware behavior, software must execute an ISB immediately prior to executing the MSR that changes SCTLR_ELn[M] from a value of 1 to 0. To simplify the complexity of a workaround, this patch series issues an ISB whenever SCTLR_ELn[M] is changed to 0 to fix the Falkor erratum 1041. Patch2 from V1 series got dropped to accommodate review comments. Apply the workaround where it's required. Patch1: - CPUTYPE definitions for Falkor CPU. Patch2: - Actual workaround changes for erratum E1041. Shanker Donthineni (2): arm64: Define cputype macros for Falkor CPU arm64: Add software workaround for Falkor erratum 1041 Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 10 ++++++++++ arch/arm64/include/asm/assembler.h | 18 ++++++++++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/cputype.h | 2 ++ arch/arm64/kernel/cpu-reset.S | 1 + arch/arm64/kernel/cpu_errata.c | 16 ++++++++++++++++ arch/arm64/kernel/efi-entry.S | 2 ++ arch/arm64/kernel/head.S | 1 + arch/arm64/kernel/relocate_kernel.S | 1 + arch/arm64/kvm/hyp-init.S | 1 + 11 files changed, 55 insertions(+), 1 deletion(-) -- Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751560AbdKMBQ7 (ORCPT ); Sun, 12 Nov 2017 20:16:59 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:56922 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751061AbdKMBQ5 (ORCPT ); Sun, 12 Nov 2017 20:16:57 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6A3B46055A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org From: Shanker Donthineni To: Will Deacon , Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Ard Biesheuvel , Matt Fleming , Christoffer Dall , linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Shanker Donthineni Subject: [PATCH v2 0/2] Implement a software workaround for Falkor erratum 1041 Date: Sun, 12 Nov 2017 19:16:40 -0600 Message-Id: <1510535802-2799-1-git-send-email-shankerd@codeaurora.org> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Falkor CPU, we’ve discovered a hardware issue which might lead to a kernel crash or the unexpected behavior. The Falkor core may errantly access memory locations on speculative instruction fetches. This may happen whenever MMU translation state, SCTLR_ELn[M] bit is being changed from enabled to disabled for the currently running exception level. To prevent the errant hardware behavior, software must execute an ISB immediately prior to executing the MSR that changes SCTLR_ELn[M] from a value of 1 to 0. To simplify the complexity of a workaround, this patch series issues an ISB whenever SCTLR_ELn[M] is changed to 0 to fix the Falkor erratum 1041. Patch2 from V1 series got dropped to accommodate review comments. Apply the workaround where it's required. Patch1: - CPUTYPE definitions for Falkor CPU. Patch2: - Actual workaround changes for erratum E1041. Shanker Donthineni (2): arm64: Define cputype macros for Falkor CPU arm64: Add software workaround for Falkor erratum 1041 Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 10 ++++++++++ arch/arm64/include/asm/assembler.h | 18 ++++++++++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/cputype.h | 2 ++ arch/arm64/kernel/cpu-reset.S | 1 + arch/arm64/kernel/cpu_errata.c | 16 ++++++++++++++++ arch/arm64/kernel/efi-entry.S | 2 ++ arch/arm64/kernel/head.S | 1 + arch/arm64/kernel/relocate_kernel.S | 1 + arch/arm64/kvm/hyp-init.S | 1 + 11 files changed, 55 insertions(+), 1 deletion(-) -- Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.