diff for duplicates of <1510587328.2699.8.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index 6f4e768..248f370 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,126 +1,200 @@ -SGkgU3RlcGhlbiwgTWljaGFlbCwNCg0KUGxlYXNlIHRyZWF0IHRoaXMgbWVzc2FnZSBhcyBhIHBv -bGl0ZSByZW1pbmRlciB0byByZXZpZXcgbXkgcGF0Y2guDQpJdCB3b3VsZCBiZSByZWFsbHkgbmlj -ZSB0byBzZWUgdGhpcyBwYXRjaCBpbiA0LjE1Lg0KDQpUaGFua3MuDQoNCk9uIEZyaSwgMjAxNy0w -OS0yOSBhdCAxNjoxMyArMDMwMCwgRXVnZW5peSBQYWx0c2V2IHdyb3RlOg0KPiBBZGQgb3B0aW9u -IHRvIHNldCBpbml0aWFsIG91dHB1dCBmcmVxdWVuY3kgb2YgcGxscyB2aWENCj4gImNsb2NrLWZy -ZXF1ZW5jeSIgcHJvcGVydHkgaW4gcGxsJ3MgZGV2aWNlIHRyZWUgbm9kZS4NCj4gVGhpcyBmcmVx -dWVuY3kgd2lsbCBiZSBzZXQgd2hpbGUgcGxsIGRyaXZlciBwcm9iZWQuDQo+IA0KPiBUaGUgdXNh -Z2UgZXhhbXBsZSBpcyBzZXR0aW5nIENQVSBjbG9jayBmcmVxdWVuY3kgb24gYm9vdA0KPiBTZWUg -ZGlzY3Vzc2lvbjoNCj4gaHR0cHM6Ly93d3cubWFpbC1hcmNoaXZlLmNvbS9saW51eC1zbnBzLWFy -Y0BsaXN0cy5pbmZyYWRlYWQub3JnL21zZzAyNjg5Lmh0bWwNCj4gDQo+IFNpZ25lZC1vZmYtYnk6 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See discussion: +> https://www.mail-archive.com/linux-snps-arc at lists.infradead.org/msg02689.html +> +> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> --- +> ?.../bindings/clock/snps,hsdk-pll-clock.txt?????????|??5 ++++ +> ?.../devicetree/bindings/clock/snps,pll-clock.txt???|??5 ++++ +> ?drivers/clk/axs10x/pll_clock.c?????????????????????| 34 ++++++++++++++++++++-- +> ?drivers/clk/clk-hsdk-pll.c?????????????????????????| 34 ++++++++++++++++++++-- +> ?4 files changed, 74 insertions(+), 4 deletions(-) +> +> diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> index c56c755..5703059 100644 +> --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> @@ -13,6 +13,10 @@ Required properties: +> ?- clocks: shall be the input parent clock phandle for the PLL. +> ?- #clock-cells: from common clock binding; Should always be set to 0. +> ? +> +Optional properties: +> +- clock-frequency: output frequency generated by pll in Hz which will be set +> +while probing. Should be a single cell. +> + +> ?Example: +> ? input_clk: input-clk { +> ? clock-frequency = <33333333>; +> @@ -25,4 +29,5 @@ Example: +> ? reg = <0x00 0x10>; +> ? #clock-cells = <0>; +> ? clocks = <&input_clk>; +> + clock-frequency = <1000000000>; +> ? }; +> diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> index 11fe487..5908f99 100644 +> --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. +> ?- clocks: shall be the input parent clock phandle for the PLL. +> ?- #clock-cells: from common clock binding; Should always be set to 0. +> ? +> +Optional properties: +> +- clock-frequency: output frequency generated by pll in Hz which will be set +> +while probing. Should be a single cell. +> + +> ?Example: +> ? input-clk: input-clk { +> ? clock-frequency = <33333333>; +> @@ -25,4 +29,5 @@ Example: +> ? reg = <0x80 0x10>, <0x100 0x10>; +> ? #clock-cells = <0>; +> ? clocks = <&input-clk>; +> + clock-frequency = <100000000>; +> ? }; +> diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c +> index 25d8c24..3f4345d 100644 +> --- a/drivers/clk/axs10x/pll_clock.c +> +++ b/drivers/clk/axs10x/pll_clock.c +> @@ -11,6 +11,7 @@ +> ?#include <linux/platform_device.h> +> ?#include <linux/module.h> +> ?#include <linux/clk-provider.h> +> +#include <linux/clk.h> +> ?#include <linux/delay.h> +> ?#include <linux/err.h> +> ?#include <linux/device.h> +> @@ -215,6 +216,25 @@ static const struct clk_ops axs10x_pll_ops = { +> ? .set_rate = axs10x_pll_set_rate, +> ?}; +> ? +> +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +> +{ +> + u32 requested_rate; +> + +> + /* If we specify initial pll output frequency try to set it */ +> + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) +> + return; +> + +> + if (clk_prepare_enable(clk)) { +> + pr_err("Cannot enable %s clock.\n", node->name); +> + return; +> + } +> + +> + if (clk_set_rate(clk, requested_rate)) +> + pr_err("Cannot set %s clock rate.\n", node->name); +> + +> + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +> +} +> + +> ?static int axs10x_pll_clk_probe(struct platform_device *pdev) +> ?{ +> ? struct device *dev = &pdev->dev; +> @@ -258,8 +278,15 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev) +> ? return ret; +> ? } +> ? +> - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, +> - &pll_clk->hw); +> + ret =??of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, +> + ??????&pll_clk->hw); +> + if (ret) +> + return ret; +> + +> + /* If we specify initial pll output frequency in dts try to set it */ +> + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); +> + +> + return 0; +> ?} +> ? +> ?static int axs10x_pll_clk_remove(struct platform_device *pdev) +> @@ -311,6 +338,9 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node) +> ? goto err_unregister_clk; +> ? } +> ? +> + /* If we specify initial pll output frequency in dts try to set it */ +> + set_pll_rate_from_of(pll_clk->hw.clk, node); +> + +> ? return; +> ? +> ?err_unregister_clk: +> diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c +> index bbf23717..74fd006 100644 +> --- a/drivers/clk/clk-hsdk-pll.c +> +++ b/drivers/clk/clk-hsdk-pll.c +> @@ -9,6 +9,7 @@ +> ? */ +> ? +> ?#include <linux/clk-provider.h> +> +#include <linux/clk.h> +> ?#include <linux/delay.h> +> ?#include <linux/device.h> +> ?#include <linux/err.h> +> @@ -295,6 +296,25 @@ static const struct clk_ops hsdk_pll_ops = { +> ? .set_rate = hsdk_pll_set_rate, +> ?}; +> ? +> +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +> +{ +> + u32 requested_rate; +> + +> + /* If we specify initial pll output frequency try to set it */ +> + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) +> + return; +> + +> + if (clk_prepare_enable(clk)) { +> + pr_err("Cannot enable %s clock.\n", node->name); +> + return; +> + } +> + +> + if (clk_set_rate(clk, requested_rate)) +> + pr_err("Cannot set %s clock rate.\n", node->name); +> + +> + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +> +} +> + +> ?static int hsdk_pll_clk_probe(struct platform_device *pdev) +> ?{ +> ? int ret; +> @@ -340,8 +360,15 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev) +> ? return ret; +> ? } +> ? +> - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, +> - &pll_clk->hw); +> + ret =??of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, +> + ??????&pll_clk->hw); +> + if (ret) +> + return ret; +> + +> + /* If we specify initial pll output frequency in dts try to set it */ +> + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); +> + +> + return 0; +> ?} +> ? +> ?static int hsdk_pll_clk_remove(struct platform_device *pdev) +> @@ -400,6 +427,9 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node) +> ? goto err_unmap_spec_regs; +> ? } +> ? +> + /* If we specify initial pll output frequency in dts try to set it */ +> + set_pll_rate_from_of(pll_clk->hw.clk, node); +> + +> ? return; +> ? +> ?err_unmap_spec_regs: +-- +?Eugeniy Paltsev diff --git a/a/content_digest b/N1/content_digest index e9562c1..e3240c4 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,141 +1,209 @@ "ref\020170929131357.26796-1-Eugeniy.Paltsev@synopsys.com\0" - "From\0Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\0" - "Subject\0Re: [PATCH] CLK: ARC: Set initial pll output frequency specified in device tree\0" + "From\0Eugeniy.Paltsev@synopsys.com (Eugeniy Paltsev)\0" + "Subject\0[PATCH] CLK: ARC: Set initial pll output frequency specified in device tree\0" "Date\0Mon, 13 Nov 2017 15:35:29 +0000\0" - "To\0linux-clk@vger.kernel.org <linux-clk@vger.kernel.org>\0" - "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" - mark.rutland@arm.com <mark.rutland@arm.com> - mturquette@baylibre.com <mturquette@baylibre.com> - sboyd@codeaurora.org <sboyd@codeaurora.org> - robh+dt@kernel.org <robh+dt@kernel.org> - " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" + "To\0linux-snps-arc@lists.infradead.org\0" "\00:1\0" "b\0" - "SGkgU3RlcGhlbiwgTWljaGFlbCwNCg0KUGxlYXNlIHRyZWF0IHRoaXMgbWVzc2FnZSBhcyBhIHBv\n" - "bGl0ZSByZW1pbmRlciB0byByZXZpZXcgbXkgcGF0Y2guDQpJdCB3b3VsZCBiZSByZWFsbHkgbmlj\n" - "ZSB0byBzZWUgdGhpcyBwYXRjaCBpbiA0LjE1Lg0KDQpUaGFua3MuDQoNCk9uIEZyaSwgMjAxNy0w\n" - "OS0yOSBhdCAxNjoxMyArMDMwMCwgRXVnZW5peSBQYWx0c2V2IHdyb3RlOg0KPiBBZGQgb3B0aW9u\n" - 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"X3VubWFwX3NwZWNfcmVnczsNCj4gwqAJfQ0KPiDCoA0KPiArCS8qIElmIHdlIHNwZWNpZnkgaW5p\n" - "dGlhbCBwbGwgb3V0cHV0IGZyZXF1ZW5jeSBpbiBkdHMgdHJ5IHRvIHNldCBpdCAqLw0KPiArCXNl\n" - "dF9wbGxfcmF0ZV9mcm9tX29mKHBsbF9jbGstPmh3LmNsaywgbm9kZSk7DQo+ICsNCj4gwqAJcmV0\n" - "dXJuOw0KPiDCoA0KPiDCoGVycl91bm1hcF9zcGVjX3JlZ3M6DQotLSANCsKgRXVnZW5peSBQYWx0\n" - c2V2 + "Hi Stephen, Michael,\n" + "\n" + "Please treat this message as a polite reminder to review my patch.\n" + "It would be really nice to see this patch in 4.15.\n" + "\n" + "Thanks.\n" + "\n" + "On Fri, 2017-09-29@16:13 +0300, Eugeniy Paltsev wrote:\n" + "> Add option to set initial output frequency of plls via\n" + "> \"clock-frequency\" property in pll's device tree node.\n" + "> This frequency will be set while pll driver probed.\n" + "> \n" + "> The usage example is setting CPU clock frequency on boot\n" + "> See discussion:\n" + "> https://www.mail-archive.com/linux-snps-arc at lists.infradead.org/msg02689.html\n" + "> \n" + "> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> ---\n" + "> ?.../bindings/clock/snps,hsdk-pll-clock.txt?????????|??5 ++++\n" + "> ?.../devicetree/bindings/clock/snps,pll-clock.txt???|??5 ++++\n" + "> ?drivers/clk/axs10x/pll_clock.c?????????????????????| 34 ++++++++++++++++++++--\n" + "> ?drivers/clk/clk-hsdk-pll.c?????????????????????????| 34 ++++++++++++++++++++--\n" + "> ?4 files changed, 74 insertions(+), 4 deletions(-)\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> index c56c755..5703059 100644\n" + "> --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> @@ -13,6 +13,10 @@ Required properties:\n" + "> ?- clocks: shall be the input parent clock phandle for the PLL.\n" + "> ?- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> ?\n" + "> +Optional properties:\n" + "> +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> +while probing. Should be a single cell.\n" + "> +\n" + "> ?Example:\n" + "> ?\tinput_clk: input-clk {\n" + "> ?\t\tclock-frequency = <33333333>;\n" + "> @@ -25,4 +29,5 @@ Example:\n" + "> ?\t\treg = <0x00 0x10>;\n" + "> ?\t\t#clock-cells = <0>;\n" + "> ?\t\tclocks = <&input_clk>;\n" + "> +\t\tclock-frequency = <1000000000>;\n" + "> ?\t};\n" + "> diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> index 11fe487..5908f99 100644\n" + "> --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register.\n" + "> ?- clocks: shall be the input parent clock phandle for the PLL.\n" + "> ?- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> ?\n" + "> +Optional properties:\n" + "> +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> +while probing. Should be a single cell.\n" + "> +\n" + "> ?Example:\n" + "> ?\tinput-clk: input-clk {\n" + "> ?\t\tclock-frequency = <33333333>;\n" + "> @@ -25,4 +29,5 @@ Example:\n" + "> ?\t\treg = <0x80 0x10>, <0x100 0x10>;\n" + "> ?\t\t#clock-cells = <0>;\n" + "> ?\t\tclocks = <&input-clk>;\n" + "> +\t\tclock-frequency = <100000000>;\n" + "> ?\t};\n" + "> diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c\n" + "> index 25d8c24..3f4345d 100644\n" + "> --- a/drivers/clk/axs10x/pll_clock.c\n" + "> +++ b/drivers/clk/axs10x/pll_clock.c\n" + "> @@ -11,6 +11,7 @@\n" + "> ?#include <linux/platform_device.h>\n" + "> ?#include <linux/module.h>\n" + "> ?#include <linux/clk-provider.h>\n" + "> +#include <linux/clk.h>\n" + "> ?#include <linux/delay.h>\n" + "> ?#include <linux/err.h>\n" + "> ?#include <linux/device.h>\n" + "> @@ -215,6 +216,25 @@ static const struct clk_ops axs10x_pll_ops = {\n" + "> ?\t.set_rate = axs10x_pll_set_rate,\n" + "> ?};\n" + "> ?\n" + "> +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node)\n" + "> +{\n" + "> +\tu32 requested_rate;\n" + "> +\n" + "> +\t/* If we specify initial pll output frequency try to set it */\n" + "> +\tif (of_property_read_u32(node, \"clock-frequency\", &requested_rate))\n" + "> +\t\treturn;\n" + "> +\n" + "> +\tif (clk_prepare_enable(clk)) {\n" + "> +\t\tpr_err(\"Cannot enable %s clock.\\n\", node->name);\n" + "> +\t\treturn;\n" + "> +\t}\n" + "> +\n" + "> +\tif (clk_set_rate(clk, requested_rate))\n" + "> +\t\tpr_err(\"Cannot set %s clock rate.\\n\", node->name);\n" + "> +\n" + "> +\tpr_debug(\"Set %s clock to %u\\n\", node->name, requested_rate);\n" + "> +}\n" + "> +\n" + "> ?static int axs10x_pll_clk_probe(struct platform_device *pdev)\n" + "> ?{\n" + "> ?\tstruct device *dev = &pdev->dev;\n" + "> @@ -258,8 +278,15 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev)\n" + "> ?\t\treturn ret;\n" + "> ?\t}\n" + "> ?\n" + "> -\treturn of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n" + "> -\t\t\t&pll_clk->hw);\n" + "> +\tret =??of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n" + "> +\t\t\t\t??????&pll_clk->hw);\n" + "> +\tif (ret)\n" + "> +\t\treturn ret;\n" + "> +\n" + "> +\t/* If we specify initial pll output frequency in dts try to set it */\n" + "> +\tset_pll_rate_from_of(pll_clk->hw.clk, dev->of_node);\n" + "> +\n" + "> +\treturn 0;\n" + "> ?}\n" + "> ?\n" + "> ?static int axs10x_pll_clk_remove(struct platform_device *pdev)\n" + "> @@ -311,6 +338,9 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node)\n" + "> ?\t\tgoto err_unregister_clk;\n" + "> ?\t}\n" + "> ?\n" + "> +\t/* If we specify initial pll output frequency in dts try to set it */\n" + "> +\tset_pll_rate_from_of(pll_clk->hw.clk, node);\n" + "> +\n" + "> ?\treturn;\n" + "> ?\n" + "> ?err_unregister_clk:\n" + "> diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c\n" + "> index bbf23717..74fd006 100644\n" + "> --- a/drivers/clk/clk-hsdk-pll.c\n" + "> +++ b/drivers/clk/clk-hsdk-pll.c\n" + "> @@ -9,6 +9,7 @@\n" + "> ? */\n" + "> ?\n" + "> ?#include <linux/clk-provider.h>\n" + "> +#include <linux/clk.h>\n" + "> ?#include <linux/delay.h>\n" + "> ?#include <linux/device.h>\n" + "> ?#include <linux/err.h>\n" + "> @@ -295,6 +296,25 @@ static const struct clk_ops hsdk_pll_ops = {\n" + "> ?\t.set_rate = hsdk_pll_set_rate,\n" + "> ?};\n" + "> ?\n" + "> +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node)\n" + "> +{\n" + "> +\tu32 requested_rate;\n" + "> +\n" + "> +\t/* If we specify initial pll output frequency try to set it */\n" + "> +\tif (of_property_read_u32(node, \"clock-frequency\", &requested_rate))\n" + "> +\t\treturn;\n" + "> +\n" + "> +\tif (clk_prepare_enable(clk)) {\n" + "> +\t\tpr_err(\"Cannot enable %s clock.\\n\", node->name);\n" + "> +\t\treturn;\n" + "> +\t}\n" + "> +\n" + "> +\tif (clk_set_rate(clk, requested_rate))\n" + "> +\t\tpr_err(\"Cannot set %s clock rate.\\n\", node->name);\n" + "> +\n" + "> +\tpr_debug(\"Set %s clock to %u\\n\", node->name, requested_rate);\n" + "> +}\n" + "> +\n" + "> ?static int hsdk_pll_clk_probe(struct platform_device *pdev)\n" + "> ?{\n" + "> ?\tint ret;\n" + "> @@ -340,8 +360,15 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev)\n" + "> ?\t\treturn ret;\n" + "> ?\t}\n" + "> ?\n" + "> -\treturn of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n" + "> -\t\t\t&pll_clk->hw);\n" + "> +\tret =??of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n" + "> +\t\t\t\t??????&pll_clk->hw);\n" + "> +\tif (ret)\n" + "> +\t\treturn ret;\n" + "> +\n" + "> +\t/* If we specify initial pll output frequency in dts try to set it */\n" + "> +\tset_pll_rate_from_of(pll_clk->hw.clk, dev->of_node);\n" + "> +\n" + "> +\treturn 0;\n" + "> ?}\n" + "> ?\n" + "> ?static int hsdk_pll_clk_remove(struct platform_device *pdev)\n" + "> @@ -400,6 +427,9 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node)\n" + "> ?\t\tgoto err_unmap_spec_regs;\n" + "> ?\t}\n" + "> ?\n" + "> +\t/* If we specify initial pll output frequency in dts try to set it */\n" + "> +\tset_pll_rate_from_of(pll_clk->hw.clk, node);\n" + "> +\n" + "> ?\treturn;\n" + "> ?\n" + "> ?err_unmap_spec_regs:\n" + "-- \n" + ?Eugeniy Paltsev -19d1afb0b88c8a52845288fab6c23ef67b5d464f5d523eab99ad39e5bdc1381c +b44ab7cbb8e8e8cefbf0bef4f6b643ccf1db67cebf7b2f9fbd66c04e521a1bf4
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https://www.mail-archive.com/linux-snps-arc@lists.infradead.org/msg02689.html +> +> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> +> --- +> .../bindings/clock/snps,hsdk-pll-clock.txt | 5 ++++ +> .../devicetree/bindings/clock/snps,pll-clock.txt | 5 ++++ +> drivers/clk/axs10x/pll_clock.c | 34 ++++++++++++++++++++-- +> drivers/clk/clk-hsdk-pll.c | 34 ++++++++++++++++++++-- +> 4 files changed, 74 insertions(+), 4 deletions(-) +> +> diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> index c56c755..5703059 100644 +> --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> @@ -13,6 +13,10 @@ Required properties: +> - clocks: shall be the input parent clock phandle for the PLL. +> - #clock-cells: from common clock binding; Should always be set to 0. +> +> +Optional properties: +> +- clock-frequency: output frequency generated by pll in Hz which will be set +> +while probing. Should be a single cell. +> + +> Example: +> input_clk: input-clk { +> clock-frequency = <33333333>; +> @@ -25,4 +29,5 @@ Example: +> reg = <0x00 0x10>; +> #clock-cells = <0>; +> clocks = <&input_clk>; +> + clock-frequency = <1000000000>; +> }; +> diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> index 11fe487..5908f99 100644 +> --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. +> - clocks: shall be the input parent clock phandle for the PLL. +> - #clock-cells: from common clock binding; Should always be set to 0. +> +> +Optional properties: +> +- clock-frequency: output frequency generated by pll in Hz which will be set +> +while probing. Should be a single cell. +> + +> Example: +> input-clk: input-clk { +> clock-frequency = <33333333>; +> @@ -25,4 +29,5 @@ Example: +> reg = <0x80 0x10>, <0x100 0x10>; +> #clock-cells = <0>; +> clocks = <&input-clk>; +> + clock-frequency = <100000000>; +> }; +> diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c +> index 25d8c24..3f4345d 100644 +> --- a/drivers/clk/axs10x/pll_clock.c +> +++ b/drivers/clk/axs10x/pll_clock.c +> @@ -11,6 +11,7 @@ +> #include <linux/platform_device.h> +> #include <linux/module.h> +> #include <linux/clk-provider.h> +> +#include <linux/clk.h> +> #include <linux/delay.h> +> #include <linux/err.h> +> #include <linux/device.h> +> @@ -215,6 +216,25 @@ static const struct clk_ops axs10x_pll_ops = { +> .set_rate = axs10x_pll_set_rate, +> }; +> +> +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +> +{ +> + u32 requested_rate; +> + +> + /* If we specify initial pll output frequency try to set it */ +> + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) +> + return; +> + +> + if (clk_prepare_enable(clk)) { +> + pr_err("Cannot enable %s clock.\n", node->name); +> + return; +> + } +> + +> + if (clk_set_rate(clk, requested_rate)) +> + pr_err("Cannot set %s clock rate.\n", node->name); +> + +> + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +> +} +> + +> static int axs10x_pll_clk_probe(struct platform_device *pdev) +> { +> struct device *dev = &pdev->dev; +> @@ -258,8 +278,15 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev) +> return ret; +> } +> +> - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, +> - &pll_clk->hw); +> + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, +> + &pll_clk->hw); +> + if (ret) +> + return ret; +> + +> + /* If we specify initial pll output frequency in dts try to set it */ +> + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); +> + +> + return 0; +> } +> +> static int axs10x_pll_clk_remove(struct platform_device *pdev) +> @@ -311,6 +338,9 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node) +> goto err_unregister_clk; +> } +> +> + /* If we specify initial pll output frequency in dts try to set it */ +> + set_pll_rate_from_of(pll_clk->hw.clk, node); +> + +> return; +> +> err_unregister_clk: +> diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c +> index bbf23717..74fd006 100644 +> --- a/drivers/clk/clk-hsdk-pll.c +> +++ b/drivers/clk/clk-hsdk-pll.c +> @@ -9,6 +9,7 @@ +> */ +> +> #include <linux/clk-provider.h> +> +#include <linux/clk.h> +> #include <linux/delay.h> +> #include <linux/device.h> +> #include <linux/err.h> +> @@ -295,6 +296,25 @@ static const struct clk_ops hsdk_pll_ops = { +> .set_rate = hsdk_pll_set_rate, +> }; +> +> +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +> +{ +> + u32 requested_rate; +> + +> + /* If we specify initial pll output frequency try to set it */ +> + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) +> + return; +> + +> + if (clk_prepare_enable(clk)) { +> + pr_err("Cannot enable %s clock.\n", node->name); +> + return; +> + } +> + +> + if (clk_set_rate(clk, requested_rate)) +> + pr_err("Cannot set %s clock rate.\n", node->name); +> + +> + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +> +} +> + +> static int hsdk_pll_clk_probe(struct platform_device *pdev) +> { +> int ret; +> @@ -340,8 +360,15 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev) +> return ret; +> } +> +> - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, +> - &pll_clk->hw); +> + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, +> + &pll_clk->hw); +> + if (ret) +> + return ret; +> + +> + /* If we specify initial pll output frequency in dts try to set it */ +> + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); +> + +> + return 0; +> } +> +> static int hsdk_pll_clk_remove(struct platform_device *pdev) +> @@ -400,6 +427,9 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node) +> goto err_unmap_spec_regs; +> } +> +> + /* If we specify initial pll output frequency in dts try to set it */ +> + set_pll_rate_from_of(pll_clk->hw.clk, node); +> + +> return; +> +> err_unmap_spec_regs: +-- + Eugeniy Paltsev diff --git a/a/content_digest b/N2/content_digest index e9562c1..6dd716f 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -11,131 +11,205 @@ " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" "\00:1\0" "b\0" - "SGkgU3RlcGhlbiwgTWljaGFlbCwNCg0KUGxlYXNlIHRyZWF0IHRoaXMgbWVzc2FnZSBhcyBhIHBv\n" - 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"Cj4gwqBzdGF0aWMgaW50IGhzZGtfcGxsX2Nsa19yZW1vdmUoc3RydWN0IHBsYXRmb3JtX2Rldmlj\n" - "ZSAqcGRldikNCj4gQEAgLTQwMCw2ICs0MjcsOSBAQCBzdGF0aWMgdm9pZCBfX2luaXQgb2ZfaHNk\n" - "a19wbGxfY2xrX3NldHVwKHN0cnVjdCBkZXZpY2Vfbm9kZSAqbm9kZSkNCj4gwqAJCWdvdG8gZXJy\n" - "X3VubWFwX3NwZWNfcmVnczsNCj4gwqAJfQ0KPiDCoA0KPiArCS8qIElmIHdlIHNwZWNpZnkgaW5p\n" - "dGlhbCBwbGwgb3V0cHV0IGZyZXF1ZW5jeSBpbiBkdHMgdHJ5IHRvIHNldCBpdCAqLw0KPiArCXNl\n" - "dF9wbGxfcmF0ZV9mcm9tX29mKHBsbF9jbGstPmh3LmNsaywgbm9kZSk7DQo+ICsNCj4gwqAJcmV0\n" - "dXJuOw0KPiDCoA0KPiDCoGVycl91bm1hcF9zcGVjX3JlZ3M6DQotLSANCsKgRXVnZW5peSBQYWx0\n" - c2V2 + "Hi Stephen, Michael,\n" + "\n" + "Please treat this message as a polite reminder to review my patch.\n" + "It would be really nice to see this patch in 4.15.\n" + "\n" + "Thanks.\n" + "\n" + "On Fri, 2017-09-29 at 16:13 +0300, Eugeniy Paltsev wrote:\n" + "> Add option to set initial output frequency of plls via\n" + "> \"clock-frequency\" property in pll's device tree node.\n" + "> This frequency will be set while pll driver probed.\n" + "> \n" + "> The usage example is setting CPU clock frequency on boot\n" + "> See discussion:\n" + "> https://www.mail-archive.com/linux-snps-arc@lists.infradead.org/msg02689.html\n" + "> \n" + "> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" + "> ---\n" + "> \302\240.../bindings/clock/snps,hsdk-pll-clock.txt\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2405 ++++\n" + "> \302\240.../devicetree/bindings/clock/snps,pll-clock.txt\302\240\302\240\302\240|\302\240\302\2405 ++++\n" + "> \302\240drivers/clk/axs10x/pll_clock.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 34 ++++++++++++++++++++--\n" + "> \302\240drivers/clk/clk-hsdk-pll.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 34 ++++++++++++++++++++--\n" + "> \302\2404 files changed, 74 insertions(+), 4 deletions(-)\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> index c56c755..5703059 100644\n" + "> --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> @@ -13,6 +13,10 @@ Required properties:\n" + "> \302\240- clocks: shall be the input parent clock phandle for the PLL.\n" + "> \302\240- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> \302\240\n" + "> +Optional properties:\n" + "> +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> +while probing. Should be a single cell.\n" + "> +\n" + "> \302\240Example:\n" + "> \302\240\tinput_clk: input-clk {\n" + "> \302\240\t\tclock-frequency = <33333333>;\n" + "> @@ -25,4 +29,5 @@ Example:\n" + "> \302\240\t\treg = <0x00 0x10>;\n" + "> \302\240\t\t#clock-cells = <0>;\n" + "> \302\240\t\tclocks = <&input_clk>;\n" + "> +\t\tclock-frequency = <1000000000>;\n" + "> \302\240\t};\n" + "> diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> index 11fe487..5908f99 100644\n" + "> --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register.\n" + "> \302\240- clocks: shall be the input parent clock phandle for the PLL.\n" + "> \302\240- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> \302\240\n" + "> +Optional properties:\n" + "> +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> +while probing. Should be a single cell.\n" + "> +\n" + "> \302\240Example:\n" + "> \302\240\tinput-clk: input-clk {\n" + "> \302\240\t\tclock-frequency = <33333333>;\n" + "> @@ -25,4 +29,5 @@ Example:\n" + "> \302\240\t\treg = <0x80 0x10>, <0x100 0x10>;\n" + "> \302\240\t\t#clock-cells = <0>;\n" + "> \302\240\t\tclocks = <&input-clk>;\n" + "> +\t\tclock-frequency = <100000000>;\n" + "> \302\240\t};\n" + "> diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c\n" + "> index 25d8c24..3f4345d 100644\n" + "> --- a/drivers/clk/axs10x/pll_clock.c\n" + "> +++ b/drivers/clk/axs10x/pll_clock.c\n" + "> @@ -11,6 +11,7 @@\n" + "> \302\240#include <linux/platform_device.h>\n" + "> \302\240#include <linux/module.h>\n" + "> \302\240#include <linux/clk-provider.h>\n" + "> +#include <linux/clk.h>\n" + "> \302\240#include <linux/delay.h>\n" + "> \302\240#include <linux/err.h>\n" + "> \302\240#include <linux/device.h>\n" + "> @@ -215,6 +216,25 @@ static const struct clk_ops axs10x_pll_ops = {\n" + "> \302\240\t.set_rate = axs10x_pll_set_rate,\n" + "> \302\240};\n" + "> \302\240\n" + "> +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node)\n" + "> +{\n" + "> +\tu32 requested_rate;\n" + "> +\n" + "> +\t/* If we specify initial pll output frequency try to set it */\n" + "> +\tif (of_property_read_u32(node, \"clock-frequency\", &requested_rate))\n" + "> +\t\treturn;\n" + "> +\n" + "> +\tif (clk_prepare_enable(clk)) {\n" + "> +\t\tpr_err(\"Cannot enable %s clock.\\n\", node->name);\n" + "> +\t\treturn;\n" + "> +\t}\n" + "> +\n" + "> +\tif (clk_set_rate(clk, requested_rate))\n" + "> +\t\tpr_err(\"Cannot set %s clock rate.\\n\", node->name);\n" + "> +\n" + "> +\tpr_debug(\"Set %s clock to %u\\n\", node->name, requested_rate);\n" + "> +}\n" + "> +\n" + "> \302\240static int axs10x_pll_clk_probe(struct platform_device *pdev)\n" + "> \302\240{\n" + "> \302\240\tstruct device *dev = &pdev->dev;\n" + "> @@ -258,8 +278,15 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev)\n" + "> \302\240\t\treturn ret;\n" + "> \302\240\t}\n" + "> \302\240\n" + "> -\treturn of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n" + "> -\t\t\t&pll_clk->hw);\n" + "> +\tret =\302\240\302\240of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n" + "> +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240&pll_clk->hw);\n" + "> +\tif (ret)\n" + "> +\t\treturn ret;\n" + "> +\n" + "> +\t/* If we specify initial pll output frequency in dts try to set it */\n" + "> +\tset_pll_rate_from_of(pll_clk->hw.clk, dev->of_node);\n" + "> +\n" + "> +\treturn 0;\n" + "> \302\240}\n" + "> \302\240\n" + "> \302\240static int axs10x_pll_clk_remove(struct platform_device *pdev)\n" + "> @@ -311,6 +338,9 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node)\n" + "> \302\240\t\tgoto err_unregister_clk;\n" + "> \302\240\t}\n" + "> \302\240\n" + "> +\t/* If we specify initial pll output frequency in dts try to set it */\n" + "> +\tset_pll_rate_from_of(pll_clk->hw.clk, node);\n" + "> +\n" + "> \302\240\treturn;\n" + "> \302\240\n" + "> \302\240err_unregister_clk:\n" + "> diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c\n" + "> index bbf23717..74fd006 100644\n" + "> --- a/drivers/clk/clk-hsdk-pll.c\n" + "> +++ b/drivers/clk/clk-hsdk-pll.c\n" + "> @@ -9,6 +9,7 @@\n" + "> \302\240 */\n" + "> \302\240\n" + "> \302\240#include <linux/clk-provider.h>\n" + "> +#include <linux/clk.h>\n" + "> \302\240#include <linux/delay.h>\n" + "> \302\240#include <linux/device.h>\n" + "> \302\240#include <linux/err.h>\n" + "> @@ -295,6 +296,25 @@ static const struct clk_ops hsdk_pll_ops = {\n" + "> \302\240\t.set_rate = hsdk_pll_set_rate,\n" + "> \302\240};\n" + "> \302\240\n" + "> +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node)\n" + "> +{\n" + "> +\tu32 requested_rate;\n" + "> +\n" + "> +\t/* If we specify initial pll output frequency try to set it */\n" + "> +\tif (of_property_read_u32(node, \"clock-frequency\", &requested_rate))\n" + "> +\t\treturn;\n" + "> +\n" + "> +\tif (clk_prepare_enable(clk)) {\n" + "> +\t\tpr_err(\"Cannot enable %s clock.\\n\", node->name);\n" + "> +\t\treturn;\n" + "> +\t}\n" + "> +\n" + "> +\tif (clk_set_rate(clk, requested_rate))\n" + "> +\t\tpr_err(\"Cannot set %s clock rate.\\n\", node->name);\n" + "> +\n" + "> +\tpr_debug(\"Set %s clock to %u\\n\", node->name, requested_rate);\n" + "> +}\n" + "> +\n" + "> \302\240static int hsdk_pll_clk_probe(struct platform_device *pdev)\n" + "> \302\240{\n" + "> \302\240\tint ret;\n" + "> @@ -340,8 +360,15 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev)\n" + "> \302\240\t\treturn ret;\n" + "> \302\240\t}\n" + "> \302\240\n" + "> -\treturn of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n" + "> -\t\t\t&pll_clk->hw);\n" + "> +\tret =\302\240\302\240of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n" + "> +\t\t\t\t\302\240\302\240\302\240\302\240\302\240\302\240&pll_clk->hw);\n" + "> +\tif (ret)\n" + "> +\t\treturn ret;\n" + "> +\n" + "> +\t/* If we specify initial pll output frequency in dts try to set it */\n" + "> +\tset_pll_rate_from_of(pll_clk->hw.clk, dev->of_node);\n" + "> +\n" + "> +\treturn 0;\n" + "> \302\240}\n" + "> \302\240\n" + "> \302\240static int hsdk_pll_clk_remove(struct platform_device *pdev)\n" + "> @@ -400,6 +427,9 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node)\n" + "> \302\240\t\tgoto err_unmap_spec_regs;\n" + "> \302\240\t}\n" + "> \302\240\n" + "> +\t/* If we specify initial pll output frequency in dts try to set it */\n" + "> +\tset_pll_rate_from_of(pll_clk->hw.clk, node);\n" + "> +\n" + "> \302\240\treturn;\n" + "> \302\240\n" + "> \302\240err_unmap_spec_regs:\n" + "-- \n" + "\302\240Eugeniy Paltsev" -19d1afb0b88c8a52845288fab6c23ef67b5d464f5d523eab99ad39e5bdc1381c +7beebb4ece846e83846691af9bcce68c862aa51aa404a96b385c91f04d9c49cb
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