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probed. +> > +> > The usage example is setting CPU clock frequency on boot +> > See discussion: +> > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c=DPL6 +> > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29kVMLW +> > chYfhSGT2M&e= +> > +> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> +> > --- +> > ?.../bindings/clock/snps,hsdk-pll-clock.txt?????????|??5 ++++ +> > ?.../devicetree/bindings/clock/snps,pll-clock.txt???|??5 ++++ +> > ?drivers/clk/axs10x/pll_clock.c?????????????????????| 34 ++++++++++++++++++++-- +> > ?drivers/clk/clk-hsdk-pll.c?????????????????????????| 34 ++++++++++++++++++++-- +> > ?4 files changed, 74 insertions(+), 4 deletions(-) +> > +> > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > index c56c755..5703059 100644 +> > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > @@ -13,6 +13,10 @@ Required properties: +> > ?- clocks: shall be the input parent clock phandle for the PLL. +> > ?- #clock-cells: from common clock binding; Should always be set to 0. +> > ? +> > +Optional properties: +> > +- clock-frequency: output frequency generated by pll in Hz which will be set +> > +while probing. Should be a single cell. +> > + +> > ?Example: +> > ? input_clk: input-clk { +> > ? clock-frequency = <33333333>; +> > @@ -25,4 +29,5 @@ Example: +> > ? reg = <0x00 0x10>; +> > ? #clock-cells = <0>; +> > ? clocks = <&input_clk>; +> > + clock-frequency = <1000000000>; +> > ? }; +> > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > index 11fe487..5908f99 100644 +> > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. +> > ?- clocks: shall be the input parent clock phandle for the PLL. +> > ?- #clock-cells: from common clock binding; Should always be set to 0. +> > ? +> > +Optional properties: +> > +- clock-frequency: output frequency generated by pll in Hz which will be set +> > +while probing. Should be a single cell. +> > + +> > ?Example: +> > ? input-clk: input-clk { +> > ? clock-frequency = <33333333>; +> > @@ -25,4 +29,5 @@ Example: +> > ? reg = <0x80 0x10>, <0x100 0x10>; +> > ? #clock-cells = <0>; +> > ? clocks = <&input-clk>; +> > + clock-frequency = <100000000>; +> > ? }; +> +> You may check Documentation/devicetree/bindings/clock/clock-bindings.txt +> about how to assign initial clock rates, in general 'clock-frequency' +> property is a property of clock consumers with two exceptions of simple +> clock sources, namely it is used in fixed clock and PWM clock bindings. + +I think that's what we agreed on with Rob Herring back in the day. +Have you checked this post of him on the topic? +http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002909.html + +Just FYI it all started from my question here: +http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002900.html + +-Alexey diff --git a/a/content_digest b/N1/content_digest index 770bdb2..7b1ea38 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,85 +1,89 @@ "ref\020171114122020.9800-1-Eugeniy.Paltsev@synopsys.com\0" "ref\01b07abf9-c94d-1759-4182-519b77c8bb37@mentor.com\0" - "From\0Alexey Brodkin <Alexey.Brodkin@synopsys.com>\0" - "Subject\0Re: [PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree\0" + "From\0Alexey.Brodkin@synopsys.com (Alexey Brodkin)\0" + "Subject\0[PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree\0" "Date\0Tue, 14 Nov 2017 21:19:34 +0000\0" - "To\0vladimir_zapolskiy@mentor.com <vladimir_zapolskiy@mentor.com>\0" - "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" - robh+dt@kernel.org <robh+dt@kernel.org> - mturquette@baylibre.com <mturquette@baylibre.com> - Eugeniy.Paltsev@synopsys.com <Eugeniy.Paltsev@synopsys.com> - linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org> - mark.rutland@arm.com <mark.rutland@arm.com> - linux-clk@vger.kernel.org <linux-clk@vger.kernel.org> - " sboyd@codeaurora.org <sboyd@codeaurora.org>\0" + "To\0linux-snps-arc@lists.infradead.org\0" "\00:1\0" "b\0" - "SGkgVmxhZGltaXIsDQoNCk9uIFR1ZSwgMjAxNy0xMS0xNCBhdCAxOTowMSArMDIwMCwgVmxhZGlt\n" - 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bC9saW51eC1zbnBzLWFyYy8yMDE3LVNlcHRlbWJlci8wMDI5MDAuaHRtbA0KDQotQWxleGV5 + "Hi Vladimir,\n" + "\n" + "On Tue, 2017-11-14@19:01 +0200, Vladimir Zapolskiy wrote:\n" + "> On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote:\n" + "> > \n" + "> > Add option to set initial output frequency of plls via\n" + "> > \"clock-frequency\" property in pll's device tree node.\n" + "> > This frequency will be set while pll driver probed.\n" + "> > \n" + "> > The usage example is setting CPU clock frequency on boot\n" + "> > See discussion:\n" + "> > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c=DPL6\n" + "> > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29kVMLW\n" + "> > chYfhSGT2M&e=\n" + "> > \n" + "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>\n" + "> > ---\n" + "> > ?.../bindings/clock/snps,hsdk-pll-clock.txt?????????|??5 ++++\n" + "> > ?.../devicetree/bindings/clock/snps,pll-clock.txt???|??5 ++++\n" + "> > ?drivers/clk/axs10x/pll_clock.c?????????????????????| 34 ++++++++++++++++++++--\n" + "> > ?drivers/clk/clk-hsdk-pll.c?????????????????????????| 34 ++++++++++++++++++++--\n" + "> > ?4 files changed, 74 insertions(+), 4 deletions(-)\n" + "> > \n" + "> > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > index c56c755..5703059 100644\n" + "> > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > @@ -13,6 +13,10 @@ Required properties:\n" + "> > ?- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > ?- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > ?\n" + "> > +Optional properties:\n" + "> > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> > +while probing. Should be a single cell.\n" + "> > +\n" + "> > ?Example:\n" + "> > ?\tinput_clk: input-clk {\n" + "> > ?\t\tclock-frequency = <33333333>;\n" + "> > @@ -25,4 +29,5 @@ Example:\n" + "> > ?\t\treg = <0x00 0x10>;\n" + "> > ?\t\t#clock-cells = <0>;\n" + "> > ?\t\tclocks = <&input_clk>;\n" + "> > +\t\tclock-frequency = <1000000000>;\n" + "> > ?\t};\n" + "> > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > index 11fe487..5908f99 100644\n" + "> > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register.\n" + "> > ?- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > ?- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > ?\n" + "> > +Optional properties:\n" + "> > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> > +while probing. Should be a single cell.\n" + "> > +\n" + "> > ?Example:\n" + "> > ?\tinput-clk: input-clk {\n" + "> > ?\t\tclock-frequency = <33333333>;\n" + "> > @@ -25,4 +29,5 @@ Example:\n" + "> > ?\t\treg = <0x80 0x10>, <0x100 0x10>;\n" + "> > ?\t\t#clock-cells = <0>;\n" + "> > ?\t\tclocks = <&input-clk>;\n" + "> > +\t\tclock-frequency = <100000000>;\n" + "> > ?\t};\n" + "> \n" + "> You may check Documentation/devicetree/bindings/clock/clock-bindings.txt\n" + "> about how to assign initial clock rates, in general 'clock-frequency'\n" + "> property is a property of clock consumers with two exceptions of simple\n" + "> clock sources, namely it is used in fixed clock and PWM clock bindings.\n" + "\n" + "I think that's what we agreed on with Rob Herring back in the day.\n" + "Have you checked this post of him on the topic?\n" + "http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002909.html\n" + "\n" + "Just FYI it all started from my question here:\n" + "http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002900.html\n" + "\n" + -Alexey -478b96ac53d6452cf5ca6819987fabb6435acbce0b755a27bbf828dd0ab38866 +425ec9a7aa5522af2e97f42a6676b35b2f56c9a5a87e12fa3855e00388e2c8af
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See discussion: +> > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c=DPL6 +> > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29kVMLW +> > chYfhSGT2M&e= +> > +> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> +> > --- +> > .../bindings/clock/snps,hsdk-pll-clock.txt | 5 ++++ +> > .../devicetree/bindings/clock/snps,pll-clock.txt | 5 ++++ +> > drivers/clk/axs10x/pll_clock.c | 34 ++++++++++++++++++++-- +> > drivers/clk/clk-hsdk-pll.c | 34 ++++++++++++++++++++-- +> > 4 files changed, 74 insertions(+), 4 deletions(-) +> > +> > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > index c56c755..5703059 100644 +> > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +> > @@ -13,6 +13,10 @@ Required properties: +> > - clocks: shall be the input parent clock phandle for the PLL. +> > - #clock-cells: from common clock binding; Should always be set to 0. +> > +> > +Optional properties: +> > +- clock-frequency: output frequency generated by pll in Hz which will be set +> > +while probing. Should be a single cell. +> > + +> > Example: +> > input_clk: input-clk { +> > clock-frequency = <33333333>; +> > @@ -25,4 +29,5 @@ Example: +> > reg = <0x00 0x10>; +> > #clock-cells = <0>; +> > clocks = <&input_clk>; +> > + clock-frequency = <1000000000>; +> > }; +> > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > index 11fe487..5908f99 100644 +> > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +> > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. +> > - clocks: shall be the input parent clock phandle for the PLL. +> > - #clock-cells: from common clock binding; Should always be set to 0. +> > +> > +Optional properties: +> > +- clock-frequency: output frequency generated by pll in Hz which will be set +> > +while probing. Should be a single cell. +> > + +> > Example: +> > input-clk: input-clk { +> > clock-frequency = <33333333>; +> > @@ -25,4 +29,5 @@ Example: +> > reg = <0x80 0x10>, <0x100 0x10>; +> > #clock-cells = <0>; +> > clocks = <&input-clk>; +> > + clock-frequency = <100000000>; +> > }; +> +> You may check Documentation/devicetree/bindings/clock/clock-bindings.txt +> about how to assign initial clock rates, in general 'clock-frequency' +> property is a property of clock consumers with two exceptions of simple +> clock sources, namely it is used in fixed clock and PWM clock bindings. + +I think that's what we agreed on with Rob Herring back in the day. +Have you checked this post of him on the topic? +http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002909.html + +Just FYI it all started from my question here: +http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002900.html + +-Alexey diff --git a/a/content_digest b/N2/content_digest index 770bdb2..fa1db57 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -14,72 +14,84 @@ " sboyd@codeaurora.org <sboyd@codeaurora.org>\0" "\00:1\0" "b\0" - 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"b20gbXkgcXVlc3Rpb24gaGVyZToNCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL3BpcGVybWFp\n" - bC9saW51eC1zbnBzLWFyYy8yMDE3LVNlcHRlbWJlci8wMDI5MDAuaHRtbA0KDQotQWxleGV5 + "Hi Vladimir,\n" + "\n" + "On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote:\n" + "> On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote:\n" + "> > \n" + "> > Add option to set initial output frequency of plls via\n" + "> > \"clock-frequency\" property in pll's device tree node.\n" + "> > This frequency will be set while pll driver probed.\n" + "> > \n" + "> > The usage example is setting CPU clock frequency on boot\n" + "> > See discussion:\n" + "> > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c=DPL6\n" + "> > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29kVMLW\n" + "> > chYfhSGT2M&e=\n" + "> > \n" + "> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\n" + "> > ---\n" + "> > \302\240.../bindings/clock/snps,hsdk-pll-clock.txt\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2405 ++++\n" + "> > \302\240.../devicetree/bindings/clock/snps,pll-clock.txt\302\240\302\240\302\240|\302\240\302\2405 ++++\n" + "> > \302\240drivers/clk/axs10x/pll_clock.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 34 ++++++++++++++++++++--\n" + "> > \302\240drivers/clk/clk-hsdk-pll.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 34 ++++++++++++++++++++--\n" + "> > \302\2404 files changed, 74 insertions(+), 4 deletions(-)\n" + "> > \n" + "> > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > index c56c755..5703059 100644\n" + "> > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt\n" + "> > @@ -13,6 +13,10 @@ Required properties:\n" + "> > \302\240- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > \302\240- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > \302\240\n" + "> > +Optional properties:\n" + "> > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> > +while probing. Should be a single cell.\n" + "> > +\n" + "> > \302\240Example:\n" + "> > \302\240\tinput_clk: input-clk {\n" + "> > \302\240\t\tclock-frequency = <33333333>;\n" + "> > @@ -25,4 +29,5 @@ Example:\n" + "> > \302\240\t\treg = <0x00 0x10>;\n" + "> > \302\240\t\t#clock-cells = <0>;\n" + "> > \302\240\t\tclocks = <&input_clk>;\n" + "> > +\t\tclock-frequency = <1000000000>;\n" + "> > \302\240\t};\n" + "> > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > index 11fe487..5908f99 100644\n" + "> > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt\n" + "> > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register.\n" + "> > \302\240- clocks: shall be the input parent clock phandle for the PLL.\n" + "> > \302\240- #clock-cells: from common clock binding; Should always be set to 0.\n" + "> > \302\240\n" + "> > +Optional properties:\n" + "> > +- clock-frequency: output frequency generated by pll in Hz which will be set\n" + "> > +while probing. Should be a single cell.\n" + "> > +\n" + "> > \302\240Example:\n" + "> > \302\240\tinput-clk: input-clk {\n" + "> > \302\240\t\tclock-frequency = <33333333>;\n" + "> > @@ -25,4 +29,5 @@ Example:\n" + "> > \302\240\t\treg = <0x80 0x10>, <0x100 0x10>;\n" + "> > \302\240\t\t#clock-cells = <0>;\n" + "> > \302\240\t\tclocks = <&input-clk>;\n" + "> > +\t\tclock-frequency = <100000000>;\n" + "> > \302\240\t};\n" + "> \n" + "> You may check Documentation/devicetree/bindings/clock/clock-bindings.txt\n" + "> about how to assign initial clock rates, in general 'clock-frequency'\n" + "> property is a property of clock consumers with two exceptions of simple\n" + "> clock sources, namely it is used in fixed clock and PWM clock bindings.\n" + "\n" + "I think that's what we agreed on with Rob Herring back in the day.\n" + "Have you checked this post of him on the topic?\n" + "http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002909.html\n" + "\n" + "Just FYI it all started from my question here:\n" + "http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002900.html\n" + "\n" + -Alexey -478b96ac53d6452cf5ca6819987fabb6435acbce0b755a27bbf828dd0ab38866 +d95d658ce9b9a57245c3a1f7fb7f81ae1b6b6bfd09432f95b49c229f181c6a01
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