From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: [PATCH 6/8] drm/msm/adreno: Read the speed bins for a5xx targets Date: Tue, 21 Nov 2017 12:40:56 -0700 Message-ID: <1511293258-12415-7-git-send-email-jcrouse@codeaurora.org> References: <1511293258-12415-1-git-send-email-jcrouse@codeaurora.org> Return-path: Received: from smtp.codeaurora.org ([198.145.29.96]:48898 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751335AbdKUTlH (ORCPT ); Tue, 21 Nov 2017 14:41:07 -0500 In-Reply-To: <1511293258-12415-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: freedreno@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org Some 5xx based chipsets have different bins for GPU clock speeds. Read the fuses (if applicable) and set the appropriate OPP table. This will only work with OPP v2 tables - the bin will be ignored for legacy pwrlevel tables. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index a1f4eee..fdbe9e9 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include "msm_gem.h" #include "msm_mmu.h" #include "a5xx_gpu.h" @@ -1184,6 +1186,25 @@ static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu) .get_timestamp = a5xx_get_timestamp, }; +static void check_speed_bin(struct device *dev) +{ + struct nvmem_cell *cell; + u32 bin, val; + + cell = nvmem_cell_get(dev, "speed_bin"); + + /* If a nvmem cell isn't defined, nothing to do */ + if (IS_ERR(cell)) + return; + + bin = *((u32 *) nvmem_cell_read(cell, NULL)); + nvmem_cell_put(cell); + + val = (1 << bin); + + dev_pm_opp_set_supported_hw(dev, &val, 1); +} + struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -1210,6 +1231,8 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) a5xx_gpu->lm_leakage = 0x4E001A; + check_speed_bin(&pdev->dev); + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 4); if (ret) { a5xx_destroy(&(a5xx_gpu->base.base)); -- 1.9.1