From: Ravi Kumar <Ravi1.kumar@amd.com>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com
Subject: [PATCH v2 16/16] net/axgbe: add support for build 32-bit mode
Date: Fri, 5 Jan 2018 04:52:18 -0500 [thread overview]
Message-ID: <1515145938-97474-16-git-send-email-Ravi1.kumar@amd.com> (raw)
In-Reply-To: <1515145938-97474-1-git-send-email-Ravi1.kumar@amd.com>
Signed-off-by: Ravi Kumar <Ravi1.kumar@amd.com>
---
doc/guides/nics/features/axgbe.ini | 1 +
drivers/net/axgbe/axgbe_common.h | 49 ++++++++++++++++++++++----------------
drivers/net/axgbe/axgbe_ethdev.c | 10 ++++----
drivers/net/axgbe/axgbe_ethdev.h | 8 +++----
drivers/net/axgbe/axgbe_rxtx.c | 12 +++++-----
drivers/net/axgbe/axgbe_rxtx.h | 4 ++--
6 files changed, 48 insertions(+), 36 deletions(-)
diff --git a/doc/guides/nics/features/axgbe.ini b/doc/guides/nics/features/axgbe.ini
index 042ff1e..ab4da55 100644
--- a/doc/guides/nics/features/axgbe.ini
+++ b/doc/guides/nics/features/axgbe.ini
@@ -15,4 +15,5 @@ L3 checksum offload = Y
L4 checksum offload = Y
Basic stats = Y
Linux UIO = Y
+x86-32 = Y
x86-64 = Y
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 294f2e4..78a055d 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1507,7 +1507,7 @@ do { \
* register definitions formed using the input names
*/
#define AXGMAC_IOREAD(_pdata, _reg) \
- rte_read32((void *)((_pdata)->xgmac_regs + (_reg)))
+ rte_read32((void *)((uint8_t *)((_pdata)->xgmac_regs) + (_reg)))
#define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \
@@ -1515,7 +1515,8 @@ do { \
_reg##_##_field##_WIDTH)
#define AXGMAC_IOWRITE(_pdata, _reg, _val) \
- rte_write32((_val), (void *)((_pdata)->xgmac_regs + (_reg)))
+ rte_write32((_val), \
+ (void *)((uint8_t *)((_pdata)->xgmac_regs) + (_reg)))
#define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@ -1531,7 +1532,7 @@ do { \
* base register value is calculated by the queue or traffic class number
*/
#define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \
- rte_read32((void *)((_pdata)->xgmac_regs + \
+ rte_read32((void *)((uint8_t *)((_pdata)->xgmac_regs) + \
MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)))
#define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
@@ -1540,7 +1541,7 @@ do { \
_reg##_##_field##_WIDTH)
#define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
- rte_write32((_val), (void *)((_pdata)->xgmac_regs + \
+ rte_write32((_val), (void *)((uint8_t *)((_pdata)->xgmac_regs) +\
MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg)))
#define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
@@ -1557,7 +1558,7 @@ do { \
* base register value is obtained from the ring
*/
#define AXGMAC_DMA_IOREAD(_channel, _reg) \
- rte_read32((void *)((_channel)->dma_regs + (_reg)))
+ rte_read32((void *)((uint8_t *)((_channel)->dma_regs) + (_reg)))
#define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \
@@ -1565,7 +1566,8 @@ do { \
_reg##_##_field##_WIDTH)
#define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \
- rte_write32((_val), (void *)((_channel)->dma_regs + (_reg)))
+ rte_write32((_val), \
+ (void *)((uint8_t *)((_channel)->dma_regs) + (_reg)))
#define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
do { \
@@ -1590,16 +1592,18 @@ do { \
_prefix##_##_field##_WIDTH, (_val))
#define XPCS32_IOWRITE(_pdata, _off, _val) \
- rte_write32(_val, (void *)((_pdata)->xpcs_regs + (_off)))
+ rte_write32(_val, \
+ (void *)((uint8_t *)((_pdata)->xpcs_regs) + (_off)))
#define XPCS32_IOREAD(_pdata, _off) \
- rte_read32((void *)((_pdata)->xpcs_regs + (_off)))
+ rte_read32((void *)((uint8_t *)((_pdata)->xpcs_regs) + (_off)))
#define XPCS16_IOWRITE(_pdata, _off, _val) \
- rte_write16(_val, (void *)((_pdata)->xpcs_regs + (_off)))
+ rte_write16(_val, \
+ (void *)((uint8_t *)((_pdata)->xpcs_regs) + (_off)))
#define XPCS16_IOREAD(_pdata, _off) \
- rte_read16((void *)((_pdata)->xpcs_regs + (_off)))
+ rte_read16((void *)((uint8_t *)((_pdata)->xpcs_regs) + (_off)))
/* Macros for building, reading or writing register values or bits
* within the register values of SerDes integration registers.
@@ -1615,7 +1619,7 @@ do { \
_prefix##_##_field##_WIDTH, (_val))
#define XSIR0_IOREAD(_pdata, _reg) \
- rte_read16((void *)((_pdata)->sir0_regs + (_reg)))
+ rte_read16((void *)((uint8_t *)((_pdata)->sir0_regs) + (_reg)))
#define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
@@ -1623,7 +1627,8 @@ do { \
_reg##_##_field##_WIDTH)
#define XSIR0_IOWRITE(_pdata, _reg, _val) \
- rte_write16((_val), (void *)((_pdata)->sir0_regs + (_reg)))
+ rte_write16((_val), \
+ (void *)((uint8_t *)((_pdata)->sir0_regs) + (_reg)))
#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@ -1635,7 +1640,7 @@ do { \
} while (0)
#define XSIR1_IOREAD(_pdata, _reg) \
- rte_read16((void *)((_pdata)->sir1_regs + _reg))
+ rte_read16((void *)((uint8_t *)((_pdata)->sir1_regs) + _reg))
#define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
@@ -1643,7 +1648,8 @@ do { \
_reg##_##_field##_WIDTH)
#define XSIR1_IOWRITE(_pdata, _reg, _val) \
- rte_write16((_val), (void *)((_pdata)->sir1_regs + (_reg)))
+ rte_write16((_val), \
+ (void *)((uint8_t *)((_pdata)->sir1_regs) + (_reg)))
#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@ -1658,7 +1664,7 @@ do { \
* within the register values of SerDes RxTx registers.
*/
#define XRXTX_IOREAD(_pdata, _reg) \
- rte_read16((void *)((_pdata)->rxtx_regs + (_reg)))
+ rte_read16((void *)((uint8_t *)((_pdata)->rxtx_regs) + (_reg)))
#define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
@@ -1666,7 +1672,8 @@ do { \
_reg##_##_field##_WIDTH)
#define XRXTX_IOWRITE(_pdata, _reg, _val) \
- rte_write16((_val), (void *)((_pdata)->rxtx_regs + (_reg)))
+ rte_write16((_val), \
+ (void *)((uint8_t *)((_pdata)->rxtx_regs) + (_reg)))
#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@ -1691,7 +1698,7 @@ do { \
_prefix##_##_field##_WIDTH, (_val))
#define XP_IOREAD(_pdata, _reg) \
- rte_read32((void *)((_pdata)->xprop_regs + (_reg)))
+ rte_read32((void *)((uint8_t *)((_pdata)->xprop_regs) + (_reg)))
#define XP_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XP_IOREAD((_pdata), (_reg)), \
@@ -1699,7 +1706,8 @@ do { \
_reg##_##_field##_WIDTH)
#define XP_IOWRITE(_pdata, _reg, _val) \
- rte_write32((_val), (void *)((_pdata)->xprop_regs + (_reg)))
+ rte_write32((_val), \
+ (void *)((uint8_t *)((_pdata)->xprop_regs) + (_reg)))
#define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@ -1724,7 +1732,7 @@ do { \
_prefix##_##_field##_WIDTH, (_val))
#define XI2C_IOREAD(_pdata, _reg) \
- rte_read32((void *)((_pdata)->xi2c_regs + (_reg)))
+ rte_read32((void *)((uint8_t *)((_pdata)->xi2c_regs) + (_reg)))
#define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
@@ -1732,7 +1740,8 @@ do { \
_reg##_##_field##_WIDTH)
#define XI2C_IOWRITE(_pdata, _reg, _val) \
- rte_write32((_val), (void *)((_pdata)->xi2c_regs + (_reg)))
+ rte_write32((_val), \
+ (void *)((uint8_t *)((_pdata)->xi2c_regs) + (_reg)))
#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 9e5114b..d4d437a 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -712,10 +712,12 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
pdata->pci_dev = pci_dev;
pdata->xgmac_regs =
- (uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
- pdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET;
- pdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET;
- pdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
+ (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
+ pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs
+ + AXGBE_MAC_PROP_OFFSET);
+ pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs
+ + AXGBE_I2C_CTRL_OFFSET);
+ pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
/* version specific driver data*/
if (pci_dev->id.device_id == 0x1458)
diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
index 4091d1a..91260ca 100644
--- a/drivers/net/axgbe/axgbe_ethdev.h
+++ b/drivers/net/axgbe/axgbe_ethdev.h
@@ -567,10 +567,10 @@ struct axgbe_port {
struct axgbe_version_data *vdata;
/* AXGMAC/XPCS related mmio registers */
- uint64_t xgmac_regs; /* AXGMAC CSRs */
- uint64_t xpcs_regs; /* XPCS MMD registers */
- uint64_t xprop_regs; /* AXGBE property registers */
- uint64_t xi2c_regs; /* AXGBE I2C CSRs */
+ void *xgmac_regs; /* AXGMAC CSRs */
+ void *xpcs_regs; /* XPCS MMD registers */
+ void *xprop_regs; /* AXGBE property registers */
+ void *xi2c_regs; /* AXGBE I2C CSRs */
/* XPCS indirect addressing lock */
unsigned int xpcs_window_def_reg;
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index c616fc1..4c38e47 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -192,9 +192,9 @@ int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
rxq->queue_id = queue_idx;
rxq->port_id = dev->data->port_id;
rxq->nb_desc = rx_desc;
- rxq->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
- (DMA_CH_INC * rxq->queue_id);
- rxq->dma_tail_reg = (volatile uint32_t *)(rxq->dma_regs +
+ rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
+ (DMA_CH_INC * rxq->queue_id));
+ rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs +
DMA_CH_RDTR_LO);
rxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
@@ -509,9 +509,9 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
txq->desc = tz->addr;
txq->queue_id = queue_idx;
txq->port_id = dev->data->port_id;
- txq->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
- (DMA_CH_INC * txq->queue_id);
- txq->dma_tail_reg = (volatile uint32_t *)(txq->dma_regs +
+ txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE +
+ (DMA_CH_INC * txq->queue_id));
+ txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs +
DMA_CH_TDTR_LO);
txq->cur = 0;
txq->dirty = 0;
diff --git a/drivers/net/axgbe/axgbe_rxtx.h b/drivers/net/axgbe/axgbe_rxtx.h
index 45aaf89..e7b3cfd 100644
--- a/drivers/net/axgbe/axgbe_rxtx.h
+++ b/drivers/net/axgbe/axgbe_rxtx.h
@@ -202,7 +202,7 @@ struct axgbe_rx_queue {
/* Ring physical address */
uint64_t ring_phys_addr;
/* Dma Channel register address */
- uint64_t dma_regs;
+ void *dma_regs;
/* Dma channel tail register address*/
volatile uint32_t *dma_tail_reg;
/* DPDK queue index */
@@ -249,7 +249,7 @@ struct axgbe_tx_queue {
/* Physical address of ring */
uint64_t ring_phys_addr;
/* Dma channel register space */
- uint64_t dma_regs;
+ void *dma_regs;
/* Dma tail register address of ring*/
volatile uint32_t *dma_tail_reg;
/* Tx queue index/id*/
--
2.7.4
next prev parent reply other threads:[~2018-01-05 9:53 UTC|newest]
Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-30 13:10 [PATCH 01/16] net/axgbe: add minimal dev init and uninit support Ravi Kumar
2017-11-30 13:10 ` [PATCH 02/16] net/axgbe: add register map and related macros Ravi Kumar
2017-12-08 21:04 ` Ferruh Yigit
2017-12-11 7:20 ` Jianbo Liu
2017-11-30 13:10 ` [PATCH 03/16] net/axgbe: add phy register map and helper macros Ravi Kumar
2017-11-30 13:11 ` [PATCH 04/16] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2017-12-08 21:05 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 05/16] net/axgbe: add phy initialization and related apis Ravi Kumar
2017-11-30 13:11 ` [PATCH 06/16] net/axgbe: add phy programming apis Ravi Kumar
2017-11-30 13:11 ` [PATCH 07/16] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2017-12-08 21:06 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 08/16] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2017-11-30 13:11 ` [PATCH 09/16] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2017-12-08 21:07 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 10/16] net/axgbe: add transmit and receive data path apis Ravi Kumar
2017-12-08 21:08 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 11/16] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2017-11-30 13:11 ` [PATCH 12/16] net/axgbe: add promiscuous mode support Ravi Kumar
2017-12-08 21:08 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 13/16] net/axgbe: add generic transmit and receive stats support Ravi Kumar
2017-11-30 13:11 ` [PATCH 14/16] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2017-12-08 21:09 ` Ferruh Yigit
2017-11-30 13:11 ` [PATCH 15/16] net/axgbe: add support for icc and clang build Ravi Kumar
2017-11-30 13:11 ` [PATCH 16/16] net/axgbe: add support for build 32-bit mode Ravi Kumar
2017-12-08 21:10 ` Ferruh Yigit
2017-12-05 0:25 ` [PATCH 01/16] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2017-12-08 21:04 ` Ferruh Yigit
2017-12-09 13:18 ` Kumar, Ravi1
2018-01-05 9:52 ` [PATCH v2 " Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 02/16] net/axgbe: add register map and related macros Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 03/16] net/axgbe: add phy register map and helper macros Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 04/16] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 05/16] net/axgbe: add phy initialization and related apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 06/16] net/axgbe: add phy programming apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 07/16] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 08/16] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 09/16] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 10/16] net/axgbe: add transmit and receive data path apis Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 11/16] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2018-01-05 20:33 ` Stephen Hemminger
2018-01-08 5:40 ` Kumar, Ravi1
2018-01-15 14:51 ` Kovacevic, Marko
2018-01-05 9:52 ` [PATCH v2 12/16] net/axgbe: add link status update Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 13/16] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 14/16] net/axgbe: add promiscuous mode support Ravi Kumar
2018-01-05 9:52 ` [PATCH v2 15/16] net/axgbe: add generic transmit and receive status support Ravi Kumar
2018-01-05 9:52 ` Ravi Kumar [this message]
2018-01-05 20:32 ` [PATCH v2 16/16] net/axgbe: add support for build 32-bit mode Stephen Hemminger
2018-01-09 20:17 ` [PATCH v2 01/16] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2018-01-11 6:42 ` Kumar, Ravi1
2018-03-09 8:42 ` [PATCH v3 01/18] " Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 02/18] net/axgbe: add register map and related macros Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 03/18] net/axgbe: add phy register map and helper macros Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 04/18] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2018-03-16 17:43 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 05/18] net/axgbe: add phy initialization and related apis Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 06/18] net/axgbe: add phy programming apis Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 07/18] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 08/18] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2018-03-16 17:44 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 09/18] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 10/18] net/axgbe: add transmit and receive data path apis Ravi Kumar
2018-03-16 17:45 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 11/18] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2018-03-16 17:46 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 12/18] net/axgbe: add link status update Ravi Kumar
2018-03-16 17:46 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 13/18] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 14/18] net/axgbe: add promiscuous mode support Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 15/18] net/axgbe: add generic transmit and receive stats support Ravi Kumar
2018-03-16 17:47 ` Ferruh Yigit
2018-03-09 8:42 ` [PATCH v3 16/18] net/axgbe: add support for build 32-bit mode Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 17/18] net/axgbe: add workaround for axgbe ethernet training bug Ravi Kumar
2018-03-09 8:42 ` [PATCH v3 18/18] net/axgbe: moved license headers to SPDX format Ravi Kumar
2018-03-11 23:31 ` Stephen Hemminger
2018-03-12 11:23 ` Kumar, Ravi1
2018-03-09 16:13 ` [PATCH v3 01/18] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2018-03-09 16:39 ` Ferruh Yigit
2018-03-12 11:25 ` Kumar, Ravi1
2018-03-16 17:42 ` Ferruh Yigit
2018-03-19 12:33 ` Kumar, Ravi1
2018-04-03 12:21 ` Ferruh Yigit
2018-04-05 6:39 ` [PATCH v4 01/17] " Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 02/17] net/axgbe: add register map and related macros Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 03/17] net/axgbe: add phy register map and helper macros Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 04/17] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 05/17] net/axgbe: add phy initialization and related apis Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 06/17] net/axgbe: add phy programming apis Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 07/17] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 08/17] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 09/17] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 10/17] net/axgbe: add transmit and receive data path apis Ravi Kumar
2018-04-05 11:34 ` Ferruh Yigit
2018-04-06 12:40 ` Kumar, Ravi1
2018-04-05 6:39 ` [PATCH v4 11/17] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 12/17] net/axgbe: add link status update Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 13/17] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 14/17] net/axgbe: add promiscuous mode support Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 15/17] net/axgbe: support generic transmit and receive stats api Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 16/17] net/axgbe: add support for build 32-bit mode Ravi Kumar
2018-04-05 6:39 ` [PATCH v4 17/17] net/axgbe: add workaround for axgbe ethernet training bug Ravi Kumar
2018-04-05 11:35 ` Ferruh Yigit
2018-04-06 12:41 ` Kumar, Ravi1
2018-04-05 11:34 ` [PATCH v4 01/17] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2018-04-06 12:39 ` Kumar, Ravi1
2018-04-06 12:36 ` [PATCH v5 01/18] " Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 02/18] net/axgbe: add register map and related macros Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 03/18] net/axgbe: add phy register map and helper macros Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 04/18] net/axgbe: add structures for MAC initialization and reset Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 05/18] net/axgbe: add phy initialization and related apis Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 06/18] net/axgbe: add phy programming apis Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 07/18] net/axgbe: add interrupt handler for autonegotiation Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 08/18] net/axgbe: add transmit and receive queue setup apis Ravi Kumar
2018-04-09 4:49 ` Rosen, Rami
2018-04-09 12:30 ` Ferruh Yigit
2018-04-06 12:36 ` [PATCH v5 09/18] net/axgbe: add DMA programming and dev start and stop apis Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 10/18] net/axgbe: add transmit and receive data path apis Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 11/18] doc: add documents for AMD axgbe Ethernet PMD Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 12/18] net/axgbe: add link status update Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 13/18] net/axgbe: add configure flow control while link adjustment Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 14/18] net/axgbe: add promiscuous mode support Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 15/18] net/axgbe: support generic transmit and receive stats api Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 16/18] net/axgbe: add support for build 32-bit mode Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 17/18] net/axgbe: add workaround for axgbe ethernet training bug Ravi Kumar
2018-04-06 12:36 ` [PATCH v5 18/18] net/axgbe : support meson build Ravi Kumar
2018-04-06 15:55 ` [PATCH v5 01/18] net/axgbe: add minimal dev init and uninit support Ferruh Yigit
2018-04-09 6:00 ` Kumar, Ravi1
2018-11-22 14:39 ` Ferruh Yigit
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