From mboxrd@z Thu Jan 1 00:00:00 1970 From: jbrunet@baylibre.com (Jerome Brunet) Date: Mon, 15 Jan 2018 12:50:31 +0100 Subject: [RFT net-next v4 5/5] net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock In-Reply-To: <20180114214858.7217-6-martin.blumenstingl@googlemail.com> References: <20180114214858.7217-1-martin.blumenstingl@googlemail.com> <20180114214858.7217-6-martin.blumenstingl@googlemail.com> Message-ID: <1516017031.2608.17.camel@baylibre.com> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org On Sun, 2018-01-14 at 22:48 +0100, Martin Blumenstingl wrote: > On Meson8b the only valid input clock is MPLL2. The bootloader > configures that to run at 500002394Hz which cannot be divided evenly > down to 125MHz using the m250_div clock. Currently the common clock > framework chooses a m250_div of 2 - with the internal fixed > "divide by 10" this results in a RGMII TX clock of 125001197Hz (120Hz > above the requested 125MHz). > > Letting the common clock framework propagate the rate changes up to the > parent of m250_mux allows us to get the best possible clock rate. With > this patch the common clock framework calculates a rate of > very-close-to-250MHz (249999701Hz to be exact) for the MPLL2 clock > (which is the mux input). Dividing that by 2 (which is an internal, > fixed divider for the RGMII TX clock) gives us an RGMII TX clock of > 124999850Hz (which is only 150Hz off the requested 125MHz, compared to > 1197Hz based on the MPLL2 rate set by u-boot and the Amlogic GPL kernel > sources). > > SoCs from the Meson GX series are not affected by this change because > the input clock is FCLK_DIV2 whose rate cannot be changed (which is fine > since it's running at 1GHz, so it's already a multiple of 250MHz and > 125MHz). > > Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") > Suggested-by: Jerome Brunet > Signed-off-by: Martin Blumenstingl Reviewed-by: Jerome Brunet From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerome Brunet Subject: Re: [RFT net-next v4 5/5] net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock Date: Mon, 15 Jan 2018 12:50:31 +0100 Message-ID: <1516017031.2608.17.camel@baylibre.com> References: <20180114214858.7217-1-martin.blumenstingl@googlemail.com> <20180114214858.7217-6-martin.blumenstingl@googlemail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Cc: linus.luessing@c0d3.blue, khilman@baylibre.com, linux-amlogic@lists.infradead.org, narmstrong@baylibre.com, peppe.cavallaro@st.com, alexandre.torgue@st.com To: Martin Blumenstingl , netdev@vger.kernel.org, ingrassia@epigenesys.com Return-path: Received: from mail-wr0-f195.google.com ([209.85.128.195]:38642 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932903AbeAOLue (ORCPT ); Mon, 15 Jan 2018 06:50:34 -0500 Received: by mail-wr0-f195.google.com with SMTP id x1so7187167wrb.5 for ; Mon, 15 Jan 2018 03:50:34 -0800 (PST) In-Reply-To: <20180114214858.7217-6-martin.blumenstingl@googlemail.com> Sender: netdev-owner@vger.kernel.org List-ID: On Sun, 2018-01-14 at 22:48 +0100, Martin Blumenstingl wrote: > On Meson8b the only valid input clock is MPLL2. The bootloader > configures that to run at 500002394Hz which cannot be divided evenly > down to 125MHz using the m250_div clock. Currently the common clock > framework chooses a m250_div of 2 - with the internal fixed > "divide by 10" this results in a RGMII TX clock of 125001197Hz (120Hz > above the requested 125MHz). > > Letting the common clock framework propagate the rate changes up to the > parent of m250_mux allows us to get the best possible clock rate. With > this patch the common clock framework calculates a rate of > very-close-to-250MHz (249999701Hz to be exact) for the MPLL2 clock > (which is the mux input). Dividing that by 2 (which is an internal, > fixed divider for the RGMII TX clock) gives us an RGMII TX clock of > 124999850Hz (which is only 150Hz off the requested 125MHz, compared to > 1197Hz based on the MPLL2 rate set by u-boot and the Amlogic GPL kernel > sources). > > SoCs from the Meson GX series are not affected by this change because > the input clock is FCLK_DIV2 whose rate cannot be changed (which is fine > since it's running at 1GHz, so it's already a multiple of 250MHz and > 125MHz). > > Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") > Suggested-by: Jerome Brunet > Signed-off-by: Martin Blumenstingl Reviewed-by: Jerome Brunet