diff for duplicates of <1516175133.4383.3.camel@analog.com> diff --git a/a/1.txt b/N1/1.txt index 06a6db9..b5bbdf2 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,56 +1,96 @@ -T24gU3VuLCAyMDE4LTAxLTE0IGF0IDEyOjM3ICswMDAwLCBKb25hdGhhbiBDYW1lcm9uIHdyb3Rl -Og0KPiBPbiBXZWQsIDEwIEphbiAyMDE4IDEzOjI5OjU0ICswMjAwDQo+IDxhbGV4YW5kcnUuYXJk -ZWxlYW5AYW5hbG9nLmNvbT4gd3JvdGU6DQo+IA0KPiA+IEZyb206IEFsZXhhbmRydSBBcmRlbGVh -biA8YWxleGFuZHJ1LmFyZGVsZWFuQGFuYWxvZy5jb20+DQo+ID4gDQo+ID4gQWNjb3JkaW5nIHRv -IHRoZSBkYXRhc2hlZXQ6DQo+ID4gKiAwIC0gZXh0ZXJuYWwgY3J5c3RhbCwgY29ubmVjdGVkIGZy -b20gcGluIE1DTEsxIHRvIE1DTEsyDQo+IA0KPiBXaGF0IGZyZXF1ZW5jeSBvZiBjcnlzdGFsPyAg -TXkgcXVpY2sgcmVhZCBvZiB0aGUgZGF0YXNoZWV0DQo+IGltcGxpZXMgdGhpcyBtYXkgYmUgZmxl -eGlibGUuICBQb3NzaWJseSBhcyBmbGV4aWJsZSBhcw0KPiB0aGUgY2xvY2sgb3B0aW9uLi4uDQoN -CkkgdGhpbmsgeW91J3JlIHJpZ2h0IGFib3V0IHRoaXMuDQpXaWxsIHJlLXZpc2l0IHRoaXMuDQoN -CklzIGl0IG9rIGlmIEkgcmUtc3BpbiB0aGlzIGFzIGEgc3RhbmRhbG9uZSBwYXRjaCA/DQoNClNp -bmNlIEknbSBuZXcgYXJvdW5kIGhlcmUsIG1heWJlIGl0IHdvdWxkIHByb2JhYmx5IGJlIGdvb2Qg -dG8gdHJ5IHRvDQpzZW5kIG9uZSBwYXRjaCBhdCBhIHRpbWUgYW5kIHJlc29sdmUgc3luY2hyb25p -emF0aW9uIFtiZXR3ZWVuIHdoYXQgSQ0KZGVsaXZlciB2cyByZWNvbW1lbmRlZCB3YXlzIG9mIGRv -aW5nIHRoaW5nc10uDQoNCj4gDQo+IA0KPiA+ICogMSAtIGV4dGVybmFsIGNsb2NrLCBhcHBsaWVk -IHRvIE1DTEsyIHBpbg0KPiA+ICogMiAtIGludGVybmFsIDQuOTIgTWh6IGNsb2NrOyBwaW4gTUNM -SzIgaXMgdHJpc3RhdGVkDQo+ID4gKiAzIC0gaW50ZXJuYWwgNC45MiBNaHogY2xvY2s7IGludGVy -bmFsIGNsb2NrIGlzIGF2YWlsYWJsZSBvbiBNQ0xLMg0KPiA+IA0KPiA+IFdoaWNoIG1lYW5zIHRo -YXQgdGhlIGV4dGVybmFsIGNsb2NrIHZhbHVlIG9ubHkgaGFzIHNlbnNlDQo+ID4gZm9yIHZhbHVl -IDEgKEFENzE5Ml9DTEtfRVhUX01DTEsyKS4NCj4gPiANCj4gPiBBbHNvIGFkZGVkIHJhbmdlIHZh -bGlkYXRpb24gZm9yIHRoZSBleHRlcm5hbCBmcmVxdWVuY3kNCj4gPiBzZXR0aW5nLCB3aGljaCB0 -aGUgZGF0YXNoZWV0IG1lbnRpb25zIHRoYXQgaXQncw0KPiA+IGJldHdlZW4gMi40NTc2IGFuZCA1 -LjEyIE1oei4NCj4gPiANCj4gPiBTaWduZWQtb2ZmLWJ5OiBBbGV4YW5kcnUgQXJkZWxlYW4gPGFs -ZXhhbmRydS5hcmRlbGVhbkBhbmFsb2cuY29tPg0KPiA+IC0tLQ0KPiA+ICBkcml2ZXJzL3N0YWdp -bmcvaWlvL2FkYy9hZDcxOTIuYyB8IDIyICsrKysrKysrKysrKysrKy0tLS0tLS0NCj4gPiAgMSBm -aWxlIGNoYW5nZWQsIDE1IGluc2VydGlvbnMoKyksIDcgZGVsZXRpb25zKC0pDQo+ID4gDQo+ID4g -ZGlmZiAtLWdpdCBhL2RyaXZlcnMvc3RhZ2luZy9paW8vYWRjL2FkNzE5Mi5jDQo+ID4gYi9kcml2 -ZXJzL3N0YWdpbmcvaWlvL2FkYy9hZDcxOTIuYw0KPiA+IGluZGV4IDdmMjA0MDEzZDZkNC4uN2Jj -MDQxMDFkMTMzIDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvc3RhZ2luZy9paW8vYWRjL2FkNzE5 -Mi5jDQo+ID4gKysrIGIvZHJpdmVycy9zdGFnaW5nL2lpby9hZGMvYWQ3MTkyLmMNCj4gPiBAQCAt -MTQxLDYgKzE0MSw4IEBADQo+ID4gICNkZWZpbmUgQUQ3MTkyX0dQT0NPTl9QMURBVAlCSVQoMSkg -LyogUDEgc3RhdGUgKi8NCj4gPiAgI2RlZmluZSBBRDcxOTJfR1BPQ09OX1AwREFUCUJJVCgwKSAv -KiBQMCBzdGF0ZSAqLw0KPiA+ICANCj4gPiArI2RlZmluZSBBRDcxOTJfRVhUX0ZSRVFfTUhaX01J -TgkyNDU3NjAwDQo+ID4gKyNkZWZpbmUgQUQ3MTkyX0VYVF9GUkVRX01IWl9NQVgJNTEyMDAwMA0K -PiA+ICAjZGVmaW5lIEFENzE5Ml9JTlRfRlJFUV9NSFoJNDkxNTIwMA0KPiA+ICANCj4gPiAgLyog -Tk9URToNCj4gPiBAQCAtMjE3LDYgKzIxOSwxMiBAQCBzdGF0aWMgaW50IGFkNzE5Ml9jYWxpYnJh -dGVfYWxsKHN0cnVjdA0KPiA+IGFkNzE5Ml9zdGF0ZSAqc3QpDQo+ID4gIAkJCQlBUlJBWV9TSVpF -KGFkNzE5Ml9jYWxpYl9hcnIpKTsNCj4gPiAgfQ0KPiA+ICANCj4gPiArc3RhdGljIGlubGluZSBi -b29sIGFkNzE5Ml92YWxpZF9leHRlcm5hbF9mcmVxdWVuY3kodTMyIGZyZXEpDQo+ID4gK3sNCj4g -PiArCXJldHVybiAoZnJlcSA+PSBBRDcxOTJfRVhUX0ZSRVFfTUhaX01JTiAmJg0KPiA+ICsJCWZy -ZXEgPD0gQUQ3MTkyX0VYVF9GUkVRX01IWl9NQVgpOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICBzdGF0 -aWMgaW50IGFkNzE5Ml9zZXR1cChzdHJ1Y3QgYWQ3MTkyX3N0YXRlICpzdCwNCj4gPiAgCQkJY29u -c3Qgc3RydWN0IGFkNzE5Ml9wbGF0Zm9ybV9kYXRhICpwZGF0YSkNCj4gPiAgew0KPiA+IEBAIC0y -NDUsMTYgKzI1MywxNiBAQCBzdGF0aWMgaW50IGFkNzE5Ml9zZXR1cChzdHJ1Y3QgYWQ3MTkyX3N0 -YXRlDQo+ID4gKnN0LA0KPiA+ICANCj4gPiAgCXN3aXRjaCAocGRhdGEtPmNsb2NrX3NvdXJjZV9z -ZWwpIHsNCj4gPiAgCWNhc2UgQUQ3MTkyX0NMS19FWFRfTUNMSzFfMjoNCj4gPiAtCWNhc2UgQUQ3 -MTkyX0NMS19FWFRfTUNMSzI6DQo+ID4gLQkJc3QtPm1jbGsgPSBBRDcxOTJfSU5UX0ZSRVFfTUha -Ow0KPiA+IC0JCWJyZWFrOw0KPiA+ICAJY2FzZSBBRDcxOTJfQ0xLX0lOVDoNCj4gPiAgCWNhc2Ug -QUQ3MTkyX0NMS19JTlRfQ086DQo+ID4gLQkJaWYgKHBkYXRhLT5leHRfY2xrX2h6KQ0KPiA+IC0J -CQlzdC0+bWNsayA9IHBkYXRhLT5leHRfY2xrX2h6Ow0KPiA+IC0JCWVsc2UNCj4gPiAtCQkJc3Qt -Pm1jbGsgPSBBRDcxOTJfSU5UX0ZSRVFfTUhaOw0KPiA+ICsJCXN0LT5tY2xrID0gQUQ3MTkyX0lO -VF9GUkVRX01IWjsNCj4gPiAgCQlicmVhazsNCj4gPiArCWNhc2UgQUQ3MTkyX0NMS19FWFRfTUNM -SzI6DQo+ID4gKwkJaWYgKGFkNzE5Ml92YWxpZF9leHRlcm5hbF9mcmVxdWVuY3kocGRhdGEtDQo+ -ID4gPmNsb2NrX3NvdXJjZV9zZWwpKSB7DQo+ID4gKwkJCXN0LT5tY2xrID0gcGRhdGEtPmNsb2Nr -X3NvdXJjZV9zZWw7DQo+ID4gKwkJCWJyZWFrOw0KPiA+ICsJCX0NCj4gPiArCQkvKiBGQUxMVEhS -T1VHSCAqLw0KPiA+ICAJZGVmYXVsdDoNCj4gPiAgCQlyZXQgPSAtRUlOVkFMOw0KPiA+ICAJCWdv -dG8gb3V0Ow0KPiANCj4g +On Sun, 2018-01-14 at 12:37 +0000, Jonathan Cameron wrote: +> On Wed, 10 Jan 2018 13:29:54 +0200 +> <alexandru.ardelean@analog.com> wrote: +> +> > From: Alexandru Ardelean <alexandru.ardelean@analog.com> +> > +> > According to the datasheet: +> > * 0 - external crystal, connected from pin MCLK1 to MCLK2 +> +> What frequency of crystal? My quick read of the datasheet +> implies this may be flexible. Possibly as flexible as +> the clock option... + +I think you're right about this. +Will re-visit this. + +Is it ok if I re-spin this as a standalone patch ? + +Since I'm new around here, maybe it would probably be good to try to +send one patch at a time and resolve synchronization [between what I +deliver vs recommended ways of doing things]. + +> +> +> > * 1 - external clock, applied to MCLK2 pin +> > * 2 - internal 4.92 Mhz clock; pin MCLK2 is tristated +> > * 3 - internal 4.92 Mhz clock; internal clock is available on MCLK2 +> > +> > Which means that the external clock value only has sense +> > for value 1 (AD7192_CLK_EXT_MCLK2). +> > +> > Also added range validation for the external frequency +> > setting, which the datasheet mentions that it's +> > between 2.4576 and 5.12 Mhz. +> > +> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> +> > --- +> > drivers/staging/iio/adc/ad7192.c | 22 +++++++++++++++------- +> > 1 file changed, 15 insertions(+), 7 deletions(-) +> > +> > diff --git a/drivers/staging/iio/adc/ad7192.c +> > b/drivers/staging/iio/adc/ad7192.c +> > index 7f204013d6d4..7bc04101d133 100644 +> > --- a/drivers/staging/iio/adc/ad7192.c +> > +++ b/drivers/staging/iio/adc/ad7192.c +> > @@ -141,6 +141,8 @@ +> > #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */ +> > #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */ +> > +> > +#define AD7192_EXT_FREQ_MHZ_MIN 2457600 +> > +#define AD7192_EXT_FREQ_MHZ_MAX 5120000 +> > #define AD7192_INT_FREQ_MHZ 4915200 +> > +> > /* NOTE: +> > @@ -217,6 +219,12 @@ static int ad7192_calibrate_all(struct +> > ad7192_state *st) +> > ARRAY_SIZE(ad7192_calib_arr)); +> > } +> > +> > +static inline bool ad7192_valid_external_frequency(u32 freq) +> > +{ +> > + return (freq >= AD7192_EXT_FREQ_MHZ_MIN && +> > + freq <= AD7192_EXT_FREQ_MHZ_MAX); +> > +} +> > + +> > static int ad7192_setup(struct ad7192_state *st, +> > const struct ad7192_platform_data *pdata) +> > { +> > @@ -245,16 +253,16 @@ static int ad7192_setup(struct ad7192_state +> > *st, +> > +> > switch (pdata->clock_source_sel) { +> > case AD7192_CLK_EXT_MCLK1_2: +> > - case AD7192_CLK_EXT_MCLK2: +> > - st->mclk = AD7192_INT_FREQ_MHZ; +> > - break; +> > case AD7192_CLK_INT: +> > case AD7192_CLK_INT_CO: +> > - if (pdata->ext_clk_hz) +> > - st->mclk = pdata->ext_clk_hz; +> > - else +> > - st->mclk = AD7192_INT_FREQ_MHZ; +> > + st->mclk = AD7192_INT_FREQ_MHZ; +> > break; +> > + case AD7192_CLK_EXT_MCLK2: +> > + if (ad7192_valid_external_frequency(pdata- +> > >clock_source_sel)) { +> > + st->mclk = pdata->clock_source_sel; +> > + break; +> > + } +> > + /* FALLTHROUGH */ +> > default: +> > ret = -EINVAL; +> > goto out; +> +> diff --git a/a/content_digest b/N1/content_digest index 41bdac1..a56cca8 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,72 +1,112 @@ "ref\020180110112956.23931-1-alexandru.ardelean@analog.com\0" "ref\020180114123745.7a1180ca@archlinux\0" - "From\0Ardelean, Alexandru <alexandru.Ardelean@analog.com>\0" + "From\0Ardelean, Alexandru <alexandru.Ardelean-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org>\0" "Subject\0Re: [PATCH 1/3] staging: iio: adc: ad7192: fix external frequency setting\0" "Date\0Wed, 17 Jan 2018 07:45:35 +0000\0" - "To\0jic23@jic23.retrosnub.co.uk <jic23@jic23.retrosnub.co.uk>\0" - "Cc\0mark.rutland@arm.com <mark.rutland@arm.com>" - linux-iio@vger.kernel.org <linux-iio@vger.kernel.org> + "To\0jic23-tko9wxEg+fIOOJlXag/Snyp2UmYkHbXO@public.gmane.org <jic23-tko9wxEg+fIOOJlXag/Snyp2UmYkHbXO@public.gmane.org>\0" + "Cc\0mark.rutland-5wv7dgnIgG8@public.gmane.org <mark.rutland-5wv7dgnIgG8@public.gmane.org>" + linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> Hennerich - Michael <Michael.Hennerich@analog.com> - robh+dt@kernel.org <robh+dt@kernel.org> - " devicetree@vger.kernel.org <devicetree@vger.kernel.org>\0" + Michael <Michael.Hennerich-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org> + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>\0" "\00:1\0" "b\0" - "T24gU3VuLCAyMDE4LTAxLTE0IGF0IDEyOjM3ICswMDAwLCBKb25hdGhhbiBDYW1lcm9uIHdyb3Rl\n" - "Og0KPiBPbiBXZWQsIDEwIEphbiAyMDE4IDEzOjI5OjU0ICswMjAwDQo+IDxhbGV4YW5kcnUuYXJk\n" - "ZWxlYW5AYW5hbG9nLmNvbT4gd3JvdGU6DQo+IA0KPiA+IEZyb206IEFsZXhhbmRydSBBcmRlbGVh\n" - "biA8YWxleGFuZHJ1LmFyZGVsZWFuQGFuYWxvZy5jb20+DQo+ID4gDQo+ID4gQWNjb3JkaW5nIHRv\n" - "IHRoZSBkYXRhc2hlZXQ6DQo+ID4gKiAwIC0gZXh0ZXJuYWwgY3J5c3RhbCwgY29ubmVjdGVkIGZy\n" - "b20gcGluIE1DTEsxIHRvIE1DTEsyDQo+IA0KPiBXaGF0IGZyZXF1ZW5jeSBvZiBjcnlzdGFsPyAg\n" - "TXkgcXVpY2sgcmVhZCBvZiB0aGUgZGF0YXNoZWV0DQo+IGltcGxpZXMgdGhpcyBtYXkgYmUgZmxl\n" - "eGlibGUuICBQb3NzaWJseSBhcyBmbGV4aWJsZSBhcw0KPiB0aGUgY2xvY2sgb3B0aW9uLi4uDQoN\n" - "CkkgdGhpbmsgeW91J3JlIHJpZ2h0IGFib3V0IHRoaXMuDQpXaWxsIHJlLXZpc2l0IHRoaXMuDQoN\n" - "CklzIGl0IG9rIGlmIEkgcmUtc3BpbiB0aGlzIGFzIGEgc3RhbmRhbG9uZSBwYXRjaCA/DQoNClNp\n" - "bmNlIEknbSBuZXcgYXJvdW5kIGhlcmUsIG1heWJlIGl0IHdvdWxkIHByb2JhYmx5IGJlIGdvb2Qg\n" - "dG8gdHJ5IHRvDQpzZW5kIG9uZSBwYXRjaCBhdCBhIHRpbWUgYW5kIHJlc29sdmUgc3luY2hyb25p\n" - "emF0aW9uIFtiZXR3ZWVuIHdoYXQgSQ0KZGVsaXZlciB2cyByZWNvbW1lbmRlZCB3YXlzIG9mIGRv\n" - "aW5nIHRoaW5nc10uDQoNCj4gDQo+IA0KPiA+ICogMSAtIGV4dGVybmFsIGNsb2NrLCBhcHBsaWVk\n" - "IHRvIE1DTEsyIHBpbg0KPiA+ICogMiAtIGludGVybmFsIDQuOTIgTWh6IGNsb2NrOyBwaW4gTUNM\n" - "SzIgaXMgdHJpc3RhdGVkDQo+ID4gKiAzIC0gaW50ZXJuYWwgNC45MiBNaHogY2xvY2s7IGludGVy\n" - "bmFsIGNsb2NrIGlzIGF2YWlsYWJsZSBvbiBNQ0xLMg0KPiA+IA0KPiA+IFdoaWNoIG1lYW5zIHRo\n" - "YXQgdGhlIGV4dGVybmFsIGNsb2NrIHZhbHVlIG9ubHkgaGFzIHNlbnNlDQo+ID4gZm9yIHZhbHVl\n" - "IDEgKEFENzE5Ml9DTEtfRVhUX01DTEsyKS4NCj4gPiANCj4gPiBBbHNvIGFkZGVkIHJhbmdlIHZh\n" - "bGlkYXRpb24gZm9yIHRoZSBleHRlcm5hbCBmcmVxdWVuY3kNCj4gPiBzZXR0aW5nLCB3aGljaCB0\n" - "aGUgZGF0YXNoZWV0IG1lbnRpb25zIHRoYXQgaXQncw0KPiA+IGJldHdlZW4gMi40NTc2IGFuZCA1\n" - "LjEyIE1oei4NCj4gPiANCj4gPiBTaWduZWQtb2ZmLWJ5OiBBbGV4YW5kcnUgQXJkZWxlYW4gPGFs\n" - "ZXhhbmRydS5hcmRlbGVhbkBhbmFsb2cuY29tPg0KPiA+IC0tLQ0KPiA+ICBkcml2ZXJzL3N0YWdp\n" - "bmcvaWlvL2FkYy9hZDcxOTIuYyB8IDIyICsrKysrKysrKysrKysrKy0tLS0tLS0NCj4gPiAgMSBm\n" - "aWxlIGNoYW5nZWQsIDE1IGluc2VydGlvbnMoKyksIDcgZGVsZXRpb25zKC0pDQo+ID4gDQo+ID4g\n" - "ZGlmZiAtLWdpdCBhL2RyaXZlcnMvc3RhZ2luZy9paW8vYWRjL2FkNzE5Mi5jDQo+ID4gYi9kcml2\n" - "ZXJzL3N0YWdpbmcvaWlvL2FkYy9hZDcxOTIuYw0KPiA+IGluZGV4IDdmMjA0MDEzZDZkNC4uN2Jj\n" - "MDQxMDFkMTMzIDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvc3RhZ2luZy9paW8vYWRjL2FkNzE5\n" - "Mi5jDQo+ID4gKysrIGIvZHJpdmVycy9zdGFnaW5nL2lpby9hZGMvYWQ3MTkyLmMNCj4gPiBAQCAt\n" - "MTQxLDYgKzE0MSw4IEBADQo+ID4gICNkZWZpbmUgQUQ3MTkyX0dQT0NPTl9QMURBVAlCSVQoMSkg\n" - "LyogUDEgc3RhdGUgKi8NCj4gPiAgI2RlZmluZSBBRDcxOTJfR1BPQ09OX1AwREFUCUJJVCgwKSAv\n" - "KiBQMCBzdGF0ZSAqLw0KPiA+ICANCj4gPiArI2RlZmluZSBBRDcxOTJfRVhUX0ZSRVFfTUhaX01J\n" - "TgkyNDU3NjAwDQo+ID4gKyNkZWZpbmUgQUQ3MTkyX0VYVF9GUkVRX01IWl9NQVgJNTEyMDAwMA0K\n" - "PiA+ICAjZGVmaW5lIEFENzE5Ml9JTlRfRlJFUV9NSFoJNDkxNTIwMA0KPiA+ICANCj4gPiAgLyog\n" - "Tk9URToNCj4gPiBAQCAtMjE3LDYgKzIxOSwxMiBAQCBzdGF0aWMgaW50IGFkNzE5Ml9jYWxpYnJh\n" - "dGVfYWxsKHN0cnVjdA0KPiA+IGFkNzE5Ml9zdGF0ZSAqc3QpDQo+ID4gIAkJCQlBUlJBWV9TSVpF\n" - "KGFkNzE5Ml9jYWxpYl9hcnIpKTsNCj4gPiAgfQ0KPiA+ICANCj4gPiArc3RhdGljIGlubGluZSBi\n" - "b29sIGFkNzE5Ml92YWxpZF9leHRlcm5hbF9mcmVxdWVuY3kodTMyIGZyZXEpDQo+ID4gK3sNCj4g\n" - "PiArCXJldHVybiAoZnJlcSA+PSBBRDcxOTJfRVhUX0ZSRVFfTUhaX01JTiAmJg0KPiA+ICsJCWZy\n" - "ZXEgPD0gQUQ3MTkyX0VYVF9GUkVRX01IWl9NQVgpOw0KPiA+ICt9DQo+ID4gKw0KPiA+ICBzdGF0\n" - "aWMgaW50IGFkNzE5Ml9zZXR1cChzdHJ1Y3QgYWQ3MTkyX3N0YXRlICpzdCwNCj4gPiAgCQkJY29u\n" - "c3Qgc3RydWN0IGFkNzE5Ml9wbGF0Zm9ybV9kYXRhICpwZGF0YSkNCj4gPiAgew0KPiA+IEBAIC0y\n" - "NDUsMTYgKzI1MywxNiBAQCBzdGF0aWMgaW50IGFkNzE5Ml9zZXR1cChzdHJ1Y3QgYWQ3MTkyX3N0\n" - "YXRlDQo+ID4gKnN0LA0KPiA+ICANCj4gPiAgCXN3aXRjaCAocGRhdGEtPmNsb2NrX3NvdXJjZV9z\n" - "ZWwpIHsNCj4gPiAgCWNhc2UgQUQ3MTkyX0NMS19FWFRfTUNMSzFfMjoNCj4gPiAtCWNhc2UgQUQ3\n" - "MTkyX0NMS19FWFRfTUNMSzI6DQo+ID4gLQkJc3QtPm1jbGsgPSBBRDcxOTJfSU5UX0ZSRVFfTUha\n" - "Ow0KPiA+IC0JCWJyZWFrOw0KPiA+ICAJY2FzZSBBRDcxOTJfQ0xLX0lOVDoNCj4gPiAgCWNhc2Ug\n" - "QUQ3MTkyX0NMS19JTlRfQ086DQo+ID4gLQkJaWYgKHBkYXRhLT5leHRfY2xrX2h6KQ0KPiA+IC0J\n" - "CQlzdC0+bWNsayA9IHBkYXRhLT5leHRfY2xrX2h6Ow0KPiA+IC0JCWVsc2UNCj4gPiAtCQkJc3Qt\n" - "Pm1jbGsgPSBBRDcxOTJfSU5UX0ZSRVFfTUhaOw0KPiA+ICsJCXN0LT5tY2xrID0gQUQ3MTkyX0lO\n" - "VF9GUkVRX01IWjsNCj4gPiAgCQlicmVhazsNCj4gPiArCWNhc2UgQUQ3MTkyX0NMS19FWFRfTUNM\n" - "SzI6DQo+ID4gKwkJaWYgKGFkNzE5Ml92YWxpZF9leHRlcm5hbF9mcmVxdWVuY3kocGRhdGEtDQo+\n" - "ID4gPmNsb2NrX3NvdXJjZV9zZWwpKSB7DQo+ID4gKwkJCXN0LT5tY2xrID0gcGRhdGEtPmNsb2Nr\n" - "X3NvdXJjZV9zZWw7DQo+ID4gKwkJCWJyZWFrOw0KPiA+ICsJCX0NCj4gPiArCQkvKiBGQUxMVEhS\n" - "T1VHSCAqLw0KPiA+ICAJZGVmYXVsdDoNCj4gPiAgCQlyZXQgPSAtRUlOVkFMOw0KPiA+ICAJCWdv\n" - dG8gb3V0Ow0KPiANCj4g + "On Sun, 2018-01-14 at 12:37 +0000, Jonathan Cameron wrote:\n" + "> On Wed, 10 Jan 2018 13:29:54 +0200\n" + "> <alexandru.ardelean@analog.com> wrote:\n" + "> \n" + "> > From: Alexandru Ardelean <alexandru.ardelean@analog.com>\n" + "> > \n" + "> > According to the datasheet:\n" + "> > * 0 - external crystal, connected from pin MCLK1 to MCLK2\n" + "> \n" + "> What frequency of crystal? My quick read of the datasheet\n" + "> implies this may be flexible. Possibly as flexible as\n" + "> the clock option...\n" + "\n" + "I think you're right about this.\n" + "Will re-visit this.\n" + "\n" + "Is it ok if I re-spin this as a standalone patch ?\n" + "\n" + "Since I'm new around here, maybe it would probably be good to try to\n" + "send one patch at a time and resolve synchronization [between what I\n" + "deliver vs recommended ways of doing things].\n" + "\n" + "> \n" + "> \n" + "> > * 1 - external clock, applied to MCLK2 pin\n" + "> > * 2 - internal 4.92 Mhz clock; pin MCLK2 is tristated\n" + "> > * 3 - internal 4.92 Mhz clock; internal clock is available on MCLK2\n" + "> > \n" + "> > Which means that the external clock value only has sense\n" + "> > for value 1 (AD7192_CLK_EXT_MCLK2).\n" + "> > \n" + "> > Also added range validation for the external frequency\n" + "> > setting, which the datasheet mentions that it's\n" + "> > between 2.4576 and 5.12 Mhz.\n" + "> > \n" + "> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>\n" + "> > ---\n" + "> > drivers/staging/iio/adc/ad7192.c | 22 +++++++++++++++-------\n" + "> > 1 file changed, 15 insertions(+), 7 deletions(-)\n" + "> > \n" + "> > diff --git a/drivers/staging/iio/adc/ad7192.c\n" + "> > b/drivers/staging/iio/adc/ad7192.c\n" + "> > index 7f204013d6d4..7bc04101d133 100644\n" + "> > --- a/drivers/staging/iio/adc/ad7192.c\n" + "> > +++ b/drivers/staging/iio/adc/ad7192.c\n" + "> > @@ -141,6 +141,8 @@\n" + "> > #define AD7192_GPOCON_P1DAT\tBIT(1) /* P1 state */\n" + "> > #define AD7192_GPOCON_P0DAT\tBIT(0) /* P0 state */\n" + "> > \n" + "> > +#define AD7192_EXT_FREQ_MHZ_MIN\t2457600\n" + "> > +#define AD7192_EXT_FREQ_MHZ_MAX\t5120000\n" + "> > #define AD7192_INT_FREQ_MHZ\t4915200\n" + "> > \n" + "> > /* NOTE:\n" + "> > @@ -217,6 +219,12 @@ static int ad7192_calibrate_all(struct\n" + "> > ad7192_state *st)\n" + "> > \t\t\t\tARRAY_SIZE(ad7192_calib_arr));\n" + "> > }\n" + "> > \n" + "> > +static inline bool ad7192_valid_external_frequency(u32 freq)\n" + "> > +{\n" + "> > +\treturn (freq >= AD7192_EXT_FREQ_MHZ_MIN &&\n" + "> > +\t\tfreq <= AD7192_EXT_FREQ_MHZ_MAX);\n" + "> > +}\n" + "> > +\n" + "> > static int ad7192_setup(struct ad7192_state *st,\n" + "> > \t\t\tconst struct ad7192_platform_data *pdata)\n" + "> > {\n" + "> > @@ -245,16 +253,16 @@ static int ad7192_setup(struct ad7192_state\n" + "> > *st,\n" + "> > \n" + "> > \tswitch (pdata->clock_source_sel) {\n" + "> > \tcase AD7192_CLK_EXT_MCLK1_2:\n" + "> > -\tcase AD7192_CLK_EXT_MCLK2:\n" + "> > -\t\tst->mclk = AD7192_INT_FREQ_MHZ;\n" + "> > -\t\tbreak;\n" + "> > \tcase AD7192_CLK_INT:\n" + "> > \tcase AD7192_CLK_INT_CO:\n" + "> > -\t\tif (pdata->ext_clk_hz)\n" + "> > -\t\t\tst->mclk = pdata->ext_clk_hz;\n" + "> > -\t\telse\n" + "> > -\t\t\tst->mclk = AD7192_INT_FREQ_MHZ;\n" + "> > +\t\tst->mclk = AD7192_INT_FREQ_MHZ;\n" + "> > \t\tbreak;\n" + "> > +\tcase AD7192_CLK_EXT_MCLK2:\n" + "> > +\t\tif (ad7192_valid_external_frequency(pdata-\n" + "> > >clock_source_sel)) {\n" + "> > +\t\t\tst->mclk = pdata->clock_source_sel;\n" + "> > +\t\t\tbreak;\n" + "> > +\t\t}\n" + "> > +\t\t/* FALLTHROUGH */\n" + "> > \tdefault:\n" + "> > \t\tret = -EINVAL;\n" + "> > \t\tgoto out;\n" + "> \n" + > -103994817dc663a639e4c4589f1435e06b31a9b4c6ef6311d51e16c623c671ce +716643b9a1950030bffe291d03ea5f18372eb321d9c57e51f70db7e7ead5c550
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